JPH10301848A - Virtual storage device having multiple page sizes - Google Patents

Abstract

(57) [Summary] [Problem] With a single virtual page size, performance cannot be met because of application requirements. A simple increase in the type of virtual page size causes an increase in the amount of implemented hardware and a decrease in performance. SOLUTION: An address conversion table (2) having a hierarchical structure
3, 24, 25, 26) to provide a means for designating the number of lower table levels, that is, the virtual page size for the virtual storage area, and to provide an extended virtual page setting instruction to enable multiple virtual page sizes. To solve the above problem. [Effect] Since multiple virtual page sizes can be provided with a small OS overhead, the performance of the computer system is improved and the memory resources and the hardware amount can be reduced. Further, more types of extended virtual page sizes can be provided, and the speed of execution of application programs can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a virtual storage of a computer system, and more particularly to a virtual storage device that enables an application program to efficiently use a plurality of virtual storage page sizes.

[0002]

2. Description of the Related Art In many computer systems,
The virtual storage is divided into single-sized pages (called virtual pages), and the virtual page size is 4 kilobytes (hereinafter KB).
Abbreviated). For example, the document "IBM C
corporation, “Enterprise S
system Architecture / 390 Pr
includes of Operation ", I
BM Corporation, pp. 3-1-3
In the mainframe virtual storage architecture (referred to as well-known example 1) described in “-51, 1994”, the virtual storage has a size of 2 gigabytes (hereinafter abbreviated as GB) indicated by a 31-bit address, and the virtual storage has a size of 4 KB. Divided into virtual pages. A virtual page is a fixed-length unit that allocates real storage to virtual storage. The real storage device is also divided into units of 4 KB (called real pages), and has a key storage entry that holds information including a key for access protection for each real page. An address translation mechanism that translates a virtual address into a real address uses an address translation table to translate a virtual page address into a real page address so that a virtual page can be placed at any position in a real storage device. The address translation table has a two-stage hierarchical structure of a segment table and a page table using partial bit strings of virtual addresses as indexes. 31
The upper 11 bits of the bit address are used as the index of the segment table, and the next 8 bits are used as the index of the page table. Therefore, one address space of 2 GB is divided into 2048 segments each having a size of 1 megabyte (hereinafter abbreviated as MB), and the segment is divided into 256 pages. One segment table corresponds to the entire 2 GB address space, and 204
It has eight entries. Each entry of the segment table holds the address of the page table. One page table corresponds to one segment and has 256 entries. The real page address of the conversion result is
Since the virtual page size is stored only in the page table entry, the virtual page size is only one type of 4 KB. The specification for invalidating the page table entry invalidates the corresponding entry of the address translation buffer together with the entry of the address translation table.

[0003] Japanese Patent Publication No. Hei 7-104818 (known example 2)
Discloses a device and a method for extending a virtual address to 47 bits or 63 bits with respect to the virtual storage device of the publicly known example 1. A two-stage or three-stage address conversion table is newly provided as an upper layer of the address conversion table for converting the 31-bit address of the known example 1. However, the virtual page size is 4K as in the known example 1.
B is only one type.

Japanese Patent Application Laid-Open No. 4-319747 (known example 3)
Discloses an address translation mechanism for efficiently providing a plurality of virtual page sizes. The address translation mechanism of the third prior art includes a single set of address translation buffers capable of indexing a plurality of virtual page size entries. The address translation buffer is a mechanism for accelerating address translation by caching address translation information originally obtained by referring to an address translation table on the main memory in a memory and a circuit that can be accessed faster than the main memory. However, it does not disclose an address conversion table for realizing a plurality of virtual page sizes.

[0005] The document "SPARC International"
nal, Inc. , “TheSPARC Arch
item Manual Version
8 ", Prentice-Hall, Inc., p.
p. 241-259, 1992 ".
Memory-mapped unit architecture (known example 4)
) Converts a virtual address into a real address using an address conversion table having a hierarchical structure of up to three levels. However, it is also possible to complete the address conversion by obtaining the real page address from the root pointer or the table entry of the first or second stage. Route pointer, first row,
When the address conversion is completed in any of the second and third stages, the virtual page sizes become 4 GB, 16 MB, 2
56 KB, 4 KB. Each table entry has information indicating whether a real page address is held in the entry. Therefore, the virtual page size can be set finely for each area. The instruction to invalidate the address translation buffer designates a virtual address to be invalidated and any one of the three types of virtual page sizes. The invalidation instruction invalidates all entries in the address translation buffer corresponding to the virtual storage area determined by the specified virtual address and the virtual page size. However, the virtual page sizes that can be specified are four types of sizes supported by the address translation mechanism.

[0006]

The virtual storage architecture of the computer system of the prior art 1 supports only a single virtual page size of 4 KB. Known example 2 also does not specifically disclose expansion of the page size.
The page size is 4 KB. These known examples have the following problems.

The first problem is that, with a relatively small single page size such as 4 KB, the amount of real storage required for the address translation table, the CPU overhead required for managing virtual pages, and the paging I / O overhead increase. That is. Since the number of pages is larger in the small page size than in the large page size, necessary resources and overhead increase in proportion to the number of pages. In particular, in a large-capacity virtual memory such as the 64-bit architecture of the publicly known example 2, this problem becomes more remarkable.

A second problem is that the block size of data handled by an application program is not single, but various, and one page size can efficiently or rapidly execute various application programs executed on a computer system. It cannot be processed. For example, in online transaction processing, a block size for bringing database data to virtual storage is generally about 8 KB, and the access pattern of virtual storage is almost random access as a block. In this case, a small page size is desirable. With a small page size, the actual storage required for the data block being accessed can be reduced and the amount of data transferred from the secondary storage to the real storage can be reduced, thus improving processing performance. On the other hand, in science and technology calculations, large arrays placed in virtual storage are often accessed almost sequentially. In this case, a large page size of 1 MB or more is desirable. With a large page size, the number of data transfers from the secondary storage device to the real storage device due to a virtual memory page fault interrupt can be reduced, and overhead and data transfer waiting time generated in proportion to the number of data transfers are reduced. As a result, processing performance is improved. In a database process such as a recent data warehouse, a block size of about several tens KB to several hundred KB, which is an intermediate size between the above two examples, is used.

Known examples 3 and 4 are intended to realize a plurality of virtual page sizes in one virtual storage space to cope with the variety of virtual storage utilization of application programs. Known example 3 discloses an address translation buffer for a plurality of virtual page sizes, but does not disclose other means necessary for a virtual storage device such as an address translation table. Known example 4 discloses an address conversion table for a plurality of virtual page sizes. Even if these known examples are combined, there are the following problems.

A third problem is an increase in the management overhead of an operating system (hereinafter abbreviated as OS) due to the fact that the area unit for specifying the virtual page size in the prior art 4 is too small. A flag indicating whether or not a real page address is held in the entry must be set in all valid entries of the address conversion table, and the OS
Management overhead increases. For most applications,
It is often sufficient if the virtual page size can be specified collectively in a large area unit such as 2 GB. For example, even if an existing 32-bit architecture computer system in which a single virtual page size is mostly used is to be expanded to 64 bits, an address of less than 2 GB or 4 GB, which is the virtual storage capacity of the conventional 32-bit architecture, is conventionally used. When the virtual page size is set to 4 KB and the page size of the virtual storage area on the virtual page size is expanded, compatibility and improvement in performance can be achieved.

A fourth problem is that the known examples 3 and 4 also have a small number of virtual page sizes and cannot meet various demands of application programs. Even in the known example 4, 4G
B, 16 KB, 256 KB, 4 KB and the page size are too far apart. Simply increasing the type of the virtual page size leads to a processing delay in the address translation buffer that is critical for performance and an increase in the amount of mounting.

[0012]

In order to solve the above-mentioned problems, the present invention provides a unit (called a region) of a virtual storage area represented by a conversion table having at least two or more lowermost m stages in a hierarchical structure. The number of table entries from the (n−m + 1) th to nth address translation tables counted from the top table to read the actual storage page address of the translation result, that is, the number of translation table rows Page size specifying means for specifying any one of a plurality of virtual storage page sizes determined by the following, and address conversion means for converting a virtual address to a real address in accordance with the page size specification means. The storage device can reduce the overhead of specifying the page size, and the first and third problems are solved. It is determined.

Further, the present invention provides an address translation table means for translating a virtual address into a real address, and an address of an extended virtual storage page having a size which is a multiple of the virtual storage page size provided by the address translation table means. In response to a translation information setting instruction, an extended virtual memory that sets address translation information specified by the instruction in one or more address translation table entries corresponding to the address of one extended virtual memory page specified by the instruction By providing the page setting means, it is possible to provide the program with more types of extended virtual page sizes while keeping the types of virtual page sizes of the address translation mechanism small, and the second and fourth problems are solved. Will be resolved.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the present invention will be described.
This will be described with reference to the drawings. In the present specification, “embodiments of the invention” will be referred to as “examples”.

An embodiment of the present invention will be described with reference to FIGS. This embodiment is based on the literature “IBM Corporation,“ Enterp.
rise System Architecture /
390 Principlesof Operation
n ", IBM Corporation, pp.
3-1-3-51, 1994, a virtual address is extended to 63 bits and a general-purpose register is extended to 64 bits based on the mainframe virtual memory architecture described in
A virtual storage device of a computer system that provides a program with multiple virtual page sizes.

FIG. 2 is a configuration diagram of the virtual storage and the real storage of the present embodiment. First, the function of the multiple virtual page size provided to the program by the present embodiment will be described with reference to FIG.

The virtual storage space 100 has a capacity of 2 63 bytes, and can select a virtual page size supported by the address translation mechanism 103 for each region which is a virtual storage area of 2 GB. Address translation mechanism 103
Provides two types of virtual page sizes, 4 KB and 1 MB. Further, there is an extended virtual page size provided to a program by a series of control instructions for virtual memory management called an extended page instruction. The extended virtual page size is specified as an operand of the extended page instruction, and 4K
A multiple of B can be specified. The extended virtual page is 4
It is a collection of a plurality of KB or 1 MB virtual pages, and is realized by setting a plurality of entries corresponding to the extended virtual page of the address translation table with one instruction by an extended page instruction. In the example of FIG. 2, region 1
The virtual page size of 10 and region 111 is 4 KB,
The virtual page size of the region 112 is 1 MB.
Further, the region 111 is set to 32
It is set as a KB extended virtual page. In this example, the entire region 111 is 32 KB. However, if an extended page command is used, an extended virtual page having a size different from 32 KB can be set in the region 111. The real storage device 101 has a size of 4 KB according to a unit having an entry of the key storage device 102, that is, a real page size.
It is divided into two areas: a page area 113 and a 1 MB page area 114. The 4 KB page area 113 stores the key storage 11 having an entry corresponding to every 4 KB of the real storage.
5, and the 1 MB page area 113 includes a key storage 116 having an entry corresponding to each 1 MB of the real storage. The actual storage amounts of the 4 KB page area 113 and the 1 MB page area 113 are variable for each system. Due to the address translation mechanism 103, the 4 KB virtual page becomes 4
A 1 MB virtual page is mapped to a real page in the 1 MB page area 114 on a real page in the KB page area 113. The extended virtual page of 32 KB size is mapped to eight real pages in the 4 KB page area 113 by eight entries of the page table 26. The eight entries of the page table 26 can be set by an extended page instruction of one instruction.

Next, the configuration and operation of the address translation mechanism 103 of this embodiment will be described with reference to FIGS. The configuration of FIG. 1 will be described. The main components of the address translation mechanism 103 are a virtual address register 10 for holding a virtual address generated at the time of execution of an instruction, two address translation buffers (TLBs) 21 for a 4 KB page and a 1 MB page,
22, a first region table (FRT) 23, a second region table (SRT) 24, and a segment table (ST), which are address conversion tables having a four-level hierarchical structure.
25, a page table (PT) 26, and a real address register 30. The TLB is a mechanism for accelerating address translation by caching address translation information obtained by referring to an address translation table stored in a real storage device in a memory and a circuit that can be accessed faster than the real storage device. FIG. 3 shows the first region table origin register (FRTOR) 20 and the FRT entry (FR
TE) 151, SRT entry (SRTE) 152, S
T entry (STE) 153, PT entry (PTE)
154 shows the format. Except for PTE, the lower table origin, that is, the head address 1 of the table
55,157,159,162 and table length 156,1
58, 161, and 163. Except for the FRTOR 150, it has an invalid bit (I) of the entry, and the STE 153
Has a common bit (C) indicating that the segment is a common area between spaces. Further, the SRTE 152 has a large page bit (L) 160 indicating that the page size of the corresponding region is 1 MB. PTE1
54 has a real page address (PFRA) 164.
When the L bit 160 is on, the field 162 of the STE 153 becomes PFRA, and the lower PT 26 does not exist. These address conversion tables use a partial bit string of the virtual address as an index.

The operation will be described with reference to FIG. The virtual page address represented by the upper 51 bits of the virtual address register 10 has two address translation buffers (TLBs) 21 and 22.
Is input to If any TLB is hit, the real page address (PFRA) of the real page assigned to the virtual page of the virtual page address is changed to the AND gate 4
It is output from one of 0 and 41, and is set to the upper 51 bits of the real address register 30 via the OR gate 44. The 12 bits of displacement (D) of the virtual address register 10 are set to the lower 12 bits of the real address register 30 as they are. When the TLB is hit as described above, the address conversion tables 23, 24, and 2 of the real storage device are used.
There is no access to 5, 26, and address conversion is completed at high speed. If no hit occurs in any of the TLBs, the address conversion is performed with reference to an address conversion table in the real storage device. An address is obtained from the FRTOR 20 and the FRX of the virtual address register 10 to read the FRTE 151, and an address is obtained from the SRTO 157 and the SRX to read the SRTE 152. STO159 and S
The STE 153 is read for an address from X.
If the L bit 160 is on, it is a 1 MB page region, so the PFR in the field 162 of the STE 153
A is set in the upper 51 bits of the real address register 30. If the I bit is on, a page exception is generated at that point. When the L bit 160 is off, the region is a 4 KB page region. Therefore, an address is obtained from the PTO 162 and PX, and the PTE 15 is read out.
The PFRA of the fifteen fields 164 is set in the upper 51 bits of the real address register 30. If the I bit is on, a page exception is generated at that point. The 12 bits of displacement (D) of the virtual address register 10 are set to the lower 12 bits of the real address register 30 as they are. If any of the I bits of the accessed entries 151 and 152 is on, an address translation exception is generated at that time.

Next, the configuration and operation of the extended page instruction of this embodiment will be described with reference to FIGS. FIG. 4 is a configuration diagram of a processing mechanism for an extended page setting instruction and an invalidation instruction.

The extended page setting instruction (SXPTE) is an instruction for setting the address conversion information of the extended virtual page in one or a plurality of STEs 153 or PTEs 154 corresponding to the address of the extended virtual page. The instruction format specifies two general-purpose register numbers as operands.
An R1 register and an R2 register, and an R2 + 1 register, which is a register next to R2, and three operands are specified. The R1 register 200 contains the P of the extended virtual page.
In the TE154 data, the R2 register 201 stores SRTE152 data indicating the ST25 and PT26 to be set, and R2
In the +1 register 202, SX 204 and PX 205 representing the extended virtual page address and the extended virtual page size (P
S) 206 is set in advance. The PS 206 is specified by a divisor of 4 KB.

When the processing is started, if the L bit 203 of the R2 register 201 is on, the processing mechanism of the SXPTE performs the processing for the 1 MB virtual page.
The micro program 210 is started. The microprogram 210 calculates the STO of the R2 register 201 and R2
The address of the leading STE 153 corresponding to the extended virtual page is obtained from the SX 204 of the +1 register 202. First S
The PTE 154 data of the R1 register 200 is written from the TE 153 to the STE specified by the PS 206. However, from the second and subsequent STEs, PFR
A is written in increments of 1 MB. By doing so, the set plurality of STEs 153 can convert the virtual address in the extended virtual page to the correct real address, like one PTE for the extended virtual page. If the L bit 203 of the R2 register 201 is off, the SXPTE4K microprogram 211 that performs processing for a 4 KB virtual page is started. The microprogram 211 calculates the STO of the R2 register 201 and R2 +
The address of the leading PTE 154 corresponding to the extended virtual page is obtained from SX 204 and PX 205 of one register 202. The PTE 154 data of the R1 register 200 is written from the first PTE 154 to the PTE specified by the PS 206. However, from the second and subsequent PTEs, PFRA is incremented by 4 KB and written.

The extended page invalidation instruction (IXPTE) is
This is an instruction to invalidate one or more STEs 153 or PTEs 154 and TLBs 21 and 22 entries corresponding to the address of the extended virtual page. The instruction format specifies two general-purpose register numbers as operands.
The R2 register and R
Two operands, the R2 + 1 register, which is the next numbered register, are specified. SRTE15 indicating ST25 and PT26 to be invalidated is stored in the R2 register 201.
SX 204, PX 205, and extended virtual page size (PS) 206 representing an extended virtual page address are set in the 2 data, R2 + 1 register 202. PS206
Is specified as a divisor of 4 KB.

When the processing is started, if the L bit 203 of the R2 register 201 is on, the IXPTE processing mechanism performs processing for a 1 MB virtual page.
The micro program 212 is started. The microprogram 212 calculates the STO of the R2 register 201 and R2
The address of the leading STE 153 corresponding to the extended virtual page is obtained from the SX 204 of the +1 register 202. First S
Turn on the I bit of STE 153 from TE 153 to STE in the range specified by PS 206, and TLB for 1MB and 4KB corresponding to the virtual address of the STE
The entries 22 and 21 are invalidated. If the L bit 203 of the R2 register 201 is off, an IXPTE4K microprogram 2 that performs processing for a 4 KB virtual page
13 is started. The micro program 213 is
The address of the leading PTE 154 corresponding to the extended virtual page is obtained from the STO of the second register 201 and the SX 204 and PX 205 of the R2 + 1 register 202. Top PTE15
From 4 to the PTE in the range specified by the PS 206, the I bit is turned on, and the entries of the 1MB and 4KB TLBs 22 and 21 corresponding to the virtual address of the PTE are invalidated.

FIG. 5 is a configuration diagram of the extended page key operation command.

Extended page key setting command (SXSKE)
Stores the access protection information of the extended real page in one or a plurality of key storages 115,
This is an instruction to be set in the 116 entry. This is an instruction format for designating two general-purpose register numbers as operands, and designates two operands of an R1 register and an R2 register. The access protection information (ACCCFRC) 223 of the extended virtual page is set in the R1 register 220, and the PFRA 224 and the extended real page size (PFS) 225 indicating the extended real page address indicating the key storage entry to be set are set in the R2 register 221. deep. PFS225
Is specified as a divisor of 4 KB.

When the SXSKE processing mechanism starts processing, the SXSKE microprogram 232 is started. The microprogram 232 stores the R2 register 22
1 from the first key storage entry pointed to by the PFRA 224
Up to the key storage entry in the range specified by the FS 225
The access protection information 223 of one register 220 is written. If the key storage entry to be set is the 4 KB area key storage 115, the number of entries to be set is PFS 225.
In the case of 1 MB area key storage 116, the number of entries to be set is the number obtained by dividing PFS 225 by 256.

Extended page key reset command (RXRB
E) is an instruction to reset the reference bit (R) of one or more entries of the key storages 115 and 116 corresponding to the address of the extended real page. The instruction format specifies two general register numbers as operands.
Only the operand of two registers is specified. In the R2 register 221, a PFRA 224 indicating an extended real page address indicating a key storage entry to be set and an extended actual page size (PFS) 225 are set. PFS225
Is specified as a divisor of 4 KB.

The RXRBE processing mechanism starts the RXRBE microprogram 233 when the processing is started. The microprogram 233 stores the R2 register 22
1 from the first key storage entry pointed to by the PFRA 224
The R bit of the access protection information 223 is reset until the key storage entry in the range specified by the FS 225.
The key storage entry to be set is 4 KB area key storage 1
If it is 15, the number of entries to be set is equal to PFS 225, and if it is 1 MB area key storage 116, the number of entries to be set is the number obtained by dividing PFS 225 by 256.

Extended page key insertion instruction (IXSKE)
Is an instruction to insert the access protection information of one or more entries of the key storages 115 and 116 corresponding to the address of the extended real page into the register. An instruction format that specifies two general-purpose register numbers as operands.
Two operands, register 1 and register R2, are specified. An L bit 222 indicating whether the area is a 1 MB real page area and access protection information (ACCCFRC) 223 for an extended virtual page are inserted into the R1 register 220. In the R2 register 221, a PFRA 224 indicating an extended real page address indicating a key storage entry to be set and an extended actual page size (PFS) 225 are set. PFS22
5 is designated by a divisor of 4 KB.

When the IXSKE processing mechanism starts processing, the IXSKE microprogram 230 is started. The microprogram 230 stores the R2 register 22
The access key (ACC) and the fetch bit (F) are read from the access protection information of the leading key storage entry pointed to by the PFRA 224 of 1 and inserted into the R1 register 220. Regarding the reference bit (R) and the change bit (C),
The logical sum of all the R bits and the logical sum of all the C bits from the first key storage entry to the key storage entry in the range specified by the PFS 225 are inserted into the R1 register 220. If the target key storage entry is the 4KB area key storage 115, the number of entries to be read is equal to the PFS 225. If the target key storage entry is the 1MB area key storage 116, the number of entries to be read is the number obtained by dividing the PFS 225 by 256.

[0032]

According to the virtual storage device of the present invention, a multi-page size virtual storage device in which a large page size and a small page size are mixed can be provided to a program with a small OS overhead. And the memory resources required for virtual storage management can be reduced. Furthermore, since an extended page size is realized by reducing the number of stages of the address conversion table, there is no need to provide a new conversion table, so that
The amount of hardware can be reduced.

Further, according to the virtual storage device of the present invention, it is possible to provide a program with more types of extended virtual page sizes while reducing the types of virtual page sizes of the address translation mechanism, and to provide various types of page sizes for various applications. Since the request can be satisfied, the speed of execution of the application program is increased.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an address translation mechanism according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of virtual storage and real storage according to an embodiment of the present invention.

FIG. 3 is a diagram showing a format of an address conversion table according to one embodiment of the present invention.

FIG. 4 is a configuration diagram of a processing mechanism for an extended page setting instruction and an invalidation instruction according to an embodiment of the present invention.

FIG. 5 is a configuration diagram of a processing mechanism of an extended page key operation command according to one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 virtual address register 21, 22 address conversion buffer 23, 24, 25, 26 address conversion table 30 real address register 100 virtual storage space 101 real storage device 102 key storage device.

Claims (8)

[Claims] 1. An address translation table means having a hierarchical structure of at least two or more stages, wherein virtual storage is provided for a computer program, and a partial bit sequence of the virtual address is used as an index for converting a virtual address into a real address. A virtual storage device having at least two stages at least in the lowest level of the hierarchical structure, and each region which is a unit of a virtual storage area represented by an m-level conversion table, counting from the highest level table (n−m
+1) Of a plurality of virtual storage page sizes determined by the number of stages of the conversion table by a function of designating from which table entry of the address conversion table of the stage from the nth stage the real storage page address of the conversion result is read A virtual storage device comprising: a page size specifying unit that specifies any one of the following: and an address conversion unit that converts a virtual address to a real address according to the page size specification unit. 2. The region is 32 bits or 31 bits.
2. The virtual storage device according to claim 1, wherein the virtual storage device has a size represented by bits. 3. An entry for selecting one of the plurality of virtual storage page sizes for each area of the real storage device and holding access protection information for each real storage page having a size equal to the selected page size. 2. The virtual storage device according to claim 1, further comprising key storage means. 4. A virtual storage device for providing virtual storage to a computer program, comprising: an address conversion table for converting a virtual address to a real address; and a virtual storage page size provided by the address conversion table. In response to an instruction to set the address translation information of an extended virtual memory page having a size that is a multiple of, the one or more address translation table entries corresponding to the address of one extended virtual memory page specified by the instruction include A virtual storage page setting means for setting address translation information specified by the instruction. 5. The address translation table means, comprising: an address translation buffer comprising a memory circuit which holds a cache of address translation information and can be accessed at a higher speed than a main memory; and a virtual storage page size provided by the address translation table means. In response to an instruction to invalidate address translation information of an extended virtual memory page having a size that is a multiple of the address of one or more address translation buffer entries corresponding to the address of one extended virtual memory page specified by the instruction. 5. The virtual storage device according to claim 4, further comprising an extended virtual storage page invalidating means for invalidating the conversion information. 6. A key storage unit having an entry for holding access protection information for each real storage page having a size equal to a virtual storage page provided by the address conversion table unit, and a size being a multiple of the real storage page size. In response to the access protection information setting instruction of the extended real storage page having
5. An extended real storage page setting means for setting access protection information specified by the instruction in one or more key storage entries corresponding to an address of one extended real storage page specified by the instruction. A virtual storage device according to claim 1. 7. The virtual storage device according to claim 4, wherein said address conversion table means further comprises means for providing a plurality of virtual storage page sizes. 8. The address translation buffer of the address translation table means includes means for providing a plurality of virtual storage page sizes, and the extended virtual storage page invalidating means comprises: Invalidate the address translation information of all the address translation buffer entries corresponding to the address of one extended storage page specified by the address translation information invalidation instruction of the virtual storage page size, regardless of whether it is for the size of the virtual storage page. 6. The virtual storage device according to claim 5, further comprising means for executing.