JPH10301895A - Bus extender - Google Patents

Abstract

(57) Abstract: Provided is a bus expansion device that can transfer a data width between two parallel buses having different data widths in accordance with the data width of the bus. SOLUTION: Parallel data DB0 to 63 from a data signal line 41 of an expansion bus 40 are held by an FF 22 and given to a selector 23. The selector 23, based on the clock signal CK _A, and outputs to the buffer 24 by selecting a lower bit DB0~31 and upper bits DB32~63 alternately. The transfer control unit 25 controls on / off of the output from the buffer 24 to the system bus 30 based on the destination and the data length of the transfer data. On the other hand, the system bus 30
Of the parallel data DA0-31 from the data signal line 31 of
The buffer 28 is held alternately by the FFs 27a and 27b.
a, 28b. The transfer control unit 29 controls the buffers 28a and 28b based on the destination data length of the transfer data.
On / off control of the output from the controller to the expansion bus 40 is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus having a plurality of control devices, such as an electronic exchange, which is used to expand the drive capacity when connecting the control devices with a parallel bus. The present invention relates to an expansion device, and more particularly to a bus expansion device between parallel buses having different data widths.

[0002]

2. Description of the Related Art FIG. 2 is a schematic block diagram showing an example of a multiprocessor system using a conventional bus expansion device. This multiprocessor system has a master processor 1 that controls the entire system, and a plurality of slave processors 2a, 2b,... That perform processes assigned to each under the control of the master processor 1.
The master processor 1 includes the slave processors 2a and 2
are connected to a system bus 3 for controlling b,. The system bus 3 includes a plurality of data signal lines 3a for transferring data between processors in parallel, a transfer control line 3b for designating a transfer direction of the data, and a clock signal line 3c for transmitting a system common clock signal CLK. And so on. A plurality of slave processors 2a, 2b,... Are commonly connected to the system bus 3. On the other hand, this multiprocessor system has a system bus 3
Similarly, a plurality of data signal lines 4a, transfer control lines 4b,
And an extension bus 4 composed of a clock signal line 4c and the like. A plurality of slave processors 2c, 2d,... Are commonly connected to the extension bus 4.

[0005] The system bus 3 and the expansion bus 4 are connected via a bus expansion device 10. Bus expansion device 1
0 is a device for distributing the load to the expansion bus 4 when the number of slave processors 2a, 2b,... Connected to the system bus 3 is large and exceeds the bus driving capability of each processor 1, 2a. It is. The bus expansion device 10
It has a three-state buffer 11. The input side of the 3-state buffer 11 is connected to each data signal line 3 of the system bus 3.
a, and the output side of each data signal line 4 of the extension bus 4
a. The control terminal of the three-state buffer 11 is supplied with a signal from a transfer control line 3b of the system bus 3 via inverters 12 and 13 which are cascaded. The bus expansion device 10 has a three-state buffer 14. The input side of the three-state buffer 14 is connected to each data signal line 4 a of the extension bus 4, and the output side is connected to each data signal line 3 a of the system bus 3. The output side of the inverter 12 is connected to the control terminal of the three-state buffer 14. The output side of the inverter 12 is further connected to the transfer control line 4 b of the extension bus 4 via the inverter 15. And the system bus 3
Is connected to the cascaded inverter 1
It is connected to the clock signal line 4c of the extension bus 4 via the buses 6 and 17.

In a multiprocessor system having such a bus expansion device 10, when data is output from the master processor 1, a plurality of bits of data are output in parallel to a data signal line 3a of a system bus 3 and a transfer control line is output. A signal of level "H" is output to 3b.
Thereby, data from the master processor 1 is transferred to the data signal line 4 a of the extension bus 4 via the three-state buffer 11. On the other hand, when the master processor 1 receives data from the slave processor 2c connected to the extension bus 4, for example, the master processor 1
After giving an instruction to output data to the slave processor 2c, a signal of level "L" is output to the transfer control line 3b. As a result, data output from the slave processor 2c in parallel to the data signal line 4a of the extension bus 4 is transferred to the data signal line 3a of the system bus 3 via the three-state buffer 15, and is received by the master processor 1. Can be.

[0005]

However, a multiprocessor system using a conventional bus expansion device has the following problems. That is, the number of data signal lines 3a of the system bus 3 and the number of data signal lines 4a of the extension bus 4 are the same. Therefore, the data widths of the master processor 1 and the slave processor 2a connected to the system bus 3 and the slave processor 2 connected to the extension bus 4
If the data width such as c is equal, no problem occurs.
However, a multiprocessor system has emerged in which, for example, a processor that processes 64-bit data and a processor that processes 32-bit data are combined in accordance with the processing content. In such a case, it is necessary for the processor with the larger data width to perform the data transfer in accordance with the data width of the processor with the smaller data width, which complicates the processing on the software and increases the data transfer speed. There was a problem that it became difficult. SUMMARY OF THE INVENTION The present invention solves the problem of the prior art, and converts and transfers a data width between two parallel buses having different data widths according to the data length transferred on the bus. It is intended to provide a bus expansion device that can be used.

[0006]

According to a first aspect of the present invention, there is provided an N-bit header section including information indicating a destination and a data length of a data, followed by one or more header sections. And N-bit unit data are sequentially transferred as N-bit data as parallel data of a first format.
, A header portion similar to the header portion, and one or more N-bit units of data following the header portion,
A bus expansion device that expands the driving capacity of a bus by connecting a second parallel bus that sequentially transfers parallel data of a second format paralleled by N bits at a time is configured as follows. ing. That is, the bus extension device receives a parallel data of the second format transferred on the second parallel bus and converts the parallel data into the parallel data of the first format. Monitoring the header section transferred on the second parallel bus, and when the destination information in the header section is addressed to the first parallel bus, for a time corresponding to the data length in the header section, A first transfer control unit that activates and outputs a first transfer control signal; and a first transfer control signal, the first transfer control signal being applied to the first parallel bus when the first transfer control signal is activated. And outputs the output signal of the first data converter to the first parallel bus, and disconnects the first parallel bus when the first transfer control signal is inactivated. And a data transfer unit.

[0007] Further, the bus expansion device receives the parallel data of the first format transferred on the first parallel bus and converts the parallel data into the parallel data of the second format. And the header section transferred on the first parallel bus, and when the destination information in the header section is addressed to the second parallel bus, the header section corresponds to the data length in the header section. A second transfer control unit that activates and outputs a second transfer control signal for a time, and the second transfer control signal is provided, and the second transfer control signal is activated when the second transfer control signal is activated. And outputs the output signal of the second data conversion unit to the second parallel bus,
A second data transfer unit that is disconnected from the second parallel bus when the second transfer control signal is inactivated. The second invention is the same as the first and second inventions of the first invention.
A bus expansion device that expands the driving capacity of the bus by connecting the parallel buses is configured as follows. That is, this bus expansion device includes a first data conversion unit, a first transfer control unit, a first data transfer unit,
And a second data conversion unit, and a second transfer control unit and a second data transfer unit as described below, which are different from the first invention.

The second transfer control section monitors the header section transferred on the first parallel bus, and the destination information in the header section is addressed to the second parallel bus, and
When the data length in the header portion is longer than a certain length, a second transfer control signal is activated and output for a time corresponding to the data length, and the destination information is addressed to the second parallel bus, and Activating and outputting the third transfer control signal for a time corresponding to the data length when the data length is equal to or less than the fixed length. The second data transfer unit receives the second and third transfer control signals, and connects to the second parallel bus when the second transfer control signal is activated. Output to the second parallel bus, and when the third transfer control signal is activated, the output signal is connected to the second parallel bus to convert the parallel data of the first format into The signal is output to the second parallel bus, and is disconnected from the second parallel bus when the second and third transfer control signals are inactivated.

According to the first aspect, since the bus expansion device is configured as described above, the following operation is performed. The 2N-bit parallel data transferred on the second parallel bus is converted into N-bit parallel data by the first data converter. Also, the N transferred on the first parallel bus
The parallel data of bits is converted into 2 bits by the second data converter.
It is converted into N-bit parallel data. When the destination of the parallel data transferred on the second parallel bus is the first parallel bus, the N-bit parallel data converted by the first data converter is controlled according to the control of the first transfer controller. Output to the first parallel bus via the first data transfer unit. On the other hand, if the destination of the parallel data transferred on the first parallel bus is the second parallel bus, the second data converted by the second data conversion unit
The N-bit parallel data is output to the second parallel bus via the second data transfer unit under the control of the second transfer control unit. According to the second aspect, the following operation is performed.

The 2N-bit parallel data transferred on the second parallel bus is converted into N-bit parallel data by the first data converter. The N-bit parallel data transferred on the first parallel bus is converted into 2N-bit parallel data by the second data converter. Second
If the destination of the parallel data transferred on the first parallel bus is the first parallel bus, the N-bit parallel data converted by the first data converter is transmitted to the first parallel bus under the control of the first transfer controller. Is output to the first parallel bus via the data transfer unit of the first embodiment. On the other hand, if the destination of the parallel data transferred on the first parallel bus is the second parallel bus and its data length is longer than a certain length, the 2N-bit parallel data converted by the second data converter is converted. The data is output to the second parallel bus via the second data transfer unit under the control of the second transfer control unit. If the destination of the parallel data transferred on the first parallel bus is the second parallel bus and the data length is equal to or less than a certain length, the N-bit parallel data on the first parallel bus Is output to the second parallel bus via the second data transfer unit under the control of the second transfer control unit.

[0011]

FIG. 1 is a configuration diagram of a bus expansion apparatus showing an embodiment of the present invention. This bus expansion device 20
Is to connect a first parallel bus (for example, a system bus) 30 and a second parallel bus (for example, an expansion bus) 40 to expand the driving capacity of the bus.
The system bus 30, N (e.g., 32) 32 data signal lines 31 parallel data DA0~DA31 is transferred bit, the control line 32 for transmitting a signal BS _A indicating the start timing of data to be transferred, the data and a signal BL _a control line 33 for transmitting, and a clock signal line 34 for transmitting a clock signal CK _a as a reference for the system bus 30 indicating that it is being transferred. And the signal B
S _A at the same time 32-bit parallel data transferred DA0
To DA31 are the destination DES and the data length L of the data.
The header section has information indicating EN. on the other hand,
Expansion bus 40, 2N (e.g., 64) the data signal line 41 of 64 the parallel data DB0~DB63 bits are transferred, the control line 42 for transmitting a signal BS _B indicating the start timing of data to be transferred, the data and a clock signal line 44 for transmitting a clock signal CK _B as a signal control line 43 for transmitting BL _B, and reference of the expansion bus 40 indicating that it is being transferred. The signal BS _B simultaneously transferred by 64-bit parallel data DB0~DB
63 is a destination DES and a data length LEN of the data.
Is included.

The bus expansion device 20 has a buffer 21 to which 64-bit parallel data DB0 to DB63 are supplied from a data signal line 41. An output side of the buffer 21 is connected to an input side of a flip-flop (hereinafter, referred to as “FF”) 22, and a clock terminal of the FF 22
The clock signal CK _B are given from the clock signal line 44. The output side of the FF 22 is connected to a data conversion unit (for example,
Selector 23). Selector 2
3 is a 64-bit parallel data DB given to the input side
0 to DB63, lower data DB0 to DB3
1, and selects and outputs 32-bit data of any of the upper data DBs 32 to 63. The control terminal of the selector 23 has a system bus 30
Clock signal line 34 is connected, and the clock signal CK _A
Accordingly, the lower data DB0 to DB31 and the upper data DB32 to DB63 are alternately selected and output. The output side of the selector 23 is connected to the input side of a data transfer unit (for example, a three-state buffer) 24, and the output side of the three-state buffer 24 is connected to the data signal line 31. The ON / OFF of the output of the three-state buffer is controlled by a control signal CON1 provided from the transfer control unit 25.

On the other hand, the data signal line 3 of the system bus 30
The 32-bit parallel data DA0 to DA31 on 1 are supplied to a buffer 26, and the output side of the buffer 26 is connected to a data converter 27. Data converter 27
Are FFs 27 each holding 32-bit data.
a, 27b, the frequency dividing circuit 27c for generating a timing signal by the clock signal CK _A and dividing it by 2 for each FF27a, 27b, and is configured with an inverter 27d. The parallel data DA0 to DA31 are stored in the FFs 27a and 27
It is given in common to the input side of the b, according divider circuits 27c divided clock signal CK _A, these FF27
a and 27b are held alternately. The lower data DB0 to DB31 of the parallel data DB0 to DB63 in the extension bus 40 are output to the FF 27a, and the upper data DB32 to DB63 are output to the FF 27b. On the output side of the data conversion unit 27,
The data transfer unit 28 is connected. Data transfer unit 28
Are 32-bit three-state buffers 28a and 28b
And an OR gate 28c for adding a control signal to the three-state buffer 28a. And F
The output sides of F27a and 27b are connected to the input sides of three-state buffers 28a and 28b, respectively. The output side of the three-state buffers 28a and 28b
Are connected to the 64 data signal lines 41. The output of the data transfer unit 28 is controlled by control signals CON2 and CON3 provided from a transfer control unit 29.

FIG. 3 is a configuration diagram of the transfer control unit 25 in FIG. The transfer control unit 25 is provided with data DB0 to DB31 output from the buffer 21, and has a destination determination unit 25a that decodes a destination DES included therein. When the destination DES of the data is the system bus 30, the destination determining unit 25 sets the output signal S25a to the level “H”. The output side of the destination determining unit 25 is connected to the input terminal D of the FF 25b. FF2
5 is connected to the control line 42 and the signal BS
_B is given. The output terminal Q of the FF 25b is connected to a first input terminal of a two-input AND gate (hereinafter, referred to as "AND") 25c. A second input terminal of AND25c is connected to the control line 43, the signal BL _B are given. FIG. 4 is a configuration diagram of the transfer control unit 29 in FIG. The transfer control unit 29 is provided with data DA0 to DA31 output from the buffer 26, and includes a destination determination unit 29a that decodes the destination DES included therein and a data length determination unit 29b that determines the data length LEN. Have. When the destination DES of the data is the system bus 40, the destination determining unit 29a sets the output signal S29a to the level “H”. The output side of the destination determination unit 29a is connected to the input terminal D of the FF 29c. FF2
9c is connected to the control line 32 and the signal B
S _A is given.

The data length judging section 29b has a data length LEN
Is longer than a certain length, the output signal S29b
Is set to “H”. The output side of the data length determination unit 29b is connected to the input terminal D of the FF 29d. F
The clock terminal C of F29d is connected to the control line 32, signal BS _A is given. Output terminals Q of the FFs 29c and 29d are connected to first and second input terminals of a three-input AND 29e, respectively. A third input terminal of AND29e control line 33 is connected, the signal BL _A is given. The output terminal Q of the FF 29c and the inverted output terminal Q / of the FF 29d are connected to the first and second input terminals of the three-input AND 29f, respectively. AND29f
Is connected to the control line 33 and the signal BL _A
Is given. 5 (1) and 5 (2) are diagrams showing the format of transfer data in the bus expansion device of FIG. 1, wherein FIG. 5 (1) shows 32-bit format transfer data and FIG. 5 (2) shows 64-bit format. Are respectively shown. Next, referring to FIGS. 3 to 5, the bus expansion device 20 of FIG.
The operation of (I) is as follows.
0, (II) System bus 30 to expansion bus 40
Transfer to the server will be described.

(I) Expansion bus 40 to system bus 3
Transfer to 0 When data is transmitted from a slave processor (not shown) connected to the extension bus 40 in FIG. 1 to a master processor (not shown) connected to the system bus 30, the slave processor The 64-bit data DB0 to DB63 shown in the word WB1 are output to the data signal line 41 and the signal B to the control lines 42 and 43 is output.
S _B and BL _B are set to “H” for output. Transfer control unit 25
Of the destination DES in the word WB1 determines that the data is data to the system bus 30, and sets the output signal S25a to "H". At this time, since the signal BS _B has become "H", the output signal S25b of FF25b becomes "H". Output signal S2 of FF 25b
5b, together with the signal BL _B serving as the data transfer "H", since given AND25c, this AND25c
Becomes "H" during the transfer of the words WB1 to WB3. Thereby, the three-state buffer 24 is turned on. Data DB0~DB63 is given to FF22 through the buffer 21, the clock signal CK _B
And is provided to the input side of the selector 23. In the selector 23, based on the clock signal CK _A system bus 30, the lower data DB0~DB31
And the upper data DB32 to DB63 are alternately selected and output. In this way, the 64-bit format data of FIG. 5B is converted into a 32-bit format as shown in FIG. 5A, and the data signal line 31 of the system bus 30 is passed through the 3-state buffer 24. Is forwarded to

(II) From the system bus 30 to the extension bus 4
Transferring to 0 When transferring data from the master processor to a slave processor connected to the extension bus 40, the master processor sets the data signal line 31 to the 32-bit data DA0 as indicated by the word WA1 in FIG. ~ DA31, and the signals BS _A ,
And in the BL _A "H" to output. The destination determination unit 29a of the transfer control unit 29 determines that the data is the data to the expansion bus 40 based on the content of the destination DES in the word WA1, and sets the output signal 29a to “H”. At this time, since the signal BS _A has become "H", FF29c output signal S29
c becomes “H”. Further, the data length determination unit 29b of the transfer control unit 29 determines whether or not the data length is larger than a certain value based on the content of the data length LEN in the word WA1. At this time, if the data length is equal to or more than a certain value, the output signal S29b becomes “H”. In addition, signal BS _A is "H"
Therefore, the output signal of the output terminal Q of the FF 29d becomes "H" and the output signal of the inverted output terminal Q / becomes "L". FF29c, the output signal of the 29d, along with the signal BL _A serving as the data transfer "H", since given AND29e, the output signal CON2 of the AND29e is
It becomes “H” during the transfer of the words WA1 to WA6, and the three-state buffers 28a and 28b are turned on.

The data DA0 to DA31 are stored in a buffer 26.
Through the FF27a, provided to 27b, 2 two FF27a based on the clock signal CK _A, held alternately in 27b. The data held in the FFs 27a and 27b is output to the data signal line 41 of the extension bus 40 via the three-state buffers 28a and 28b. As described above, the 32-bit data of FIG.
The data is converted into a 64-bit format as shown in (2) and transferred to the extension bus 40. On the other hand, when the data length determination unit 29b determines that the data length is equal to or smaller than the predetermined value, the output signal S29b becomes “L”, the output signal of the output terminal Q of the FF 29d is “L”, and the inverted output terminal Q / Is "H". As a result, the control signal CON2 becomes "L" and the control signal CON3 becomes "H", the three-state buffer 28a is turned on, and the three-state buffer 28b is turned on.
Is turned off. Therefore, the data DA0 to DA31 on the data signal line 31 are transferred to the data DB0 of the data signal line 41 via the FF 27a and the three-state buffer 28a.
ＤＢDB31 is transferred in the 32-bit format.

As described above, the bus expansion device of the present embodiment stores 64-bit data DB0 to DB63 in the lower 32 bits.
A selector 23 for dividing the data into bits and upper 32 bits and alternately outputting the divided data, and two FFs 27a for alternately holding two consecutive 32-bit data DA0 to DA31 and outputting the data as parallel 64-bit data; 27b, data transfer between two parallel buses having different bit numbers is possible. Further, since the data length determining unit 29b that determines the data length LEN and controls the data transfer unit 28 according to the data length LEN is provided, the data length LE is determined.
If the transfer data is smaller than a certain value, bidirectional data transfer with a smaller data width is also possible.
Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(A) The data width is not limited to 32 bits and 64 bits, and data can be transferred between an arbitrary N bit and a double 2N bit parallel bus. (B) Although the data width of the system bus has been described as N bits and the data width of the expansion bus has been described as 2N bits, the reverse is also applicable. (C) If there is no need to perform bidirectional data transfer due to the smaller data width, the data length determination unit 29b can be omitted. (D) The bus expansion device between parallel buses having a bit width of 1: 2 has been described, but the present invention is also applicable to parallel buses having an integer multiple of 1: 3, 1: 4, and the like. . In that case, the number of selections by the selector and the number of data held by the FF may be increased. (E) Although the FFs 22, 27a, and 27b are used to hold the data DA0 to 31 to be transferred, data holding means such as a memory may be used.

[0021]

As described above in detail, according to the first aspect, the first data converter for converting 2N-bit parallel data into N-bit parallel data, and converts the N-bit parallel data into 2N-bit parallel data. A second data conversion unit for converting data into parallel data, first and second transfer control units for controlling transfer with destination information of a header portion of the parallel data, and a transfer control signal from these transfer control units. Since the first and second data transfer units for transferring data between the first and second parallel buses are provided, data can be transferred between parallel buses having different bit widths. According to the second aspect, since the transfer control unit that changes the width of the data to be transferred according to the data length is provided,
In addition to the data transfer similar to that of the invention, it is also possible to transfer the transfer data having a short data length as it is without converting the bit width.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a bus expansion device according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a multiprocessor system using a conventional bus expansion device.

FIG. 3 is a configuration diagram of a transfer control unit 25 in FIG. 1;

FIG. 4 is a configuration diagram of a transfer control unit 29 in FIG. 1;

FIG. 5 is a diagram showing a format of transfer data in FIG. 1;

[Explanation of symbols]

 Reference Signs List 20 bus expansion device 23 selector 24, 28a, 28b 3-state buffer 25, 29 transfer control unit 27 data conversion unit 28 data transfer unit 30 system bus 40 expansion bus

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideyuki Murakami 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Katsuyuki Okada 3-192-2 Nishishinjuku, Shinjuku-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation (72) Michihiro Aoki Inventor 3-192-2 Nishishinjuku, Shinjuku-ku, Tokyo Japan Inside Telegraph and Telephone Corporation (72) Tokuo Hosaka 3-192-1, Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation

Claims (2)

[Claims] 1. An N-bit header portion including information indicating a data destination and a data length, and one or a plurality of N-bit units following the N-bit header portion are sequentially transferred by N bits as parallel data of a first format. A first parallel bus, a header section similar to the header section described above, and one or more N-bit units of data successively transfer 2N-bit parallel data of a second format sequentially. Second
A bus expansion device that expands the driving capacity of the bus by connecting with the parallel bus of the second type, receiving the parallel data of the second format transferred on the second parallel bus, and A first data conversion unit that converts the data into parallel data of a first format; and a header unit that monitors the header portion transferred on the second parallel bus, wherein the destination information in the header portion is the first parallel bus. A first transfer control unit that activates and outputs a first transfer control signal for a time corresponding to the data length in the header portion, and the first transfer control signal; When the first transfer control signal is activated, it is connected to the first parallel bus to output an output signal of the first data converter to the first parallel bus, and the first transfer control signal Disconnects from the first parallel bus when is deactivated A first data transfer unit, and a second data conversion unit that receives the parallel data of the first format transferred on the first parallel bus and converts the parallel data into the parallel data of the second format Monitoring the header section transferred on the first parallel bus, and when the destination information in the header section is addressed to the second parallel bus, a time corresponding to the data length in the header section. A second transfer control unit that activates and outputs a second transfer control signal, and the second transfer control signal is provided, and the second transfer control signal is activated when the second transfer control signal is activated. An output signal of the second data converter is connected to a parallel bus and output to the second parallel bus, and is disconnected from the second parallel bus when the second transfer control signal is inactivated. And a second data transfer unit. Tensioning device. 2. An N-bit header section including information indicating a data destination and a data length, and a subsequent one or a plurality of N-bit data are sequentially transferred by N bits as parallel data of a first format. A first parallel bus, a header section similar to the header section described above, and one or more N-bit units of data successively transfer 2N-bit parallel data of a second format sequentially. Second
A bus expansion device that expands the driving capacity of the bus by connecting with the parallel bus of the second type, receiving the parallel data of the second format transferred on the second parallel bus, and A first data conversion unit that converts the data into parallel data of a first format; and a header unit that monitors the header portion transferred on the second parallel bus, wherein the destination information in the header portion is the first parallel bus. A first transfer control unit that activates and outputs a first transfer control signal for a time corresponding to the data length in the header portion, and the first transfer control signal; When the first transfer control signal is activated, it is connected to the first parallel bus to output an output signal of the first data converter to the first parallel bus, and the first transfer control signal Disconnects from the first parallel bus when is deactivated A first data transfer unit, and a second data conversion unit that receives the parallel data of the first format transferred on the first parallel bus and converts the parallel data into the parallel data of the second format And monitoring the header section transferred on the first parallel bus, wherein the destination information in the header section is addressed to the second parallel bus, and the data length in the header section is a fixed length. The second transfer control signal is activated and output for a time corresponding to the data length when the data length is longer than the data length, the destination information is addressed to the second parallel bus, and the data length is equal to or less than the predetermined length. A second transfer control unit for activating and outputting a third transfer control signal for a time corresponding to the data length at the time of the second transfer control signal; and providing the second and third transfer control signals. Connect to the second parallel bus when the control signal is activated The output signal of the second data converter is output to the second parallel bus, and when the third transfer control signal is activated, the output signal is connected to the second parallel bus so as to be connected to the first parallel bus. Outputting parallel data to the second parallel bus;
A second data transfer unit that is disconnected from the second parallel bus when the transfer control signal is inactivated.