JPH10308511A - Silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a structure of high withstand voltage, low ON-resistance and low gate threshold voltage, by forming a silicon carbide thin film in a groove side surface in a groove gate type power MOSFET. SOLUTION: An MOSFET is formed by forming an n-type thin film semiconductor layer 8 in a side surface of a groove 7. It is constituted so that a p-n junction between an n<-> -type epitaxial layer 2 and a p-type epitaxial layer 3 causes avalanche breakdown before punch-through of an n-type thin film semiconductor layer 8 when a reverse bias voltage is applied. Concretely, when p-type polysilicon is used for a gate electrode layer 10, a film thickness X (μm) and an impurity concentration N (cm<-3> ) of the n-type thin film semiconductor layer 8 are set to satisfy relationship of Y<-10000 X-0.6)+0.3(logN-15)} to an aimed withstand voltage Y(V), and when n-type polysilicon is used for the gate electrode layer 10, they are set to satisfy relationship of Y<-10000 (X-0.6)+0.3 logN-15)}.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device, which can be used as a silicon carbide semiconductor device, for example, as an insulated gate field effect transistor, especially a vertical MOSFET for high power.

[0002]

2. Description of the Related Art Conventionally, a trench gate type power MOSFET excellent in low on-resistance and high withstand voltage has been used as a silicon carbide semiconductor device.
(JP-A-7-326755 or JP-A-8-70124) has been proposed. As shown in FIG. 17, the trench gate type power MOSFET has a hexagonal single crystal carbonized structure formed by an n ⁺ -type single crystal silicon carbide (SiC) semiconductor substrate 1, an n ⁻ -type epitaxial layer 2 and a p-type epitaxial layer 3. A semiconductor substrate 4 made of silicon is formed, and its upper surface (main surface) is substantially a (0001-) carbon surface.

[0003] A predetermined area of the surface layer of the p-type epitaxial layer 3
In the area, n⁺Type source region 5 is formed, and n⁺Type
A trench (trench) 7 is formed at a predetermined position in the source region 5.
Have been. This groove 7 has n⁺Source region 5 and p-type epi
N penetrating through the axial layer 3 ^-Type epitaxial layer 2
And a side surface 7a perpendicular to the surface of the p-type epitaxial layer 3.
And bottom surface 7b parallel to the surface of p-type epitaxial layer 3
Having.

[0004] A gate insulating film (gate oxide film) 9 is formed inside the trench 7, and the gate oxide film 9 is filled with a gate electrode layer 10. On the gate electrode layer 10, an interlayer insulating film 11 is arranged. Further, the surface of n ⁺ type source region 5 including on interlayer insulating film 11 and p ⁺
On the surface of the type epitaxial layer 3, are formed a source electrode layer 12, the source electrode layer 12 is n ⁺ -type source region 5
And the p-type epitaxial layer 3. Also, n
On the surface of ⁺ type silicon carbide semiconductor substrate 1 (the back surface of semiconductor substrate 4), drain electrode layer 13 is formed.

By applying a positive voltage to the gate electrode layer 10, the p-type epitaxial layer 3
The surface of the substrate serves as a channel, and a current flows between the source electrode layer 12 and the drain electrode layer 13.

[0006]

The breakdown voltage between the source and the drain in the above-mentioned trench gate type power MOSFET is as follows.
It is determined by the conditions under which avalanche breakdown occurs at the pn junction of the p-type epitaxial layer 3 and the n ⁻ -type epitaxial layer 2 and the conditions under which the entire region of the p-type epitaxial layer 3 is depleted to cause punch-through. In punch through, p
Since the breakdown voltage changes due to the variation in the thickness of the epitaxial layer, and it is difficult to obtain a predetermined breakdown voltage, it is necessary to cause avalanche breakdown. In order to prevent punch-through and cause avalanche breakdown, the impurity concentration of the p-type epitaxial layer 3 is made sufficiently high, and the thickness of the region between the n ⁺ -type source region 5 and the n ^-- type epitaxial layer 2 is increased. It is necessary to make the thickness a sufficiently large.

However, when the impurity concentration of the p-type epitaxial layer 3 is increased, the gate threshold voltage increases,
In addition, channel mobility decreases due to an increase in impurity scattering,
ON resistance increases. When the thickness a is increased,
There is a problem that the channel length is increased and the on-resistance is increased. Therefore, the present applicant, as shown in FIG.
A semiconductor device in which an n-type silicon carbide thin film semiconductor layer 8 is formed by epitaxial growth on the surfaces of n ⁺ -type source region 5, p-type epitaxial layer 3 and n ⁻ -type epitaxial layer 2 on side surface 7 a of trench 7. It was proposed (Japanese Patent Application No. Hei 7-229487).

In the semiconductor device shown in FIG.
The n-type thin film semiconductor layer 8 is used as a channel forming region, and a voltage is applied to the gate electrode layer 10 to apply an electric field to the gate oxide film 9 to induce a storage channel in the n-type thin film semiconductor layer 8 so that the source electrode is formed. A current is caused to flow between the layer 12 and the drain electrode layer 13. Thus, MOSF
By setting the operation mode of the ET to the accumulation mode in which the channel is induced without inverting the conductivity type of the channel formation layer, the MOSFET can be operated at a lower gate voltage than the inversion mode MOSFET in which the conductivity type is inverted and the channel is induced. Can work.

Further, since the impurity concentration of the p-type epitaxial layer 3 and the impurity concentration of the n-type thin film semiconductor layer 8 in which the channel is formed can be controlled independently, the impurity concentration of the p-type epitaxial layer 3 can be increased. n ⁺ type source region 5
And the thickness a sandwiched between the n ⁻ -type epitaxial layers 2 can be reduced, so that the channel length can be shortened, the breakdown voltage can be increased, and the on-resistance can be reduced.

Further, by lowering the impurity concentration of the n-type thin-film semiconductor layer 8 in which the channel is formed, the gate threshold voltage can be lowered and the influence of impurity scattering when carriers flow can be reduced. The mobility can be increased, the ON resistance can be reduced, and the power loss can be reduced. Therefore, according to the trench gate type power MOSFET shown in FIG. 18, a silicon carbide semiconductor device having a high withstand voltage, a low power loss, and a low gate threshold voltage can be obtained.

However, in the trench gate type power MOSFET shown in FIG. 18 proposed earlier, the film thickness and the impurity concentration which are the structural parameters of the n-type thin film semiconductor layer 8 are as follows.
The relationship between the constituent materials of the gate electrode 12 and the conductivity type has not been studied, and a desired source-drain breakdown voltage may not be obtained depending on the relationship. Therefore, an object of the present invention is to provide a desired high withstand voltage when a silicon carbide thin film is formed on the side surface of a groove.

[0012]

The breakdown voltage of the n-type thin film semiconductor layer 8 depends on the expansion of the depletion layer caused by the electrostatic potential difference of the pn junction between the p-type epitaxial layer 3 and the n-type thin film semiconductor layer 8 and the gate electrode layer. The control can be performed by using both the expansion of the depletion layer caused by the work function difference between the constituent material of No. 10 and SiC. That is, due to the expansion of the depletion layers, the entire area of the n-type thin film semiconductor layer 8 is depleted, a potential barrier is formed in the n-type thin film semiconductor layer 8 between the source and the drain, and the n-type thin film semiconductor layer 8 has a withstand voltage. Let

The magnitude of the potential barrier of the thin film portion between the source and the drain fluctuates in principle depending on the thickness of the n-type thin film semiconductor layer 8, the impurity concentration, the breakdown voltage, and the conductivity type of the constituent material of the gate electrode layer 10. . Therefore, it is necessary to set the withstand voltage of the n-type thin-film semiconductor layer 8 higher than the withstand voltage determined by the p-type epitaxial layer 3 and the n ⁻ -type epitaxial layer 2 in order to suppress the withstand voltage fluctuation.

In order to find the condition, FIG.
Was set, and the calculation was performed using MEDICI (manufactured by TMA) as a device simulator. In this simulation model, the thickness of the side surface of the groove of the gate oxide film 9 is set to 60 nm,
The impurity concentration of the p-type epitaxial layer 3, the junction depth and impurity concentration of n ^- -type epitaxial layer 2, the junction depth, p-type epitaxial layer 3 and the n ^- breakdown voltage of the formed body diode by -type epitaxial layer 2 is 1000
V was set. Further, the dielectric constant of SiC is set to 1
0.0, electron affinity 4.3 eV, band gap 2.9 V, drain current 5 × 10 ⁻¹⁰ A, temperature T
Was set to 623K.

FIGS. 20 and 21 show calculation results of the breakdown voltage when the thickness of the n-type thin film semiconductor layer 8 is changed using the impurity concentration as a parameter. FIG. 20 shows that p
FIG. 21 shows a case in which n-type polysilicon is used for the gate electrode layer 10 in the case where the polysilicon is used, and 図, Δ, and □ in the figure show impurity concentrations. The portion where the breakdown voltage is constant with respect to the change in the film thickness of the n-type thin film semiconductor layer 8 is the case where the breakdown voltage of the body diode is fixed at 1000V. In a portion where the breakdown voltage sharply decreases as the thickness of the n-type thin film semiconductor layer 8 increases, the breakdown voltage is determined by punch-through of the n-type thin film semiconductor layer 8. In the portion where the breakdown voltage is fixed to 1000 V, the pn junction between the n ⁻ -type epitaxial layer 2 and the p-type epitaxial layer 3 is avalanche-break before the n-type thin film semiconductor layer 8 causes punch-through. It is supposed to go down.

When p-type polysilicon is used for the gate electrode layer 10, as shown in FIG. 20, the film thickness X (μm), the impurity concentration N (cm ⁻³ ), and the withstand voltage Y ( V)
Is Y = -10000 ｛(X-0.8) +0.3 (lo
gN-15) When the relationship of｝ is satisfied, the withstand voltage starts to rapidly decrease. When n-type polysilicon is used for the gate electrode layer 10, the film thickness X (μm), the impurity concentration N (cm ⁻³ ), and the withstand voltage Y (V−V) of the n-type thin film semiconductor layer 8 are shown in FIG. ) Is Y = -10000 {(X-0.6) +0.
When the relationship of 3 (logN-15)｝ is satisfied, the withstand voltage starts to rapidly decrease.

Therefore, by setting the film thickness and the impurity concentration of the n-type thin film semiconductor layer 8 based on the above relationship, a desired breakdown voltage can be obtained. The present invention has been made based on the above study. In the invention according to claim 1, when the reverse bias voltage is applied, the second semiconductor layer and the high-resistance semiconductor layer are preceded by punch-through. The semiconductor device is characterized in that an avalanche breakdown occurs at a pn junction with one semiconductor layer. With such a relationship, a desired high withstand voltage can be obtained.

According to the second aspect of the present invention, the gate electrode layer is of the second conductivity type and the thickness X of the second semiconductor layer is
(Μm) and impurity concentration N (cm ⁻³ ), Y <−10000 ｛(X−0.8) +0.3 (l)
ogN-15)}. According to the third aspect of the present invention, when the gate electrode layer is of the first conductivity type, the thickness X (μm) and the impurity concentration N (cm ⁻³ ) of the second semiconductor layer are:
With respect to the withstand voltage Y (V), Y <-10000 ° (X-0.
6) +0.3 (logN-15)}. By setting the thickness of the second semiconductor layer and the impurity concentration N (cm ⁻³ ) so as to satisfy such a relationship, a target high withstand voltage can be obtained.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. FIG. 1 shows an n-channel type trench gate type power MOSFET (vertical power MOSFET) according to the present embodiment. N ⁺ as a low resistance semiconductor layer
Type silicon carbide semiconductor substrate 1 uses hexagonal silicon carbide. On this n ⁺ -type silicon carbide semiconductor substrate 1, an n ⁻ -type silicon carbide semiconductor layer (n ⁻ -type epitaxial layer) 2 as a high resistance semiconductor layer and a p-type silicon carbide semiconductor layer (p-type) as a first semiconductor layer Epitaxial layers) 3 are sequentially stacked. Thus, n ⁺ type silicon carbide semiconductor substrate 1 and n ^+
A semiconductor substrate 4 made of single-crystal silicon carbide is constituted by the-type epitaxial layer 2 and the p-type epitaxial layer 3, and the upper surface thereof is substantially a (0001-) carbon surface.

An n ⁺ -type source region 5 as a semiconductor region is formed in a predetermined region in the surface portion of the p-type epitaxial layer 3. Further, the p-type epitaxial layer 3
A low-resistance p-type silicon carbide region 6 is formed in a predetermined region on the outer peripheral side of n ⁺ -type source region 5 in the inner surface layer portion. Further, a groove 7 is formed in a predetermined region of the n ⁺ type source region 5, and the groove 7 penetrates the n ⁺ type source region 5 and the p type epitaxial layer 3 and reaches the n ⁻ type epitaxial layer 2. The groove 7 has a side surface 7 a perpendicular to the surface of the semiconductor substrate 4 and a bottom surface 7 b parallel to the surface of the semiconductor substrate 4.

The side surface 7a of the groove 7 is substantially [11-00].
It extends in the direction. In this case, the [11-00] direction is <11-00>, <101-0>, <011-0>
>, <1-100>, <101-0>, <0110->
Are collectively referred to as the six directions.
Is composed of a plurality of surfaces that are substantially parallel to the [11-00] direction.

The planar shape of the side surface 7a of the groove 7 is a hexagon whose interior angles are substantially equal. That is, as shown in the plan view of the semiconductor substrate 4 in FIG.
1, S2, S3, S4, S5, and S6, the angle between the sides S1 and S2 (inner angle), the angle between the sides S2 and S3 (inner angle), the angle between the sides S3 and S4 (inner angle), and the sides S4 and S5
(Inner angle), an angle (inner angle) between sides S5 and S6, and an angle (inner angle) between sides S6 and S1 are approximately 120 °.

On the surface of n ⁺ type source region 5, p type epitaxial layer 3 and n ⁻ type epitaxial layer 2 on side surface 7 a of trench 7 in FIG. 1, a thin film semiconductor layer of n type silicon carbide (second semiconductor) Layer 8 is extended. The n-type thin film semiconductor layer 8 is formed of a thin film having a thickness of about 1000 to 5000 °, and the crystal type of the n-type thin film semiconductor layer 8 is the same as the crystal type of the p-type epitaxial layer 3, for example, 6H−
It is SiC. In addition, 4H-SiC or 3C-SiC may be used. Further, the impurity concentration of n-type thin film semiconductor layer 8 is lower than that of n ⁺ -type silicon carbide semiconductor substrate 1 and n ⁺ -type source region 5.

Further, a gate oxide film 9 is formed on the surface of the n-type thin film semiconductor layer 8 in the groove 7 and on the bottom surface 7b of the groove 7. The inside of the gate oxide film 9 in the trench 7 is filled with a gate electrode layer 10. Gate electrode layer 10 is covered with interlayer insulating film 11. A source electrode layer 12 as a first electrode layer is formed on the surface of n ⁺ type source region 5 and the surface of low-resistance p-type silicon carbide region 6. n
On the surface of ⁺ type silicon carbide semiconductor substrate 1 (the back surface of semiconductor substrate 4), a drain electrode layer 13 as a second electrode layer is formed.

The operation of the trench gate type power MOSFET is as follows. By applying a positive electrode to the gate electrode 10, an accumulation channel is induced in the thin film semiconductor layer 8, and the source electrode layer 12 and the drain electrode layer 13 A carrier flows between them. That is, the thin film semiconductor layer 8 becomes a channel formation region. As described above, by setting the accumulation mode in which the channel is induced as the MOSFET operation mode, the MOSFE in the inversion mode in which the conductivity type is inverted to induce the channel.
As compared with T, the MOSFET can be operated with a lower gate voltage, the channel mobility can be increased, and the gate threshold voltage can be reduced with low power loss. The source / drain current control when no gate voltage is applied is performed by expanding a depletion layer of a pn junction formed by the p-type epitaxial layer 3 (body layer) and the thin film semiconductor layer 8 (channel formation layer). Normally-off characteristics can be achieved by completely depleting the thin film semiconductor layer 8.

Further, the p-type epitaxial layer 3 (body layer) and the n ⁻ -type epitaxial layer 2 (drift layer)
Since an n-junction is formed, the breakdown voltage of the device can be designed so as to be determined by the avalanche breakdown of the pn junction between the p-type epitaxial layer 3 fixed to the source electrode and the n ⁻ -type epitaxial layer 2. Can be larger. That is, when a large positive voltage (for example, a counter electromotive voltage generated when switching noise or inductive load) is applied to the drain side with respect to the source, that is, a reverse bias voltage is applied to the pn junction between the source and the drain. When the thin-film semiconductor layer 8 between the n ⁻ -type epitaxial layer 2 and the p-type epitaxial layer 3 is punched through by the high voltage on the drain side, the n ⁻ -type epitaxial layer 2 and the p-type epitaxial layer 3 It is sufficient that the pn junction between the avalanche breakdown occurs at a voltage lower than the voltage at which the punch-through occurs.

In the graphs shown in FIGS. 20 and 21, the region where the breakdown voltage changes abruptly indicates the breakdown voltage determined by punch-through of the thin-film semiconductor layer 8, and the region where the breakdown voltage is 1000 V indicates that the thin-film semiconductor layer 8 has the punch-through. This means that the voltage causing the avalanche breakdown is lower than the voltage causing the slew. From the two figures, p between the n ⁻ -type epitaxial layer 2 and the p-type epitaxial layer 3
In order to determine the withstand voltage of the SiC power MOSFET by n-junction avalanche breakdown, the thin film semiconductor layer 8
It is necessary to reduce the film thickness as the impurity concentration becomes higher.

In order to determine the breakdown voltage of the SiC power MOSFET based on the avalanche breakdown of the pn junction between the n ⁻ -type epitaxial layer 2 and the p-type epitaxial layer 3, as shown in FIGS. In addition to setting the thin film semiconductor layer 8, it can be achieved by, for example, changing the impurity concentration of the n ⁻ -type epitaxial layer 2 and the p-type epitaxial layer 3.

In addition, by independently controlling the impurity concentration of the p-type epitaxial layer 3 and the impurity concentration of the thin film semiconductor layer 8, a high breakdown voltage, low power loss, and a low gate threshold voltage can be obtained.
It becomes an SFET. In particular, by lowering the impurity concentration of the thin film semiconductor layer 8 forming the channel, the influence of impurity scattering when carriers flow is reduced, and the channel mobility can be increased. The source-drain breakdown voltage is
Since it is mainly governed by the impurity concentration and the film thickness of the n ⁻ -type epitaxial layer 2 and the p-type epitaxial layer 3, the impurity concentration of the p-type epitaxial layer 3 is increased to sandwich the high-resistance semiconductor layer and the semiconductor region. The distance can be shortened, and the channel length can be shortened while maintaining high withstand voltage. Therefore, the channel resistance can be drastically reduced, and the on-resistance between the source and the drain can be reduced.

Next, a manufacturing process of the trench gate type power MOSFET will be described with reference to FIGS. First, FIG.
As shown in FIG. 1, an n ⁺ -type silicon carbide semiconductor substrate 1 having a (0001-) carbon surface as a main surface is prepared, and n
^{The −} type epitaxial layer 2 is epitaxially grown, and the p type epitaxial layer 3 is epitaxially grown on the n ⁻ type epitaxial layer 2. Thus, n
⁺ Type silicon carbide semiconductor substrate 1 and n ⁻ type epitaxial layer 2
And a p-type epitaxial layer 3 are formed. Incidentally, the crystal axis of the n ⁺ -type silicon carbide semiconductor substrate 1 to about 3.5 ° to 8 ° inclined n ^- -type epitaxial layer 2,
Since the p-type epitaxial layer 3 is formed, the plane orientation of the main surface of the semiconductor substrate 4 is substantially a (0001-) carbon plane.

Next, as shown in FIG.
In a predetermined region of the surface layer portion of the ⁺Mold source region 5
For example, it is formed by ion implantation of nitrogen. Furthermore, p-type
A low resistance p is applied to another predetermined region of the surface portion of the epitaxial layer 3.
Type silicon carbide region 6 for ion implantation of aluminum, for example.
Formed. Then, as shown in FIG.
RIE (Reactive Ion E)
tching) method and n⁺Type source region 5 and p-type
N through the epitaxial layer 3 together^-Type epitaxy
A groove 7 reaching the signal layer 2 is formed. At this time, the side of the groove 7
Groove 7 so that 7a is substantially parallel to the [11-00] direction.
Form. Therefore, as shown in FIG.
The planar shape of the side surface 7a of the groove 7 is a hexagon whose inner angles are substantially equal.
Becomes

Further, as shown in FIG. 6, the inner wall (side surface 7a and bottom surface 7b) of the groove 7 is formed by an epitaxial growth method.
The n-type thin-film semiconductor layer 8 is formed on the upper surface of the semiconductor substrate 4 including. Specifically, a 6H-SiC thin film layer is homoepitaxially grown on 6H-SiC by CVD, and the n ⁺ -type source region 5, the p-type epitaxial layer 3, and the n ^-- type epitaxial layer 2 on the inner wall of the groove 7 are formed. An n-type thin-film semiconductor layer 8 extending to the surface of the substrate is formed.

At this time, the epi growth rate is (0001-)
Since it is 8 to 10 times or more in the direction perpendicular to the carbon surface, the n-type thin film semiconductor layer 8 can be formed thick on the groove side surface 7a and thin on the groove bottom surface 7b. Here, the film thickness X (μm) of the n-type thin film semiconductor layer 8 on the groove side surface 7a
And the impurity concentration N (cm ⁻³ ), when the gate electrode layer 10 is p-type polysilicon, the target source-drain withstand voltage Y (V) is Y <−10000 ° (X−0.
8) +0.3 (logN-15)}, and when the gate electrode layer 10 is n-type polysilicon, Y <-10000 {(X-0.6) +0.3
(Log N−15)}.

In the step of forming the n-type thin film semiconductor layer 8, the n-type thin film semiconductor layer 8 is grown while reducing surface irregularities caused by the groove forming step. Therefore, the channel forming surface becomes a flat surface,
Channel mobility is improved. Further, the n-type thin film semiconductor layer 8
Since there is no crystal defect caused by ion bombardment by the RIE method, a decrease in mobility can be prevented, and the on-resistance between the source and the drain can be reduced.

Subsequently, as shown in FIG. 7, the surface of the semiconductor substrate 4 and the n-type thin film semiconductor layer 8 and the groove 7 are thermally oxidized.
A gate oxide film (thermal oxide film) 9 is formed on the bottom surface 7b of the substrate. At this time, the thermal oxide film is thinner on the side surface 7a and thicker on the substrate surface and the groove bottom surface 7b, and the thin film semiconductor layer 8 formed on the surface of the semiconductor substrate 4 and the groove bottom surface 7b by epitaxial growth becomes an oxide film. This is because the oxidation rate of hexagonal silicon carbide is (0
This is because it is about five times faster than the (001-) carbon plane and the plane perpendicular to the (0001-) carbon plane. In this manner, the thin film semiconductor layer 8 on the surface of the semiconductor substrate 4 and the groove bottom surface 7b of the n-type thin film semiconductor layer 8 formed by epitaxial growth is thermally oxidized and the thin film semiconductor layer 8 is formed only on the groove side surface 7a.
Will remain.

In the step of forming the gate oxide film 9,
As described above, the channel forming surface is a flat surface,
The thickness of the gate oxide film 9 formed on the channel formation surface can also be made uniform. As a result, the completed MOSFE
At T, there is no local electric field concentration point when a gate voltage is applied. Therefore, the gate oxide film breakdown voltage can be improved. For the same reason, the life of the gate oxide film can be extended.

Then, as shown in FIG. 8, the inside of the gate oxide film 9 in the trench 7 is filled with a gate electrode layer 10. As a constituent material of the gate electrode layer 10, p-type polysilicon or n-type polysilicon is used. further,
As shown in FIG. 9, the insulating film 1 is formed on the upper surface of the gate electrode layer 10.
Form one. Thereafter, as shown in FIG. 1, source electrode layer 12 is formed on n ⁺ -type source region 5 including on interlayer insulating film 11 and low-resistance p-type silicon carbide region 6. Also, n
^A drain electrode layer 1 is formed on the surface of
3 to complete a trench gate type power MOSFET.

In the above embodiment, the source electrode layer 12 formed in the n ⁺ type source region 5 and the low resistance p type silicon carbide region 6 may be made of different materials. Further, the low-resistance p-type silicon carbide region 6 can be omitted, and in this case,
Source electrode layer 12 is formed so as to be in contact with n ⁺ -type source region 5 and first p-type epitaxial layer 3. Further, the source electrode layer 12 only needs to be formed at least on the surface of the n ⁺ type source region 5.

Further, the silicon carbide semiconductor device according to the present invention is not limited to the above-described n-channel vertical MOSFET,
The same can be applied to a p-channel vertical MOSFET in which the p-type and the n-type are interchanged in FIG.
Further, in the configuration shown in FIG. 1, the side surface 7a of the groove 7 is approximately 90 ° with respect to the surface of the semiconductor substrate 4, but the groove 7 is not shown in FIG.
As shown in the figure, the angle between the side surface 7a of the groove 7 and the surface of the semiconductor substrate 4 does not necessarily have to be close to 90 °. Also,
The groove 7 may be V-shaped without a bottom surface. Further, as shown in FIG. 11, the side surface 7a of the groove 7 need not be a flat surface, but may be a smooth curved surface.

A better effect can be obtained by designing the angle between the side surface 7a of the groove 7 and the surface of the semiconductor substrate 4 so as to increase the channel mobility. As shown in FIG. 12, the upper portion of gate electrode layer 10 may have a shape extending above n ⁺ type source region 5. With this configuration, the connection resistance between the n ⁺ -type source region 5 and the channel induced in the n-type thin film semiconductor layer 8 can be reduced.

Further, as shown in FIG. 13, the thickness of the gate oxide film 9 is substantially equal at the center and the lower end of the n-type thin film semiconductor layer 8 where the channel is formed, and at the lower end of the n-type thin film semiconductor layer 8. The structure may be such that the gate electrode layer 10 reaches below. With this structure, the connection resistance between the channel and the drain region induced in the n-type thin film semiconductor layer 8 can be reduced. Further, the present invention may be implemented as shown in FIG. That is, the upper part of the gate electrode layer 10 has a shape extending above the n ⁺ -type source region 5 as shown in FIG. 12, and the lower end of the n-type thin film semiconductor layer 8 as shown in FIG. A structure in which the gate electrode layer 10 extends to the bottom may be used.

The n-type thin film semiconductor layer 8 and the p-type epitaxial layer 3 may be of different crystal types. For example, the p-type epitaxial layer 3 may be made of 6H SiC,
Is 4H SiC to increase the mobility in the direction in which carriers flow, thereby obtaining a MOSFET with low power loss. Further, as shown in FIG. 15, the planar shape of the side surface of the groove 7 (specifically, the shape on the side of the gate electrode layer 10) may be a hexagon whose inner angles are substantially equal. That is, as shown in the plan view of the substrate 4 in FIG.
In S12, S13, S14, S15, and S16, the angle (inner angle) formed between the sides S11 and S12, and the sides S12 and S13
(Inner angle), the angle between sides S13 and S14 (inner angle), the angle between sides S14 and S15 (inner angle), side S15
And the angle between the sides S16 and S11 (the interior angle) is approximately 120 degrees.

The side surface 7a of the groove 7 is substantially [11-0].
The plane is not limited to a plurality of planes parallel to the [0] direction, but may be a plurality of planes substantially parallel to the [112-0] direction. In this specification, when the plane and the direction axis of the hexagonal single-crystal silicon carbide are expressed, a bar should be added to a required number as originally described in the drawings. However, since there is a restriction on the expression means, instead of the expression in which a bar is put on the required number, the expression is made by adding "-" after the required number.

[Brief description of the drawings]

FIG. 1 shows a trench gate type power M according to an embodiment of the present invention.
It is a perspective view of OSFET.

FIG. 2 is a plan view of the semiconductor substrate 4 shown in FIG.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the trench gate type power MOSFET shown in FIG.

FIG. 4 is a cross-sectional view for explaining a manufacturing step following FIG. 3;

FIG. 5 is a cross-sectional view for explaining a manufacturing step following FIG. 4;

FIG. 6 is a cross-sectional view for explaining a manufacturing step following FIG. 5;

FIG. 7 is a cross-sectional view for explaining a manufacturing step following FIG. 6;

FIG. 8 is a cross-sectional view for explaining a manufacturing step following FIG. 7;

FIG. 9 is a cross-sectional view for explaining a manufacturing step following FIG. 8;

FIG. 10 is a schematic sectional view showing a modified example of the trench gate type power MOSFET shown in FIG. 1;

FIG. 11 is a schematic sectional view showing a modification of the trench gate type power MOSFET shown in FIG. 1;

FIG. 12 is a schematic sectional view showing a modification of the trench gate type power MOSFET shown in FIG. 1;

FIG. 13 is a schematic sectional view showing a modification of the trench gate type power MOSFET shown in FIG.

FIG. 14 is a schematic sectional view showing a modification of the trench gate type power MOSFET shown in FIG. 1;

FIG. 15 is a perspective view showing a modification of the trench gate type power MOSFET shown in FIG.

16 is a plan view of the semiconductor substrate 4 shown in FIG.

FIG. 17 is a schematic sectional view of a conventional trench gate type power MOSFET.

FIG. 18 shows a trench gate type power M previously proposed by the present applicant.
FIG. 3 is a schematic sectional view of an OSFET.

FIG. 19 is a diagram showing a simulation model for determining the film thickness and impurity concentration of the n-type thin film semiconductor layer 8.

FIG. 20 shows an example in which p-type polysilicon is used for a gate electrode layer 10 and an n-type thin-film semiconductor layer 8 is formed using impurity concentration as a parameter
FIG. 9 is a diagram showing calculation results of a withstand voltage when the film thickness is changed.

FIG. 21 shows an example in which n-type polysilicon is used for a gate electrode layer 10 and n-type thin-film semiconductor layers 8 are formed using impurity concentration as a parameter.
FIG. 9 is a diagram showing calculation results of a withstand voltage when the film thickness is changed.

[Explanation of symbols]

1 ... n ⁺ -type silicon carbide semiconductor substrate as the low-resistance semiconductor layer, 2 ... n as the high-resistance semiconductor layer ^- -type epitaxial layer, 3 ... p-type epitaxial layer as a first semiconductor layer, 4 ... semiconductor substrate, 5 ... n ⁺ -type source region as semiconductor region, 7 ... groove, 7a ... side surface, 7b ... bottom surface, 8 ... second
An n-type thin film semiconductor layer as a semiconductor layer, 9 a gate oxide film, 10 a gate electrode layer, 11 an interlayer insulating film, 12 a source electrode layer as a first electrode layer, and 13 a second electrode layer Drain electrode layer.

Claims (3)

[Claims] A first conductive type low-resistance semiconductor layer; a first conductive type high-resistance semiconductor layer; and a second conductive type first semiconductor layer. A semiconductor substrate (4) formed of a first conductivity type; a semiconductor region (5) of a first conductivity type formed in a predetermined region of a surface layer portion of the first semiconductor layer; A groove penetrating the semiconductor layer, and a second semiconductor layer of a first conductivity type formed of a silicon carbide thin film formed on at least a surface of the first semiconductor layer on a side surface of the groove. A gate insulating film (9) formed on at least a surface of the second semiconductor layer; a gate electrode layer (10) formed on the gate insulating film in the trench; And at least a portion formed on a part of the surface of the semiconductor region. One electrode layer (12); and a second electrode layer (1) formed on the back surface of the semiconductor substrate.
3) wherein when a reverse bias voltage is applied to a pn junction between the second electrode layer and the first electrode layer, the voltage between the high-resistance semiconductor layer and the semiconductor region is reduced. 2. A silicon carbide semiconductor device, wherein the pn junction between the high-resistance semiconductor layer and the first semiconductor layer undergoes avalanche breakdown before the second semiconductor layer causes punch-through. 2. A silicon carbide layer comprising: a first conductive type low resistance semiconductor layer (1); a first conductive type high resistance semiconductor layer (2); and a second conductive type first semiconductor layer (3). A semiconductor substrate (4) formed of a first conductivity type; a semiconductor region (5) of a first conductivity type formed in a predetermined region of a surface layer portion of the first semiconductor layer; A groove penetrating the semiconductor layer, and a second semiconductor layer of a first conductivity type formed of a silicon carbide thin film formed on at least a surface of the first semiconductor layer on a side surface of the groove. A gate insulating film (9) formed on at least a surface of the second semiconductor layer; a second conductivity type gate electrode layer (10) formed on the gate insulating film in the trench; On at least a part of the surface of the semiconductor region of the surface of the semiconductor substrate A second electrode layer (1) formed on the back surface of the semiconductor substrate;
3) wherein the thickness X (μm) of the second semiconductor layer and the impurity concentration N
(Cm ⁻³ ) is Y <−10000 with respect to the withstand voltage Y (V).
A silicon carbide semiconductor device characterized by satisfying a relationship of {(X−0.8) +0.3 (logN−15)}. 3. A low-resistance semiconductor layer (1) of the first conductivity type, a high-resistance semiconductor layer (2) of the first conductivity type, and a first semiconductor layer (3) of the second conductivity type are stacked and silicon carbide is formed. A semiconductor substrate (4) formed of a first conductivity type; a semiconductor region (5) of a first conductivity type formed in a predetermined region of a surface layer portion of the first semiconductor layer; A groove penetrating the semiconductor layer, and a second semiconductor layer of a first conductivity type formed of a silicon carbide thin film formed on at least a surface of the first semiconductor layer on a side surface of the groove. A gate insulating film (9) formed on at least a surface of the second semiconductor layer; a first conductivity type gate electrode layer (10) formed on the gate insulating film in the trench; On at least a part of the surface of the semiconductor region of the surface of the semiconductor substrate A second electrode layer (1) formed on the back surface of the semiconductor substrate;
3) wherein the thickness X (μm) of the second semiconductor layer and the impurity concentration N
(Cm ⁻³ ) is Y <−10000 with respect to the withstand voltage Y (V).
A silicon carbide semiconductor device characterized by satisfying the relationship of {(X−0.6) +0.3 (logN−15)}.