JPH103091A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the production yield of a TFT and an LCD by preventing generation of a drain offset voltage Vdo of a TFT. SOLUTION: Source electrode 2a made of ITO of TFT
And the angle θ of the tapered surfaces 20, 30 formed on the opposing side surfaces of the drain electrode 3a is set to 40 ° or less. Such restriction of the taper angle is effective when the thickness d of the source electrode and the drain electrode is 80 nm or more. While maintaining the characteristic of Vdo = 0, the source electrode 2
The resistivity can be reduced by increasing the thickness of the source bus 2 (signal bus) formed at the same time as a to about 150 nm, for example. Thus, even in a relatively large LCD, a source bus can be formed with a single layer of ITO without using a metal layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device (hereinafter referred to as LCD) using a thin film transistor (hereinafter referred to as TFT) as a switching element, and more particularly to a technique for preventing a drain offset voltage of a TFT.

[0002]

2. Description of the Related Art A TFT matrix LCD has a TF inside.
A TFT array substrate in which a T matrix is formed in an array and a common electrode substrate in which a common electrode is formed on the inner surface are disposed to face each other with a liquid crystal layer interposed therebetween. In the drain voltage / current characteristics of the TFT, if there is a drain offset voltage, when performing gradation display, the change range of the gradation is narrowed and the display quality is deteriorated. Therefore, it is desirable that the offset voltage is zero. . As a conventional technique for reducing the drain offset voltage, Japanese Patent Application Laid-Open No. Sho 62-80626 entitled "Liquid Crystal Display Element" (hereinafter referred to as "cited example") has already been proposed by the same applicant as the present invention. The cited example will be briefly described with reference to FIGS. 4A and 4B similar to those used as FIGS. 12 and 1 of the specification.

FIGS. 4A and 4B are cross-sectional views of a TFT array substrate 100 before and after the application of the offset reduction technique, respectively. In FIG. 4, 1 is a glass substrate, 2 and 3
Is a source bus and a pixel electrode formed simultaneously on the glass substrate 1 by transparent ITO, and 4 is a semiconductor layer made of a-Si (amorphous silicon). Reference numerals 5 and 6 denote ohmic contact layers made of n ⁺ a-Si formed for improving electrical connection between the semiconductor layer 4 and the source bus 2 or the pixel electrode 3, and reference numeral 7 denotes SiNx or the like. A gate insulating film, 8 is a gate electrode made of aluminum or the like, and 9 is a protective layer made of SiNx or the like. The periphery of the source bus 2 and the end of the pixel electrode 3 overlapping with the gate electrode 8 are a source electrode 2a and a drain electrode 3a, respectively.

[0004] In Figure 4B, in order to prevent lowering the on / off ratio per light from the glass substrate 1 side to TFT50 portion, the write shield 12 of metal such as Cr is formed, such as SiO ₂ thereon The case where the insulating film 13 is formed is shown. In the cited example, the opposing side surfaces of the source electrode 2a and the drain electrode 3a are tapered surfaces 20, 30 having a taper angle of 45 ° formed by isotropic etching. Ohmic contact layers 5 and 6 are formed, and semiconductor layer 4 is formed on ohmic contact layers 5 and 6.
By forming the semiconductor layer 4 on the tapered surfaces 20 and 30 in this manner, the thickness of the semiconductor layer 4 can be reduced to, for example, about 500 ° to 100 °, and the ohmic contact between the source electrode 2a and the drain electrode 3a can be made. The contact area with the layers 5 and 6 can be increased, and good ohmic contact can be obtained. Therefore, in the drain voltage-current characteristics, as shown by the solid line in FIG. 5, a characteristic in which the drain offset voltage Vdo is extremely small can be obtained. In FIG. 5, the dotted line shows the characteristics of the TFT without the tapered surface shown in FIG. 4A.

Incidentally, the TFT array substrate 100 may not be provided with the protective layer 9 as shown in FIG.

[0006]

Recently, the spread of TFT matrix LCDs has been remarkable, and this tendency is expected to be further accelerated in the future. Along with this, there is a strong demand for reduction of manufacturing cost and improvement of display quality. An object of the present invention is to prevent a drain offset voltage of a TFT from being generated and to improve a manufacturing yield.

[0007]

[Means for Solving the Problems]

(1) In the first aspect of the present invention, the angle (θ) between the tapered surface formed on the opposite side surface of the source electrode 2a and the drain electrode 3a and the horizontal plane is set to 40 ° or less. (2) In the invention of claim 2, in the above (1), the thickness of the source electrode and the drain electrode is formed to be 80 nm or more.

(3) In the third aspect of the present invention, in (1), the signal bus (also referred to as a source bus) connected to the source electrode is formed integrally with ITO having the same thickness as the source electrode. I have.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the latest research by the present inventors, the offset of the drain voltage of a TFT and the tapered surface 20 formed on the source electrode 2a and the drain electrode 3a are determined.
It has been found that there is a close relationship with the taper angle θ of 30 (FIG. 1). That is, as shown in FIG. 2, the source bus 2, the source electrode 2a, the pixel electrode 3, and the drain electrode 3a
Film thickness (hereinafter simply referred to as ITO film thickness) d is 150 n
m (very thick to reduce the resistivity of the source bus 2), the taper angle θ of ITO becomes θ
When ≤40 ° or less, the drain offset voltage Vdo = 0, and when θ> 40 °, the offset voltage Vdo increases according to the taper angle θ. In the experiment, sample groups # 1, # 2, # 3, and # 4 in which the taper angles θ were set to 30 °, 40 °, 45 °, and 60 °, respectively, were produced. FIG. 2 shows the average drain offset voltage Vdo for each.
Is plotted.

Further, it has been found that the relationship shown in FIG. 3 exists between the ITO film thickness d and the taper angle θ when the offset voltage Vdo becomes 0. In the experiment, the thickness d of the ITO was 150,
Sample groups (a), (b), (c), (d), and (e) were prepared at 120, 80, 60, and 40 nm, respectively, and each of (a), (b), and (c) was prepared. In the sample group, small groups # 1, # 2, # 3, and # 4 having taper angles θ of 30, 40, 45, and 60 degrees were formed, and the drain offset voltage Vdo was measured. As a result, (a),
In each of the groups (b) and (c), the small groups # 1 and # 2
do = 0, Vdo is generated from the small group # 3,
It was found that Vdo was further increasing in small group # 4. From this result, when the film thickness d is in the range of 80 to 150 nm, the limit value of the taper angle θ at which Vdo = 0 is 40 ° to 4 °.
It can be seen that it is between 5 °. In FIG. 3, 40 ° is set as the limit value in consideration of some margin.

In the sample groups (d) and (e) in which d = 60 nm and 40 nm, θ = 90 ° was set, and Vdo = 0 in each case. If θ is set to 90 ° or less, Vdo is more unlikely to occur.
= 90 ° as the limit value. In the case of the cited example described in the conventional example, since θ = 45 ° is set by isotropic etching, the drain offset voltage Vdo slightly exists when the film thickness d is 80 nm or more. θ
In the case of> 40 °, the offset voltage Vdo exists because the angle β = 180 ° −θ between the tapered surfaces 20, 30 and the uppermost horizontal plane of ITO in FIG. 1 becomes steeper than 140 °, and Semiconductor layers 4 at edges P and Q
Of the semiconductor layer 4 becomes sharp at the edges P and Q.
This is considered to be due to cracks occurring and insufficient covering of the electrodes (called step coverage).

If the thickness of the semiconductor layer 4 is increased to prevent cracking of the semiconductor layer 4, the on / off ratio of the TFT (the ratio of the drain current when the TFT is on / off) is reduced. Can not be used. Therefore, when the thickness d of ITO is increased, the taper angle θ of ITO is reduced, the edges P and Q are moderately bent to prevent cracks, and a technique for eliminating Vdo is important.

The ITO of the sample used for obtaining the experimental results shown in FIGS. 2 and 3 is an in-line type sputtering apparatus, adopting a film forming method called DC magnetron sputtering, and setting the pressure / temperature during sputtering to 4 mTorr / 100. Set to ° C. When the thickness d of ITO was 150 nm, the resistivity was 2.9 × 10 ⁻⁴ Ωcm, which was considerably small, and the transmittance of light having a wavelength of λ = 550 nm was 96%, and excellent characteristics were obtained.

The ITO was tapered by dry etching. HI (hydrogen iodide) / Ar / O2 was used as an etching gas at the time of dry etching, the high frequency output of the etching apparatus was set to 2.9 kw, and the pressure at the time of etching was set to 20 to 30 mTorr.

[0015]

【The invention's effect】

(1) In the present invention, the angle .theta. Between the tapered surface formed on the opposite side surface of the source electrode 2a and the drain electrode 3a made of ITO of the TFT and the horizontal plane is increased from 45.degree.
° or less, and at the edges P, Q at the upper end of the tapered surface, the angle β = 180 ° −θ at which the ohmic contact layer 5 and the semiconductor layer 4 above are bent is moderated, so that cracks are formed. And the drain offset voltage Vdo can be eliminated. Therefore, Vdo characteristic defects can be prevented, and the manufacturing yield of the TFT array substrate, and thus the LCD, can be improved accordingly.

(2) According to the present invention, the thickness of the source bus (signal bus) 2 formed at the same time as the source electrode 2a is set to, for example, about 150 nm while maintaining the drain offset voltage Vdo = 0 of the TFT. By increasing the thickness, the resistivity can be considerably reduced to, for example, 2.9 × 10 ⁻⁴ Ωcm. This makes it possible to form a source bus with a single layer of ITO without using a metal layer even in a relatively large-screen LCD, which also has the effect of reducing the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a TFT array substrate used for an LCD of the present invention.

FIG. 2 is a graph showing a relationship between an angle θ of a tapered surface formed on ITO (a source electrode and a drain electrode) of the TFT in FIG. 1 and a drain offset voltage Vdo.

FIG. 3 is a diagram showing a range of a taper angle θ where Vdo = 0 for a TFT in FIG. 1;

FIG. 4 is a sectional view of a main part of a conventional TFT array substrate,
Is when the facing surfaces of the source electrode and the drain electrode are vertical,
B shows the case where the 45 ° tapered surfaces 20 and 30 are formed on the facing surface.

FIG. 5 shows drain current versus drain voltage characteristics of a conventional TFT.

FIG. 6 is a cross-sectional view of a main part of a conventional TFT array substrate in which a protective layer 9 of FIG. 5 is removed.

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[Procedure amendment]

[Submission date] October 29, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005] In some cases, the TFT array substrate 100 does not include the gate insulating film 7 on the protective layer 9 and the pixel electrode 3 as shown in FIG.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Fig. 6

[Correction method] Change

[Correction contents]

[6] The gate insulating film over the protective layer 9 and the pixel electrode 3 in FIG. 4
Sectional drawing of the principal part of the conventional TFT array substrate in which 7 is not provided .

[Procedure amendment 3]

[Document name to be amended] Drawing

[Correction target item name] Fig. 6

[Correction method] Change

[Correction contents]

FIG. 6

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/78 617N

Claims (3)

[Claims] 1. A thin film transistor is used as a switching element for selectively displaying a pixel, and a tapered surface is formed on opposite side surfaces of a source electrode and a drain electrode made of ITO of the thin film transistor, and the entire surface of the tapered surface is formed. In an active matrix type liquid crystal display element in which an ohmic contact layer is formed and a semiconductor layer is formed between the source electrode and the drain electrode so as to cover the ohmic contact layer, an angle (θ) between the tapered surface and a horizontal surface is provided. Is set to 40 ° or less. 2. The liquid crystal display device according to claim 1, wherein the source electrode and the drain electrode have a thickness of 80 nm or more. 3. The liquid crystal display according to claim 1, wherein a signal bus (also referred to as a source bus) connected to the source electrode is formed integrally of ITO having the same thickness as the source electrode. element.