JPH10312181A - How to write and read data - Google Patents

Abstract

(57) [Summary] PROBLEM TO BE SOLVED: To provide data capable of performing high-speed data access.
Data writing and reading methods. SOLUTION: Each van of a frame memory M0, M1 is provided.
Writing two-dimensional data to the blocks β0 and β1
On the horizontal A and B lines adjacent to each other
A0, A1, A2, A as write units
3, ... A_n-1, A _n, ... and data B0, B1, B2, B
3, ..., B_n-1, B_n,... For each data A, B
Although the frame memory is different, the bank number is common
And write data A_n-1And data A_n,
And data B_n-1And data B_nIn the context of each
Writing to different numbered banks in different frame memories
The same frame memo as last time
The procedure of writing to banks with different numbers
Is inserted every time the number of times α becomes 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for writing and reading data which can be used for writing and reading drawing data of a graphic device, for example.

[0002]

2. Description of the Related Art In a graphics device, a frame memory is used to write and read drawing data. In recent years, as a method of achieving high-speed processing of drawing data, a method of shortening an access time to a memory or a method of increasing a bus width to increase a data amount that can be accessed at a time have been considered.

[0003]

However, in the above-described method of increasing the data amount by widening the bus width, the number of dots that can be accessed at one time increases, so that when a small area is to be filled, useless dots are accessed. There is a possibility that a drawback occurs that the drawing performance is rather deteriorated. In addition, the frame memory is generally composed of a DRAM, which requires a precharge period, so that the next access cannot be performed immediately after the access, and the data access is not accelerated, so that the drawing performance is sufficiently improved. I have not been able to.

Japanese Patent Laid-Open Publication No. Sho 59-149391 discloses a high-speed frame buffer writing system. This method uses a vector generator (DDA: Digita).
When writing a sequence of points, which is a vector component obtained by [1 Differential Analyzer], to a frame buffer, the sequence of points is stored in a DDA buffer having a fixed capacity, and at the same time, the frame buffer is stored in the DDA.
This is a method in which the content of the DDA buffer is divided and written into the size of the buffer corresponding to the buffer, and the content of the DDA buffer is written collectively. However, this prior art does not disclose the concept described later with reference to FIGS.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data write / read method capable of performing high-speed data access.

[0006]

In order to solve the above-mentioned problems, a data writing / reading method according to the present invention uses a divided frame memory and performs two-dimensional data access when writing data. In the data reading, a data writing / reading method for performing one-dimensional data access is provided, wherein each of the divided frame memories includes two banks, and one of the banks is used for accessing each frame memory. At this time, the other access uses the other bank.

[0007] According to the above configuration, in each frame memory, when one bank is accessed, the other bank is not accessed. Therefore, even when each bank is formed of a DRAM, the access is not performed. When the data is not read, preparation for data writing / reading (precharge) in the bank is performed, and continuous access to the frame memory can be performed without time, so that data access can be performed at high speed. Be transformed into

The frame memory is divided into two, for example, frame memories M0 and M1. Each of the frame memories M0 and M1 is provided with a bank β0 and β1, respectively, and drawing data is used as write / read data. .

The two-dimensional data writing to each of the banks β0 and β1 of the frame memories M0 and M1 is performed by writing data as write units in adjacent horizontal A and B lines on the drawing surface. A0, A1, A2
A3,... _An-1 , _An ,... And data B0, B1, B2,
_{B3, ..., B n-1} , B n, ... each data A, with different but written as bank number is common frame memory together for B, the data A _n-1 and the data A _n,
And in the context of each of data B _n-1 and data B _n ,
In the process of repeatedly writing to different banks of different numbers in the frame memories different from each other, the procedure of writing to the different banks of the same frame memory as the previous time is based on the number of repetitions α = 2 ^L (L is an arbitrary number selected from natural numbers) May be inserted every time when the value of () is reached.

For example, when α = 2 (L = 1), data A0 and B0 are set to “M0 (β0), M1 (β0)” and data A1 and B1 are set to “M1 (β1), M0 (Β1) ”for data A2, B2 for“ M1 (β0), M0 (β0) ”for data A3, B3 for“ M0 (β1), M1 (β1) ”for data A4, B4 for“ M0 (β0), M1 (β0) ”to data A5, B5 to“ M1 (β1), M0 (β1) ”Data A6, B6 to“ M1 (β0), M0 (β0) ”Data A7, B7 to“ M0 (β1) , M1 (β1) ”.

If α = 4 (L = 2), data A0 and B0 are set to “M0 (β0), M1 (β0)” and data A1 and B1 are set to “M1 (β1), M0 (Β1) ”to data A2, B2 to“ M0 (β0), M1 (β0) ”to data A3, B3 to“ M1 (β1), M0 (β1) ”to data A4, B4 to“ M1 (β0), M0 (β0) ”to data A5, B5 to“ M0 (β1), M1 (β1) ”to data A6, B6 to“ M1 (β0), M0 (β0) ”to data A7, B7 to“ M0 (β1) ” , M1 (β1) ”.

If α = 8, the data A0 and B0 are changed to “M0 (β0), M1 (β0)” and the data A1 and B1 are changed to “M1 (β1), M0 (β1)”. Data A2, B2 to “M0 (β0), M1 (β0)” Data A3, B3 to “M1 (β1), M0 (β1)” Data A4, B4 to “M0 (β0), M1 (β0)” Data A5, B5 to “M1 (β1), M0 (β1)” Data A6, B6 to “M0 (β0), M1 (β0)” Data A7, B7 to “M1 (β1), M0 (β1) Data A8, B8 to "M1 (β0), M0 (β0)" Data A9, B9 to "M0 (β1), M1 (β1)" Data A10, B10 to "M1 (β0), M0 (β0) )) And data A11 and B11 to “M0 (β1), M1 (β1)” and data A12 and B12 to “M1 (β0 , M0 (β0) ”to data A13, B13 to“ M0 (β1), M1 (β1) ”Data A14, B14 to“ M1 (β0), M0 (β0) ”Data A15, B15 to“ M0 (β1 ), M1 (β1) ”.

The two-dimensional data writing to the banks .beta.0 and .beta.1 of the frame memories M0 and M1 is performed by writing data as write units in the horizontal A and B lines adjacent to each other on the drawing surface. A0, A1, A2
A3,... _An-1 , _An ,... And data B0, B1, B2,
For B3,..., B _n−1 , B _n ,..., Data A0, B0 to “M0 (β0), M1 (β0)” Data A1, B1 to “M1 (β0), M0 (β0)” A2 and B2 are replaced with "M0 (β1), M1 (β1)" Data A3 and B3 are replaced with "M1 (β1), M0 (β1)" As shown in FIG. 2 but is written as a common, data a _n-1 and the data a _n, and data in the context of each of the B _n-1 and the data B _n, the writing frame memory bank different but same number to each other You may make it repeat what is done every time.

The two-dimensional data writing to each of the banks β0 and β1 of the frame memories M0 and M1 is performed by writing data as write units in adjacent horizontal A and B lines on the drawing surface. A0, A1, A2
A3,... _An-1 , _An ,... And data B0, B1, B2,
For B3,..., B _n−1 , B _n ,..., Data A0, B0 to “M0 (β0), M1 (β0)” Data A1, B1 to “M0 (β1), M1 (β1)” A2 and B2 are replaced by "M1 (β0), M0 (β0)" Data A3 and B3 are replaced by "M1 (β1), M0 (β1)" 2 but is written as a common, data a _n-1 and the data a _n, and the context of each of the data B _n-1 and the data B _n, bank number are different from each other to be written to the same frame memory You may make it repeat what is done every time.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) An embodiment of the present invention will be described below with reference to FIGS. 1 to 16. Prior to the description,
The concept underlying the present invention will be described with reference to FIGS.

A graphics device is characterized in that polygon data (hereinafter, referred to as polygon data) is often written in a frame memory. Therefore, it is considered that the frame memory is divided into a two-dimensional area of “m dots × n dots”, two-dimensional data access is performed, and access to useless dots in the case of one-dimensional data access is reduced. Was. Specifically, as shown in FIG. 18, when writing polygon data, for example, 4 × 2
Dot (two 4 x 1 dot unit frames in the vertical direction in the figure)
The data access is performed two-dimensionally as described above, and the data is accessed one-dimensionally as 8 × 1 dots (two unit frames of 4 × 1 dots in the figure in the horizontal direction) when reading polygon data. According to this method, it is sufficient to access six areas (-in FIG. 18),
The number of accesses is reduced as compared with the case of performing dimensionally (in this case, access to 12 areas is necessary).

FIG. 17A is an explanatory diagram showing the data arrangement corresponding to the dot arrangement on the drawing surface. FIGS. 17B and 17C show two frame memories M0 and M0.
FIG. 4 is an explanatory diagram showing the contents of stored data of each of M1. In these figures, data (A0,
A1, B0, etc.) are data for 4 × 1 dots, respectively, where A indicates data on the A-th row, and B indicates data on the B-th row. When one dot is composed of 8-bit data, data A0 and the like are 3 bits.
It becomes 2-bit data. The bus width (the amount of data that can be accessed at one time) is 64 bits.

When writing data, first, two-dimensional data access of 4 × 2 dots is performed on data A0 and data B0, and data A0 is written into frame memory M0 and data B0 is written into frame memory M1. . Next, two-dimensional data access of 4 × 2 dots is performed on the data A1 and the data B1, and the data B1 is written in the frame memory M0 and the data A1 is written in the frame memory M1. Thereafter, similar access is performed, and data is written into the frame memory M0 as shown in FIG. 17B, and data is written into the frame memory M1 as shown in FIG.

On the other hand, at the time of data reading, one-dimensional data access to the frame memories M0 and M1 is performed, and 8 × 1 dot data for the data A0 and A1 and 8 × 1 dot data for the data A2 and A3. Data access is performed in the order of data. Note that B
In the data in the row, since the data B0 is stored in the frame memory M1 and the data B1 is stored in the frame memory M0, these data B0 and B1 are stored in a shift register (not shown) and read out in a predetermined order. Become.

In the above description, the concept and the method which are the premise of the present invention have been described. However, such a method cannot solve the decrease in the data processing speed caused by the precharge period when the DRAM is used as the frame memory.

Therefore, a data writing / reading method of the present invention has been devised which can increase the data processing speed even when a DRAM is used as a frame memory. Hereinafter, a method for writing and reading data according to the present invention will be described.

FIG. 1 is a block diagram showing a schematic configuration of a three-dimensional graphics apparatus using the data writing / reading method of the present invention. The three-dimensional graphics device includes a geometric conversion unit 1, a drawing unit 2, and a display unit 3.

The geometric conversion unit 1 performs calculation processing called modeling conversion, visual field conversion, and perspective conversion using one piece of three-dimensional polygon data as a minimum unit.

The drawing unit 2 generates pixel data (RGB) according to the plane coordinate values of the polygon generated by the geometric conversion unit 1.
In some cases, the pixel data may be a LUT address of a Look Up Table method, and the pixel data may be written to the frame memory 15. During the display period, the data may be read from the frame memory 15 according to the scanning of the display unit 3. The data is transferred to the display unit 3.

The display unit 3 displays the data transferred from the drawing unit 2 on a CRT (not shown).

FIG. 2 is a block diagram showing a specific example of the configuration of the drawing section 2. As shown in FIG. In the drawing unit 2, the data write / read method of the present invention is performed. Vertical DDA (D
digital Differential Anali
zer) 4 receives the data from the geometric transformation unit 1, obtains data of both left and right end points of each vertical line from the data, and transfers the data to two horizontal DDAs 5 and 6. The data at the left and right end points indicate, for example, the position information of each pixel at the edge of the polygon shown in FIG. The horizontal DDAs 5 and 6 obtain pixel data on the screen between both end points based on the data at the left and right end points, and write the data to the buffers 7 and 8.

Here, one dot (pixel) data is composed of 8 bits, and is composed of 4 × 1 dot units (4 in FIG. 14).
The processing is performed in a unit frame of × 1 dot). Therefore, the buffers 7 and 8 are respectively shown in FIG.
As shown in (1), data for 4 × 1 dots are held, and the data output bus width of the buffers 7 and 8 is 32 bits. It should be noted that the two horizontal DDAs 5 and 6 (two buffers 7 and 8) are provided because, in this embodiment, a two-dimensional drawing write is performed in units of two lines.

The buffers 7 and 8 are connected to a frame memory 15 via a MUX (multiplexer) 9 and an FM bus control 12. When data is filled in the buffers 7 and 8 (that is, when data of 4 × 2 dots is stored), the data is sent to the FM bus control 12 through the MUX 9. The MUX is controlled by an X coordinate address on the screen of data of 4 × 2 dots, and outputs data of 4 × 2 dots to an FM (frame memory) bus control 12 by exchanging two sets of 32-bit buses. It has become.

4A, the FM bus control 12 accesses the frame memory 15 in units of 4.times.2 dot data (4 dot.times.2 line data) as shown in FIG. To write data. On the other hand, at the time of display reading, as shown in FIG. 3B, the frame memory 15 is divided into 8 × 1 dot data (8 dot × 1 line data).
To read data.

The frame memory 15 is provided with two frame memories M0 and M1 (hereinafter, when any one of the frame memories M0 and M1 is indicated without being specified, only the symbol M is attached). Process with bit width. In this embodiment, the frame memory M is constituted by a synchronous DRAM.

The synchronous DRAM has two banks β.
0, β1 (hereinafter, when either of the banks β0, β1 is indicated without specifying, only the symbol β is added), and high-speed access is enabled by alternately accessing these two banks β0, β1. It is. This synchronous D
The RAM will be described with reference to FIGS. FIG. 5 is an explanatory diagram conceptually showing an example of a synchronous DRAM. FIG. 6A shows the timing at the time of burst reading when CASLatency = 3 and Burst length = 4, and FIG.
Indicates the timing at the time of burst write.

In FIG. 6A, first, Active
0 activates the Row address of bank β0,
When the column address is set by the read command, 3
Data is output after the cycle. Next, the bank β0 can be activated only in Active0 two cycles after the last data output, and the next data access is delayed. However, if data of bank β1 is accessed after reading of bank β0, bank β1 can be activated by the command in the hatched portion in FIG. 6, so that data access can be performed immediately after the read cycle of bank β0. And high-speed access is possible. Similarly, at the time of the burst write in FIG. 6B, high-speed access is enabled by alternately using the banks β0 and β1.

The MUX (multiplexer) 10 is connected to the FM bus control 12 and selects and shifts required 32-bit data from the 32-bit × 2 data read from the frame memory 15. Output to register 11.

FIG. 7 shows the MUX 10 and the shift register 11
FIG. 3 is a block diagram showing an example of a connection configuration relationship. MU
X10 includes eight MUX units 10a to 10h, and the shift register 11 also includes eight shift register units 11a to 11h.
11h. The MUX unit 10a is connected to the shift register unit 11a, and the MUX unit 10b is connected to the shift register unit 1a.
1b, and so on. Each of the shift register sections 11a to 11h stores 4 × 1 dot data (32
Bit data) is held, and the timing of this holding is set by a control signal given to the shift register units 11a to 11h. Also, the MUX units 10a to 10h
Are also made by the control signals given to them.

Next, the form of the drawing light will be described with reference to FIG. FIG. 7A is an explanatory view showing the data arrangement corresponding to the dot arrangement on the drawing surface, and FIG. 8B shows the contents of data stored in the banks β0 and β1 of the frame memory M0. FIG. 9C is an explanatory diagram showing the contents of data stored in the banks β0 and β1 of the frame memory M1.

In these figures, data (A0, A1, B0, etc.) constituting one unit frame is 4 × 1
A is data for a dot, A is data on the A line, B is data on the B line, C is data on the C line, D is data on the D line. Respectively. When one dot is composed of 8-bit data, data A0 and the like are 32-bit data. The bus width (the amount of data that can be accessed at one time) is 64 bits.

At the time of writing data, first, two-dimensional data access for 4 × 2 dots is performed for data A0 and data B0, and data A0 is stored in bank β0 of frame memory M0 and bank β0 of frame memory M1. Is written with data B0. Next, two-dimensional data access of 4 × 2 dots is performed on the data A1 and the data B1, and the data A1 is written to the bank β1 of the frame memory M1 and the data B1 is written to the bank β1 of the frame memory M0. Thereafter, similar access is performed, and data is written into the frame memory M0 as shown in FIG. 3B, and data is written into the frame memory M1 as shown in FIG.

It should be noted that the manner of writing to the banks β0 and β1 of the two frame memories M0 and M1 will be briefly described. Data A0 and B0 are converted to “M0 (β0), M1 (β0)”. B1 to “M1 (β1), M0 (β1)” Data A2, B2 to “M0 (β0), M1 (β0)” Data A3, B3 to “M1 (β1), M0 (β1)” Data A4 , B4 to “M1 (β0), M0 (β0)” Data A5, B5 to “M0 (β1), M1 (β1)” Data A6, B6 to “M1 (β0), M0 (β0)” A7 and B7 are changed to "M0 (β1), M1 (β1)". That is, the data A and B are written so that the frame memories are different from each other but the bank numbers are common, and the data A _n-1 and the data A _n , and the data B _n-1 and the data B _{n in} the _order of the data, This is to write to different numbered banks of different frame memories, and as such writing is repeated,
A procedure for writing to a bank of a different number in the same frame memory as the previous time is inserted every time the number of repetitions α becomes 4.

On the other hand, at the time of reading data, the data A is first stored in each bank β0 of the frame memories M0 and M1.
One-dimensional data access of 8 × 1 dots for 0 and A4 is performed. Next, in each bank β1 of the frame memories M0 and M1, 8 × 1 dots of data A5 and A1 are accessed.
One-dimensional one-dimensional data access is performed. Thereafter, the same access is performed up to data A7. Note that the bank β0 is used twice consecutively, and thereafter the bank β1 is continuously used twice.
Alternatively, the banks may be alternately used by using each bank twice (see FIG. 9A).

Here, when the data A0 and A4 are read, the shift registers 11a and 11e enter a data write state, and the MUX 10 connected to these shift registers 11a and 11e.
a, 10e, the MUX unit 10a converts the data A0 into
Switching is performed so that the MUX unit 10e selects the data A4. When the data A5 and A1 are read next time, the shift register units 11f and 11f
b enters a data write state, and M connected to these
In the UX units 10f and 10b, switching is performed so that the MUX unit 10f selects data A5 and the MUX unit 10b selects data A1. The same applies to other data. Thus, the data A0 to A7 are sequentially stored in the shift register units 11a to 11h. Therefore, data A0 to A7 are output from the shift register in this order.

Next, an example of the timing of reading and writing of the banks β0 and β1 in each frame memory M will be described. FIG. 9 shows each frame memory M when one dot is composed of 8 bits (8-bit color).
10 is a timing chart showing an example of the timings at the time of reading and writing of the bank β with respect to the frame memory M. Both the frame memories M0 and M1 operate as shown in FIG. In FIG. 9, CAS Latency = 3, Burst leng
The case where th1 is set is shown.

At the time of drawing writing, as shown in FIG. 9B, the column address (C0w) of the bank β0 after two clocks after the setting of the raster address (R0) of the bank β0.
Is set, and data (Pw) is written at this timing. Then, at the next clock of the column address (C0w), the lath address (R1) of the bank β1 is set, and thereafter the column address is set and data is written. In this figure, each data (P
w) A0 / B0, B1 / A1, etc. shown below represent the contents of the write data corresponding to FIG. 8, and for example, the above A0 / B0 is stored in the bank β0 of the frame memory M0. The data A0 is stored in the bank β0 of the frame memory M1.
Means that the data B0 is respectively written to

At the time of display reading, as shown in FIG. 9A, two clocks after the setting of the raster address (R0) of the bank β0, the raster address (R
Set 1). Then, the lath address (R0),
(R1) twice for each column address (C0
r, C0r) and (C1r, C1r) are repeatedly set. Data (Pr)... Are read out three clocks after the column address is set, but by setting the column address as described above, 16 data reads are performed continuously for one frame memory M. . In this figure, A0 / A4, A2 / B6, and the like described below each data (Pr) represent the contents of the read data corresponding to FIG.
0 / A4 means that data A0 is read from bank β0 of frame memory M0 and data A4 is read from bank β0 of frame memory M1.

Here, in order to correspond to the data reading shown in FIG. 9A, the shift register 11 shown in FIG.
It is configured using two buffers each having a capacity of 128 dots × 8 bits. Then, the data of 128 dots × 8 bits obtained by 16 data readings is stored in one buffer, and while the data is shifted from the one buffer to the display unit 3, the data is transferred to the frame memories M0 and M1. Data writing is performed, and a process of sequentially storing data of 128 × 8 bits obtained in the next 16 data reads from the frame memories M0 and M1 in the other buffer is performed.

In FIG. 9A, the data access is performed 16 times. However, since the data A0 to A7 to be continued can be read by the four accesses, the MUX 10 and the shift register 11 are basically provided. May have a configuration corresponding to FIG. As shown in FIG. 9A, the data access is performed 16 times not only when one dot is set to an 8-bit color but also when one dot is set to a 16-bit color or a 24-bit color. This is because the continuous readout period is secured to some extent and the precharge period is omitted.

FIG. 10 is a timing chart showing timings at the time of drawing writing and display reading when one dot is 16-bit color. In this case, FIG.
The difference from this is that the shift register 11 is 64 dots × 1
A point configured by using two buffers each having a capacity of 6 bits,
In addition, two-dimensional data access of 4 × 2 dots at the time of drawing writing and one-dimensional data access of 8 × 1 dots at the time of display reading are both performed by two accesses. For example, the first of two accesses during display read
The first access is performed in the same manner as in FIG. 9A (that is, 8-bit data of the 16-bit data of each dot is obtained), and the second access is performed as shown in FIG. A0 '/ A described below each data (Pr)
4 ', A2' / B6 ', etc., so that the remaining 8-bit data of each dot is obtained. The data A0 'and the data B0' are stored in each of the frame memories M0 and M0.
1 is stored as indicated by the dotted lines in FIGS. 8B and 8C. Similarly, when it is desired to use 24-bit color, it is sufficient to perform access three times.

Further, in this embodiment, FIG.
As shown in (b), only writing is performed at the timing of drawing light. However, this drawing light is read by a Z-buffer method for three-dimensional graphics processing or a read-modify write for alpha blending (data temporarily stored in the frame memory). To read, perform internal processing, and immediately write). The read-modify-write in the Z-buffer method will be briefly described with reference to FIG. In clock 1 of this figure, R0
Is set, and C0r (read) is set at clock 3. Then, at clock 6, data Zr is read. Then, at clock 8, C0w (write)
Is set, the data Zw is written at this timing.

Although it has been described above that data A0 to A7 which should be continuous in four accesses can be read, data A0 and A1 which should be continuous in one access can be obtained by devising a read address. , Or A2, A3, or A4, A5,... In other words, the banks of the frame memory M0 and the frame memory M1 may be used differently, and the same bank may be accessed twice successively. For example, for data A0, A1, and data A2, A3, access to bank β0 for frame memory M0 and access to bank β1 for frame memory M1 can be continued twice. I just need. FIG. 12 shows the specific read address.

Also, the case where the two-dimensional data access is set to two lines has been described as an example. For example, in the case of four lines, four horizontal DDAs, four 4 × 1 pixel buffers, and four frame memories are provided in FIG. Then, the writing process of the pixel data may be performed as shown in FIG. FIG. 3A is an explanatory diagram showing a data arrangement corresponding to a dot arrangement on a screen.
FIG. 4B shows four frame memories M0, M1, and M.
FIG. 3 is an explanatory diagram showing the contents of data stored in banks β0 and β1 of M2 and M3.

For example, data A0, B0, C0, D0,
Data A1, B1, C1, D1, data A2, B2, C
, D2, and data A3, B3, C3, D3,... Are written as “M0 (β0), M1 (β0), M2 (β0), M3
(Β0) ”“ M1 (β1), M2 (β1), M3 (β1), M0
(Β1) ”“ M2 (β0), M3 (β0), M0 (β0), M1
(Β0) ”“ M3 (β1), M0 (β1), M1 (β1), M2
(Β1) ”...

In the example described above, the data A0, A1,
A2, A3,... A _n−1 , A _n ,.
B2, B3, ..., B n -1, B n, ... each data A, with different but written as bank number is common frame memory together for B, the data A _n-1 and the data A _n, and data In the context of each of B _n-1 and data B _n , while writing to different numbers of banks of different frame memories is repeated, the procedure of writing to different numbers of banks of the same frame memory as the previous time is repeated. The insertion is performed every time the number of times α becomes 4. However, the present invention is not limited to the case where the number of times of repetition α is 4, and may satisfy the condition of α = 2 ^L (L is an arbitrary number selected from natural numbers).

If α = 2 (L = 1), two-dimensional writing of data A0, B0, data A1, B1, data A2, B2, data A3, B3,. M0 (β0), M1 (β0) ”for data A1, B1 for“ M1 (β1), M0 (β1) ”for data A2, B2 for“ M1 (β0), M0 (β0) ”for data A3, B3 Data A4, B4 for “M0 (β1), M1 (β1)” Data A5, B5 for “M0 (β1), M0 (β1)” Data A6, B6 To “M1 (β0), M0 (β0)” and data A7, B7 to “M0 (β1), M1 (β1)”. FIG. 13 shows the contents of write data in each bank of the frame memories M0 and M1 when α = 2. FIG. 14A shows the read timing when α = 2, and FIG. 14B shows the write timing. The timing itself is not different from the case of FIG.

If α = 8 (L = 3), two-dimensional writing of data A0, B0, data A1, B1, data A2, B2, data A3, B3,. M0 (β0), M1 (β0) ”for data A1, B1 for“ M1 (β1), M0 (β1) ”for data A2, B2 for“ M0 (β0), M1 (β0) ”for data A3, B3 Data A4, B4 for “M1 (β1), M0 (β1)” Data A5, B5 for “M1 (β1), M0 (β1)” Data A6, B6 To "M0 (β0), M1 (β0)" Data A7, B7 to "M1 (β1), M0 (β1)" Data A8, B8 to "M1 (β0), M0 (β0)" Data A9, B9 is set to “M0 (β1), M1 (β1)”. Data A10 and B10 are set to “M1 (β0), M1”. (Β0) ”for data A11, B11 for“ M0 (β1), M1 (β1) ”for data A12, B12 for“ M1 (β0), M0 (β0) ”for data A13, B13 for“ M0 (β1), The data A14 and B14 become “M1 (β0), M0 (β0)” and the data A15 and B15 become “M0 (β1) and M1 (β1)”. FIG. 15 shows the write data contents of each bank of the frame memories M0 and M1 when α = 8. FIG. 16A shows the read timing when α = 8, and FIG. 16B shows the write timing. The timing itself is not different from the case of FIG.

In FIG. 9, FIG. 14, and FIG. 16, the lath address (R1) of the bank β1 is set two clocks after the lath address (R0) of the bank β0 is set, and the same address is applied twice from the same bank. In this case, when the lath address (R0) of the bank β0 is set and the lath address (R1) of the bank β1 can be immediately set, the bank β0 and the bank β1 may be alternately read. it can. Also, the magnitude of α affects the size of the buffer that temporarily holds the read data,
The smaller α is, the smaller the buffer amount can be.

(Embodiment 2) Next, another embodiment of the present invention will be described with reference to FIG. FIG. 19 (a)
FIG. 19B is an explanatory diagram showing the data arrangement corresponding to the dot arrangement on the screen. FIG.
FIG. 7 is an explanatory diagram showing the contents of data stored in banks β0 and β1 of 0 and M1, respectively.

In this embodiment, the frame memory M
0, M1 two-dimensional data to each bank β0, β1
Data writing in the horizontal direction A adjacent to each other on the drawing surface.
Data that is each writing unit in line and B line
A0, A1, A2, A3,... A _n-1, A_n, ... and data
B0, B1, B2, B3, ..., B_n-1, B_n, ...
The data A0 and B0 are converted to “M0 (β0), M1 (β0)”. The data A1 and B1 are converted to “M1 (β0), M0 (β0)”. )) And data A3 and B3 as “M1 (β1), M0 (β1)”.
If the banks are written differently but have the same bank number,
Data A_n-1And data A_n, And data B_n-1When
Data B_nIn the context of each
Rewriting is different, but writing to the same numbered bank twice
Repeat what you do.

Here, paying attention to each frame memory M, the order becomes β0 → β0 → β1 → β1, so that every other bank is not used alternately. That is, every other bank is used alternately.

However, the data reading is performed as follows: "M0 (β0), M1 (β0)", "M0 (β1), M1 (β1)", "M0 (β0), M1 (β0)", "M0 (β1), M1 ( β1) ”..., then (A0 / A1), (A2 / A3),
.. Has the advantage that data can be read out continuously. That is, in the first embodiment, as described above, in order to ensure the continuity of the read data, in each of the frame memories M0 and M1, the banks are used differently, and the access to the same bank is performed. It is necessary to devise two consecutive times. On the other hand, according to this embodiment, there is an advantage that continuity of read data can be ensured without such a device.

(Embodiment 3) Next, another embodiment of the present invention will be described with reference to FIGS. FIG. 20A is an explanatory diagram showing the data arrangement corresponding to the dot arrangement on the screen, and FIG.
Banks β0, β of the two frame memories M0, M1
FIG. 3 is an explanatory diagram showing the contents of storage data of No. 1;

In this embodiment, the frame memory M
0, M1 two-dimensional data to each bank β0, β1
Data writing in the horizontal direction A adjacent to each other on the drawing surface.
Data that is each writing unit in line and B line
A0, A1, A2, A3,... A _n-1, A_n, ... and data
B0, B1, B2, B3, ..., B_n-1, B_n, ...
Data A0 and B0 are "M0 (β0), M1 (β0)" Data A1 and B1 are "M0 (β1), M1 (β1)" Data A2 and B2 are "M1 (β0), M0 (β0) )) And data A3 and B3 as “M1 (β1), M0 (β1)”.
If the banks are written differently but have the same bank number,
Data A_n-1And data A_n, And data B_n-1When
Data B_nIn each context, the bank numbers are
Write twice to different but same frame memory
Repeat what you do.

In this embodiment, since data to be consecutive belongs to the same frame memory, continuity of read data cannot be ensured.

Therefore, in the data continuity, the third embodiment has a disadvantage with respect to the data writing / reading method of the second embodiment, but the second embodiment has a disadvantage.
In the data write operation, every other bank is used alternately in writing data. On the other hand, the third embodiment has an advantage that every other bank can be used alternately. Become.

FIG. 21 shows a MUX in this embodiment.
100a, 100b and shift registers 110a, 110
It is the block diagram which showed an example of the connection structure of b, 110c, 110d. When, for example, data A0 and A3 are input to the two input terminals In0 and In1, respectively, one of them is shifted by the MUX 100a to the shift registers 110a and 110a.
10c, and the other is supplied to shift registers 110b and 110d in MUX 100b. One of shift registers 110a and 110c receives a control signal from a signal line (not shown) so that only one of them holds given data, and one of shift registers 110b and 110d holds only one given data. As described above, the control signal is received from a signal line (not shown). With such a configuration, shift registers 110a, 11
0b, 110c, and 110d include data A0, A1, A
2, A3 are stored in this order, and are read out in this order.

[0064]

As described above, according to the present invention,
It is possible to perform one-dimensional data access and two-dimensional data access using a single-port frame memory, and to perform continuous access to the frame memory without time delay, thereby increasing the speed of data access and drawing. This has the effect of improving performance.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a graphics device.

FIG. 2 is a block diagram showing a specific configuration of a drawing unit in which the data write / read method of the present invention is implemented.

FIG. 3 is an explanatory diagram showing a data processing unit composed of 1 × 4 dots according to the present invention.

FIGS. 4A and 4B are diagrams showing the present invention, wherein FIG. 4A is an explanatory diagram of two-dimensional data access at the time of data writing, and FIG. 4B is one-dimensional data access at the time of data reading; FIG.

FIG. 5 is a conceptual diagram of a frame memory including a synchronous DRAM of the present invention.

FIG. 6A is a timing chart showing a burst read timing of the synchronous DRAM, and FIG. 6B is a timing chart showing a burst write timing of the synchronous DRAM.

FIG. 7 is a block diagram showing an example of a connection configuration relationship between the MUX and the shift register in FIG. 2 of the present invention.

FIGS. 8A and 8B are diagrams showing the present invention, wherein FIG. 8A is an explanatory diagram showing a data arrangement corresponding to a dot arrangement on a screen, and FIG. 8B and FIG. FIG. 9 is an explanatory diagram showing the contents of data stored in each bank of the frame memory when the number of repetitions α is 4.

9A and 9B are diagrams showing the present invention, wherein FIG. 9A is a timing chart showing the timing at the time of display reading of a frame memory composed of a synchronous DRAM, and FIG. 6 is a timing chart showing timing (1 dot is 8-bit color).

10A and 10B are diagrams showing the present invention, wherein FIG. 10A is a timing chart showing the timing at the time of display reading of a frame memory composed of a synchronous DRAM, and FIG. 6 is a timing chart showing timing (1 dot is 16-bit color).

FIG. 11 is an explanatory diagram when two-dimensional data access is performed in four lines in the present invention, and FIG. 11A is an explanatory diagram showing a data arrangement corresponding to a dot arrangement on a screen. FIG. 3B is an explanatory diagram showing the contents of data stored in each bank of the frame memory.

FIG. 12 is a timing chart showing the timing at the time of display reading when the continuation of read data is secured in the present invention.

FIGS. 13A and 13B are diagrams showing the present invention, and FIGS. 13A and 13B are explanatory diagrams showing the contents of data stored in each bank of the frame memory when the number of repetitions α is 2. FIG. It is.

14A and 14B are diagrams corresponding to FIG. 13, wherein FIG. 14A is a timing chart showing a timing at the time of display reading, and FIG. 14B is a timing chart showing a timing at the time of drawing writing; .

15A and 15B are diagrams showing the present invention, and FIGS. 15A and 15B are explanatory diagrams showing the contents of data stored in each bank of the frame memory when the number of repetitions α is 8. FIG. It is.

16 is a diagram corresponding to FIG. 15, wherein FIG. 16A is a timing chart showing a timing at the time of display reading, and FIG. 16B is a timing chart showing a timing at the time of drawing writing; .

17A and 17B are diagrams for explaining the concept underlying the present invention, wherein FIG. 17A is an explanatory diagram showing a data arrangement corresponding to a dot arrangement on a screen, and FIG. FIG. 3C is an explanatory diagram showing the contents of data stored in the frame memory.

FIG. 18 is a diagram for explaining the concept underlying the present invention, and is an explanatory diagram for explaining two-dimensional writing / one-dimensional reading for polygon data.

FIGS. 19A and 19B are diagrams showing a second embodiment of the present invention, in which FIG. 19A is an explanatory diagram of two-dimensional data access at the time of data writing, and FIG. FIG. 3 is an explanatory diagram of one-dimensional data access.

FIG. 20 is a diagram showing a third embodiment of the present invention, wherein FIG. 20 (a) is an explanatory diagram of two-dimensional data access at the time of data writing, and FIG. 20 (b) is a diagram at the time of data reading; FIG. 3 is an explanatory diagram of one-dimensional data access.

FIG. 21 is a diagram illustrating a third embodiment of the present invention,
FIG. 3 is a block diagram illustrating an example of a connection configuration between a UX and a shift register.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Geometric conversion part 2 Drawing part 3 Display part 4 Vertical DDA 5 Horizontal DDA 6 Horizontal DDA 7 Pixel buffer 8 Pixel buffer 9 MUX 10 MUX 11 Shift register 12 FM bus control 15 Frame memory

Claims (5)

[Claims] 1. A data writing / reading method in which a frame memory is divided and used to perform two-dimensional data access during data writing and one-dimensional data access during data reading. A method for writing and reading data, wherein each of the divided frame memories includes two banks, and when one of the banks is used for accessing each frame memory, the other bank is used for the next access. 2. The frame memory is divided into two frame memories M0 and M1.
2. The data writing / reading method according to claim 1, wherein banks 0 and M1 are provided in 0 and M1, respectively, and drawing data is used as write / read data. 3. Each of the frame memories M0 and M1
Writing two-dimensional data to banks β0 and β1
Horizontal A and B lines adjacent to each other on the screen
A0, A1, A, which are the respective write units in
2, A3, ... A _n-1, A_n, ... and data B0, B1, B
2, B3, ..., B_n-1, B_n, ... for each data A, B
Frame memories are different from each other but the bank numbers are common
And write data A_n-1And data A
_n, And data B_n-1And data B _nIn each context of
Are different numbered banks of different frame memories
In the same frame as the previous
The procedure for writing to banks of different numbers in
The number of repetitions α is α = 2^L(L is a natural number
Each time it reaches a certain value).
A method for writing and reading data according to claim 2. 4. Each of the frame memories M0 and M1
Writing two-dimensional data to banks β0 and β1
Horizontal A and B lines adjacent to each other on the screen
A0, A1, A, which are the respective write units in
2, A3, ... A _n-1, A_n, ... and data B0, B1, B
2, B3, ..., B_n-1, B_n,..., Data A0, B0 to “M0 (β0), M1 (β0)” Data A1, B1 to “M1 (β0), M0 (β0)” Data A2, B2 to “M0 (β1), M1 (Β1), data A3 and B3 as “M1 (β1), M0 (β1)”, and so on.
Write so that the bank number is common, and
A_n-1And data A_n, And data B_n-1And data B_nof
In each context, the frame memories are different from each other,
Writing to the same numbered bank twice
3. The data book according to claim 2, wherein the data is repeated.
Reading method. 5. Each of the frame memories M0 and M1
Writing two-dimensional data to banks β0 and β1
Horizontal A and B lines adjacent to each other on the screen
A0, A1, A, which are the respective write units in
2, A3, ... A _n-1, A_n, ... and data B0, B1, B
2, B3, ..., B_n-1, B_n,..., Data A0, B0 to “M0 (β0), M1 (β0)” Data A1, B1 to “M0 (β1), M1 (β1)” Data A2, B2 to “M1 (β0), M0 (Β0) ”for data A3 and B3 for“ M1 (β1), M0 (β1) ”.
Write so that the bank number is common, and
A_n-1And data A_n, And data B_n-1And data B_nof
In each context, the bank numbers are different but the same
Writing to the frame memory twice
3. The data book according to claim 2, wherein the data is repeated.
Reading method.