JPH10312183A - Display control device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To realize a display control device capable of continuously displaying the same display data even with a small capacity of a RAM for storing a display code. SOLUTION: A buffer 111 for storing display data outputted from a ROM 105, and a selector 11 for selecting one of the display data of the ROM 105 and the buffer 111
And a continuous display control bit for continuous display, instead of continuously storing the same display code a in the RAM 103 in order to continuously output the same RGB display data to the display device 107. A display code b including a number-of-times bit is stored. When the display code b is decoded by the ROM address generation unit 104, the selector 112 stores the buffer 1
Eleven display data are selected and output continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for data displayed on a display device such as a CRT.

[0002]

2. Description of the Related Art In recent years, in order to display various information such as channels and volume on a display device such as a CRT, display data stored in a ROM is read out in the order of display codes stored in a RAM, and RGB display data is read out. A display control device for converting into a TV set is used in a TV set or the like.

FIG. 2 is a block diagram of a conventional display control device. In FIG. 2, reference numeral 201 denotes a conventional display control device;
02 is a CPU, 103 is a RAM in which a display code to be displayed on the display device 107 is stored, 104 is a ROM
An address generation unit, 105 is a ROM storing display data, 106 is a color conversion unit that converts display data read from the ROM 105 into RGB display data, and 107 is a display device.

The operation of the conventional display control device configured as described above will be described below. Display codes are stored in the RAM 103 in advance in the order of display by the CPU 102, and the display codes are stored in the CPU 1
02 according to the RAM address output from the RAM 103
And is input to the ROM address generation unit 104. The ROM address generation unit 104 decodes the display code and outputs a ROM address for accessing the ROM 105 storing the display data. This R
Display data is output from the ROM 105 according to the OM address, and is input to the color conversion unit 106. The color conversion unit 106 converts display data input from the ROM 105 into RGB display data that can be displayed on the display device 107 and outputs the data to the display device 107. In the display device 107, the RAM 10
3 are displayed in the order of the display codes stored.

In the conventional example shown in FIG. 2, "AAA"
A display example of a character string "B" is shown.
The display code stored in M103 is provided with a display end bit indicating whether or not to end the display. When the display end bit is, for example, "1", the ROM address generation unit 10
4 and is notified to the CPU 102,
Display is completed.

[0006]

However, in the above-described conventional configuration, even if the same display data is to be displayed continuously, the display codes indicating the same display data must be stored in the RAM 103 by the number of consecutive display data. For this reason, there is a problem that the capacity of the RAM 103 increases.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a display control device which enables continuous display of the same display data even with a small amount of RAM for storing display codes. I do.

[0008]

According to a first aspect of the present invention, there is provided a display control device comprising: a CPU; and a RAM for outputting a display code stored in advance by an address output from the CPU.
A display data memory address generation unit for decoding a display code output from the RAM to generate a display data memory address, and display data stored in advance by a display data memory address output from the display data memory address generation unit A display data memory for outputting the display data, a buffer memory for storing the display data output from the display data memory, and selecting one of the display data output from the display data memory and the display data stored in the buffer memory. A display code including a control bit for continuously displaying, instead of continuously storing the same display code in the RAM to continuously output the same display data from the selector. And the display data memory address generator generates a continuous table. When a display code including a control bit for decoding is decoded, a continuous display control signal is issued to the selector, and when the continuous display control signal is input, the selector selects and outputs the display data stored in the buffer memory. When the continuous display control signal is not input, the display data output from the display data memory is selected and output.

With this configuration, when the same display data is continuously output and displayed, one display code corresponding to the display data to be displayed and a display code including a control bit for continuous display are stored in the RAM. , The capacity of the RAM for storing the display code can be saved, and continuous display can be performed with a small RAM capacity.

According to a second aspect of the present invention, there is provided a display control apparatus.
In the display control device described above, the control bits for continuous display include a bit indicating the number of times the selector selects the buffer memory. This gives R
If one display code corresponding to the display data to be displayed is stored in the AM, the display can be performed any number of times continuously.

According to a third aspect of the present invention, there is provided a display control apparatus.
Or the display control device according to item 2, further comprising a color conversion unit that converts display data output from the selector into RGB display data. Thus, color display can be performed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a display control device according to an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a display control device according to an embodiment of the present invention;
2 is a CPU, 103 is a RAM for storing a display code, 1
04 is a ROM address generation unit (display data memory address generation unit), 105 is a ROM which is a display data memory,
Reference numeral 106 denotes a color conversion unit, 107 denotes a display device, 111 denotes a buffer memory, and 112 denotes a selector for selecting display data from the ROM 105 and the buffer memory 111.

In the present embodiment shown in FIG. 1, in addition to the configuration of the conventional example shown in FIG. 3, a buffer memory 111 for storing display data output from a ROM 105, and display data for one of the ROM 105 and the buffer memory 111, A selector 112 is provided for selecting the same, so that the same display code is continuously stored in the RAM 103 instead of continuously storing the same display code in the RAM 103 in order to continuously output the same RGB display data to the display device 107. A display code including a control bit (continuous display control bit, continuous count bit) is stored. Then, when the display code b is decoded by the ROM address generation unit 104, the selector 112 continuously selects and outputs the display data of the buffer memory 111 by the number of times indicated by the consecutive number of bits.

The operation of the display control device of the present embodiment configured as described above will be described below. In addition,
Here, “AAA” shown on the display device 107 in FIG.
The display of a character string "B" will be described as an example.
, Display codes a, b, and c are stored in advance in the order of display by the CPU 102 as an example. The display codes a and c include a display end bit indicating whether to end the display by “1” and “0”, and “1” and “0” to indicate whether to display the same display data continuously. And a display basic bit as an original display code for generating a ROM address for accessing the ROM 105 storing display data. Also,
The display code b includes a display end bit, a continuous display control bit, and a continuous count bit for displaying the same display data continuously.

First, the RAM output from the CPU 102
The display code a is read from the RAM 103 according to the address, and is input to the ROM address generation unit 104. R
The OM address generation unit 104 decodes the display code a, and generates and outputs a ROM address for accessing the ROM 105 from the display basic bit portion. Further, since the continuous display control bit of the display code a is “0”, the selector 112 is in a state of selecting display data of the RAM 105. ROM 105 according to ROM address
Are output to the color conversion unit 106 via the selector 112, and are also input and stored in the buffer memory 111. The color converter 106 converts the display data input from the selector 112 into RGB display data that can be displayed on the display device 107 and outputs the data to the display device 107. Thereby, the display device 107
Then, the first "A" at the left end is displayed.

Next, the RA output from CPU 102
The display code b is read from the RAM 103 based on the M address, and is input to the ROM address generation unit 104.
In the display code b, it is assumed that the continuous display control bit is “1” indicating continuous display, and the content of the continuous count bit is “2”. This display code b is stored in the ROM address generator 104
Of the buffer memory 111
Is transmitted to the selector 112 to select the data in succession twice. This control signal causes the selector 11
2 switches its output to an input from the buffer memory 111, and outputs “A” stored in the buffer memory 111.
Is output to the color conversion unit 106 twice consecutively, and is converted into RGB display data. As a result, the display device 107 displays the second and third “A” from the left end. As described above, in order to display “A” three times in succession, the content of the continuous number bit of the display code b is determined by the number of times the selector 112 selects display data in the buffer memory 111 (that is, the number of consecutive The number of display times-1) is "2".

Next, the RA output from the CPU 102
The display code c is read from the RAM 103 based on the M address, and is input to the ROM address generation unit 104.
The ROM address generation unit 104 decodes the display code c, generates and outputs a ROM address for accessing the ROM 105 from the display basic bit portion, and the display end bit is “1” indicating the end of the display. Therefore, the CPU 102 is notified to that effect. By the ROM address output from the ROM address generation unit 104, R
The display data of “B” is output from the OM 105, input to the color conversion unit 106 via the selector 112, and input to and stored in the buffer memory 111. The color converter 106 converts the display data input from the selector 112 into RGB display data that can be displayed on the display device 107 and outputs the data to the display device 107. As a result, the display device 107 displays the fourth (right end) “B” from the left end. Then, as described above, since the display end notification is sent from the decoder of the ROM address generation unit 104 to the CPU 102, the display is completed.

As described above, according to the embodiment of the present invention, the buffer memory 111 for storing the display data output from the ROM 105 and the selector 1 for selecting one of the display data of the ROM 105 and the buffer memory 111
12 is provided, and the display code b including the continuous display control bit and the continuous count bit is stored in the RAM 103, so that the continuous display can be performed only by storing one display code a in the RAM 103. The capacity of the RAM 103 to be stored can be saved, and a small RA
Continuous display is possible with M capacity.

In the embodiment of the present invention, R
The display code b for controlling the continuous display is stored in the AM 103 following the display code a corresponding to the display data to be continuously displayed, but the continuous display control bit of the display code b is stored in the display code a to be continuously displayed. Needless to say, it is also possible to include the bit and the number of consecutive times.

In this embodiment, the ROM 105 is used as the display data memory. However, it goes without saying that a RAM may be used. Further, by providing the color conversion unit 106, color display can be performed by the display device 107. However, in the case of monochrome display, the color conversion unit 106 is not necessary.

[0021]

As described above, according to the present invention, instead of storing the same display code continuously in the RAM so as to continuously output the same display data from the selector, the control bit for continuous display is used. The display data memory address generation unit issues a continuous display control signal to the selector when decoding the display code including the control bit for continuous display, and the selector uses the continuous display control signal to decode the display code. When the same display data is displayed continuously by selecting the display data stored in the buffer memory, one display code corresponding to the display data to be displayed and one display code are displayed continuously in the RAM. Since it is only necessary to store the display code including the control bit of, the capacity of the RAM for storing the display code can be saved, Continuous display with no RAM capacity is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a display control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional display control device.

[Explanation of symbols]

Reference Signs List 101 display control device 102 CPU 103 RAM 104 ROM address generation unit (display data memory address generation unit) 105 ROM (display data memory) 106 color conversion unit 107 display device 111 buffer memory 112 selector

Claims (3)

[Claims] 1. A CPU, a RAM that outputs a display code stored in advance by an address output from the CPU, and a display data memory that decodes a display code output from the RAM to generate a display data memory address. An address generator, a display data memory for outputting display data stored in advance by a display data memory address output from the display data memory address generator, and a buffer for storing display data output from the display data memory A memory, and a selector that selects and outputs one of display data output from the display data memory and display data stored in the buffer memory, and stores the same display data from the selector in the RAM. Use the same display button to output continuously. Instead of storing the codes continuously, a display code including a control bit for continuous display is stored, and the display data memory address generation unit decodes the display code including the control bits for the continuous display. When the continuous display control signal is issued to the selector, the selector selects and outputs the display data stored in the buffer memory when the continuous display control signal is input, and the continuous display control signal is input. A display control device for selecting and outputting display data output from the display data memory when not performed. 2. The display control device according to claim 1, wherein the control bits for continuous display include a bit indicating the number of times the selector selects the buffer memory. 3. The display data output from the selector is R
3. The display control device according to claim 1, further comprising a color conversion unit that converts the display data into GB display data.