JPH10312364A - Information processor and exclusive control flag management system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily reset the state of exclusive control over a common resource by clearing an exclusive control flag set by a processor which is disable to access the exclusive control flag. SOLUTION: If trouble occurs to some node, all processors included in this node are disable to access the exclusive control flag 1. At this time, a converting means 11 refers to a node-processor correspondence table 10 with the node ID of the node where the trouble has occurred and takes the processor IDs of the processors included in the node out in order. A discriminating means 12 compares the processor IDs taken out by the converting means 11 with the ID2 of a processor in exclusive control to know whether or not they match each other. A clearing means 13 clears the exclusive control flag 1 corresponding to the processor ID2 of the processor in exclusive control when the match between the processor IDs is discriminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exclusive control flag management method in an information processing apparatus and an information processing apparatus, and more particularly to an information processing apparatus having a cluster configuration in which nodes including a plurality of processors are connected by an inter-node connecting device. The present invention relates to an exclusive control flag management method including a method for clearing an exclusive control flag when a failure occurs during processing, and an information processing apparatus.

[0002]

2. Description of the Related Art In recent years, an information processing apparatus having a multiprocessor configuration including a plurality of processors has been developed in order to respond to a demand for higher speed in the information processing apparatus. Further, in order to respond to the demand for higher speed, an information processing apparatus has been developed which has a cluster configuration in which a configuration unit called a node in which a plurality of processors are bundled is further connected by an inter-node connection device.

[0003] When accessing a shared resource among a plurality of processors, a method of performing exclusive control between processors using an exclusive control flag is well known.

The exclusive control using the exclusive control flag is performed as follows.

[0005] In a shared memory system in which a plurality of processors are connected, an exclusive flag is set so that one processor does not work on the shared memory while one processor is writing or reading the shared memory, and the work is prohibited. Here, an exclusive control flag corresponding to a shared resource that is a shared memory is provided. A processor that intends to obtain an access right to a shared resource performs a set process on an exclusive control flag. At this time, if the exclusive control flag has not been set, the set processing by the processor is successful, and the processor can obtain the access right to the shared resource. If the exclusive control flag has already been set by another processor, the set process fails, and the processor cannot gain access to the shared resource.

When the exclusive control flag is used, when a certain processor sets the exclusive flag and a failure occurs in the processor, the exclusive control flag cannot be reset and the exclusive state of the shared resource is not released. The problem exists.

As a conventional technique for solving this problem, for example, a technique of monitoring an exclusive control flag using a watchdog timer or a technique described in Japanese Patent Application Laid-Open No. 05-158781 as an "exclusive flag management apparatus in a shared memory system". There were technologies that could be used.

The exclusion flag management device using a watchdog timer monitors the time during which the exclusion flag is set by the watchdog timer, and if the exclusion flag is set for more than a predetermined time, the exclusion flag is forcibly set. To reset the exclusive flag.

The "exclusive flag management device in the shared memory system" of Japanese Patent Application Laid-Open No. 05-158781 constitutes the following exclusive control flag management device. An exclusive flag management device that manages setting and resetting of an exclusive flag provided on a shared memory device shared by a plurality of computers; and a recording unit that records the exclusive control flag and a processor ID that sets the exclusive control flag. ,
When a failure occurs in any of the processors, a matching unit that matches the processor ID with the processor ID recorded in the recording unit; and when the two matching processor IDs match as a result of the matching, the exclusive flag is set. And a clearing means for forcing clearing. With these means, when a failure occurs in a processor, the exclusive control flag set by the processor is cleared.

[0010]

The problem to be solved by the present invention is as follows.

First, in the prior art, when exclusive control is performed on a shared resource among a plurality of processors using an exclusive flag, when a failure occurs while a certain processor sets the exclusive flag, exclusive control is performed. There is a problem that the exclusive control state for the shared resource is not released because the flag cannot be reset.

Second, in the method of monitoring the exclusive control flag by the watchdog timer, the exclusive control flag can be reset only after a monitoring time longer than the maximum time that the exclusive control flag can be set continuously. There was a problem.

Third, in the technique described in "Exclusive flag management device in shared memory system" in Japanese Patent Laid-Open No. 05-158731, a failure has occurred in a processor in order to avoid the first problem. This is effective in the case where the information processing apparatus having the cluster configuration cannot handle the case where the node including the processor under the exclusive control cannot access the exclusive control flag due to the failure in the node unit. There was a problem. Also, in an information processing apparatus having a cluster configuration, an access path is disconnected due to a failure in an inter-node connecting device that connects nodes, and it is not possible to access an exclusive control flag from a plurality of nodes including a processor under exclusive control. However, there was a problem that it was not possible to respond to the case.

[Object of the Invention] An object of the present invention is to provide an information processing apparatus having a cluster configuration in a case where exclusive control of a shared resource is performed among a plurality of processors using an exclusive control flag. In addition to the case where a failure occurs, access to the exclusive control flag from the node including the processor under exclusive control due to the failure becomes impossible, and the failure of the access path connecting the nodes Even if access to the exclusive control flag from multiple nodes including the processor becomes impossible, the exclusive control flag set by the processor that cannot access the exclusive control flag is cleared to enable sharing. To be able to immediately release the exclusive control status for resources A.

[0015]

The present invention will be described with reference to the drawings as follows for the above object.

The exclusive control flag management method of the present invention is shown in FIG.
, An exclusive control flag 1, an exclusive control processor ID2 indicating the processor ID of the processor that has set the exclusive control flag 1, and a node ID assigned to the node.
Node-processor correspondence table 10 describing the correspondence between the ID and the processor ID of the processor included in the node
A conversion means 11 for converting a node ID to a processor ID by referring to the node-processor correspondence table 10 when a failure occurs in a node; a processor ID output from the conversion means 11;
Identification means 1 for comparing with D2 to determine whether they match
2 and a clearing unit 13 for clearing the exclusive control flag 1 when the matching of the processor ID is identified by the identifying unit 12.

Referring to FIG. 2, the exclusive control flag management method of the present invention refers to an exclusive control flag 1, an exclusive-controlling processor ID2 indicating the processor ID of the processor that has set the exclusive control flag 1, and a node. An access path ID assigned to an access path between the inter-node connection devices and between the inter-node connection device and the inter-node connection device; and a processor ID of a processor that accesses the exclusive control flag via the access path. The access path-processor correspondence table 20 describing the correspondence of the access path and the access path-processor correspondence table 20 when a failure occurs in the access path.
To a processor ID, an identification unit 12 for comparing the processor ID output from the conversion unit 11 with the processor ID2 under exclusive control, and identifying whether or not they match each other. Clearing means 13 for clearing the exclusive control flag 1 when a match between the processor IDs is identified.

Further, referring to FIG. 3, the exclusive control flag management method of the present invention can identify the processor ID, the node ID field 30 storing the node ID of the node including the processor, and the processor in the node. The exclusive control flag 1, the exclusive control processor ID 2 indicating the processor ID of the processor that has set the exclusive control flag 1, the node ID when the node has failed, and the exclusive ID The node ID field of the processor ID 2 being controlled is compared with the node ID field, and a node identification means 32 for identifying whether or not the processor ID 2 is coincident with the node ID field. Clearing means 13 for performing the operation.

Referring to FIG. 4, the exclusive control flag management method according to the present invention is capable of identifying a processor ID, a node ID field 30 for storing a node ID of a node including a processor, and a processor in the node. , An exclusive control flag 1, an exclusive control processor ID 2 indicating the processor ID of the processor that has set the exclusive control flag 1, a node-to-node connection device, and an inter-node connection device. An access path that describes an association between an access path ID assigned to an access path between inter-node connecting devices and a node ID of a node that accesses the exclusive control flag via the access path; 40,
When a failure occurs in the access route, the access route-node correspondence table 40 is referred to, and the access route ID is referred to.
To a node ID, a node ID output from the conversion unit 11, and a processor I under exclusive control.
A node identification unit 32 that compares the node ID field of D2 with the node ID to determine whether they match, and a clearing unit that clears the exclusive control flag 1 if the node identification unit 32 identifies a match of the processor ID. 13.

Further, in an information processing apparatus having a cluster configuration including a node including a plurality of processors and an inter-node connecting device for connecting the plurality of nodes, the processor ID, an exclusive control flag corresponding to the processor ID, Referring to a node-processor correspondence table in which the node ID of the node and the processor ID are paired,
Conversion means for converting D into the processor ID, identification means for comparing the processor ID output from the conversion means with the processor ID under exclusive control, and identification of the processor ID by the identification means. Clearing means for clearing an exclusive control flag, wherein when a failure occurs in the processor, the set exclusive control flags of all processors included in the node are cleared. .

[Operation] The present invention according to the above-mentioned invention-specifying matter has the following operation.

Referring to FIG. 1, when the exclusive control flag 1 is set in the shared memory of the shared resource by the processor, the processor ID of the processor that has been set at the same time is recorded as the processor ID 2 under exclusive control.

When a failure occurs in a certain node, it becomes impossible for all processors included in the node to access the exclusive control flag 1. At this time, the conversion means 11
Is determined by the node ID of the failed node.
Referring to the processor correspondence table 10, the processor IDs of the processors included in the node are sequentially extracted.

The identification means 12 stores the processor ID extracted by the conversion means 11 and the processor ID under exclusive control.
2 is compared, and whether or not they match is identified.

The clearing means 13 clears the exclusive control flag 1 corresponding to the processor ID 2 under exclusive control when the identification means 12 identifies the coincidence of the processor IDs.

Next, referring to FIG. 2, when the exclusive control flag 1 is set by the processor, the processor ID of the processor that set the processor at the same time is recorded as the exclusive control processor ID2.

When a failure occurs in a certain access path between the node-to-node connection device or between the node-to-node connection device, all access to the exclusive control flag 1 via the access path is performed. Access from other processors becomes impossible. At this time, the conversion means 11
Refers to the access path-processor correspondence table 20 based on the access path ID of the failed access path, and sequentially extracts the processor IDs of the processors that access the exclusive control flag via the access path.

The identification means 12 is provided with a processor ID extracted by the conversion means 11 and an exclusive control processor ID.
2 is compared, and whether or not they match is identified.

The clearing means 13 clears the exclusive control flag 1 corresponding to the processor ID2 under exclusive control when the identification means 12 identifies the coincidence of the processor IDs.

Further, referring to FIG. 3, by forming the processor ID from the node ID field 30 and the in-node identification field, the node ID in the processor ID
By referring to the D field 30, a node including a processor having the processor ID can be specified.

When the exclusive control flag 1 is set by the processor, the processor ID of the processor that set the exclusive control flag at the same time is recorded as the exclusive control processor ID 2.

Here, when a failure occurs in a certain node, it becomes impossible to access the exclusive control flag 1 from all processors included in the node. At this time, the node identification means 32 outputs the node ID of the failed node.
Is compared with the node ID field 30 of the processor ID2 under exclusive control to determine whether they match.

The clearing means 13 clears the exclusive control flag 1 corresponding to the processor ID 2 under exclusive control when the node identification means 32 identifies the coincidence of the node IDs.

Referring to FIG. 4, exclusive control flag 1
In addition, by configuring the processor ID2 under exclusive control from the node ID field 30 and the in-node identification field 31, the node including the processor having the processor ID2 is specified by referring to the node ID field 30 in the processor ID2. It is possible to do.

When the exclusive control flag 1 is set by the processor, the processor ID of the processor that set the exclusive control flag at the same time is recorded as the processor ID 2 under exclusive control.

When a failure occurs in a certain access path between the node-to-node connection device or between the node-to-node connection device, all access to the exclusive control flag 1 via the access path is performed. Access from this node becomes impossible. At this time, the conversion unit 11 refers to the access route-node correspondence table 40 based on the access route ID of the failed access route, and sequentially determines the node IDs of the nodes that access the exclusive control flag via the access route. Take out.

The node identification means 32 compares the node ID extracted by the conversion means 11 with the node ID field 30 of the processor ID2 under exclusive control, and identifies whether they match.

The clearing means 13 clears the exclusive control flag 1 corresponding to the processor ID 2 under exclusive control when the node identification means 32 identifies the coincidence of the node IDs.

In an information processing apparatus having a large-scale cluster configuration, a processor ID of a processor and an exclusive control flag corresponding to the processor ID are set in order to clear an exclusive control flag by one of the processors due to a failure. The exclusive control flag of the processor in which the failure has occurred is cleared from the storage means paired with the above. That is, by referring to the node-processor correspondence table in which the node ID of the node and the processor ID are paired, the node of the failed processor is detected, and the processor ID is compared with the processor ID under exclusive control. Identifying the processor I
If a match of D is identified, the exclusive control flag is cleared.

[0040]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 5 shows the entire configuration of an information processing apparatus having a cluster configuration according to the first embodiment. The plurality of processors 50 are connected to the inter-processor connection network 5.
1 interconnected. This structural unit is called node 5
2, a plurality of nodes 52 are further connected by an inter-node connecting device 53, whereby a large-scale multiprocessor system with a cluster configuration is realized.

All nodes 5 on the inter-node connecting device 53
The exclusive control flag 1 in the shared memory 3, which is a shared resource, is mounted at a position accessible from the server 2. In addition, when a failure occurs in any of the processors 10... 1n in a certain node, the failure is detected by the inter-processor connection network 51 and notified to the inter-node connection device 53 through an access path. Is notified of the failure.

FIG. 1 shows an example of the configuration of the exclusive control flag management method in this embodiment. In the present embodiment, the memory 3 that realizes the exclusive control flag 1 and the processor ID 2 under the exclusive control, the exclusive control flag access control circuit 5 that controls the exclusive control access request from the processors 10.
And a bus 4 connecting them. Here, the value of the exclusive control flag 1 of the processor ID2 under exclusive control is "1".
Is the processor ID under exclusive control, but when the value of the exclusive control flag 1 is "0", it indicates a simple processor ID.

Further, it includes a fault processing control circuit 6 for receiving fault information and a memory access circuit 7 for accessing the exclusive control flag 1 having a plurality of words on the memory 3. Further, a node-processor correspondence table 10, a conversion unit 11, and an identification unit 1 which are features of the present embodiment.
2 and clearing means 13.

FIG. 7 shows a node-processor correspondence table 1.
0, a block diagram of a configuration example of the conversion means 11 is shown.

The node-processor correspondence table 10
It comprises a memory A70 and a memory B71. The memory A 70 is addressed by the node ID and stores a memory B start address corresponding to each node.
The memory B 71 has an end bit 72 and a processor ID 73
The processor ID 73 corresponding to each node is stored in the area from the address specified by the memory B start address on the memory A 70 to the address where the end bit 72 is set to “1”. I do.

The conversion means 11 includes a control circuit 74, a reference key register 75, a counter 76, and a reference result register 7.
7 is comprised. When referencing by node ID,
The node ID is stored in the reference key register 75, and the memory A70 of the node-processor correspondence table 10 is accessed. The read memory B start address is stored in the counter 76, the memory B is accessed, and the end bit 72 and the processor ID 73 are read. The read processor ID 73 is stored in the reference result register 77 and output to the identification unit 12. At this time, if the end bit 72 is "1", it is determined that the current address is the last position of the area corresponding to the node. If the end bit 72 is not "1", it is determined that the area is continued, and the counter 76 is incremented by an instruction from the control circuit 74. In FIG. 7, +1
The operation of the control circuit 74 is shown in FIG.

FIG. 8 is a block diagram showing a configuration example of the identification means 12 and the clear means 13 for resetting.

The identification means 12 comprises a comparison register A 80, a comparison register B 81, an address holding register 82, and a comparator 83. The comparison register A80 is a conversion unit 1
1 output from the reference result register 77
D73 is stored. The comparison register B81 stores the exclusive control processor ID2 read from the memory 3 by the memory access circuit 7. Address holding register 8
2 is the processor ID under exclusive control in the comparison register B81.
2 holds the address in the memory 3. The comparator 83 compares the values of the comparison register A80 and the comparison register B81, and if the result of the comparison is a match, the exclusive control flag 1 is identified as unclearable.

The clear means 13 includes a write control circuit 84
And an address register 85. The write control circuit 84 sends an address register 85 to the memory 3.
Is written as an address and "0" is written as write data.

Next, the operation of the present invention in this embodiment will be described.

When a failure occurs in a certain node among the plurality of nodes 52, node failure information is notified to the failure processing control circuit 6 in the inter-node connecting device 53 via an access path. The failure processing is started by the failure processing control circuit 6, and the node ID of the failed node is output to the conversion means 11. Further, the memory access circuit 7 is activated, and the processor ID2 under exclusive control is sequentially read from all the addresses of the memory 3.

The fault processing control circuit 6 is converted by the conversion means 11.
The node-processor ID table 10 is referred to using the node ID output from the node as a reference key, the processor ID of the processor under the node is read, and the processor which has become inaccessible to the identification means 12 due to a failure is identified. Is output as the processor ID.

The identification means 12 compares the processor ID output from the conversion means 11 with the processor ID2 under exclusive control output from the memory access circuit 7, and if the comparison result indicates a match, clears. Mean 13
Is instructed to clear the exclusive control flag for the address.

The clearing means 13 writes "0" into the exclusive control flag 1 of the address to clear the address.

If the identification of all of the processor IDs 2 under exclusive control is completed for a certain processor ID, and if the processor ID is the last processor ID included in the failed node, the failure processing ends. . on the other hand,
If the faulty processor ID is not the last processor ID, the replacement unit 11 takes out the next processor ID, and again executes the memory access circuit 7.
Is started, and the process is continued.

According to the above series of operations, when a failure occurs in a certain node, a clearing process for the exclusive control flag 1 set by all the processors included in the node is realized.

[Second Embodiment] FIG. 6 shows the overall configuration of an information processing apparatus having a cluster configuration according to the second embodiment.

Overall Configuration in First Embodiment (FIG. 5)
In the present embodiment, the nodes are connected by a plurality of inter-node connecting devices 53, whereas the number of inter-node connecting devices 53 is one. As a result, an access path A60 between the internode connection device 53 and the internode connection device 53 exists as an access route in addition to the access path 54 between the node and the node connection device. FIG. 6 shows one example of the access route A60, but it is assumed that there is a plurality of access routes. When a failure occurs in such an access path A60 between the inter-node connecting devices, the processors included in the plurality of nodes 52 cannot access the exclusive control flag 1. In the example of FIG. 6, when a failure occurs in the access route 60, access to the exclusive control flag 1 from the nodes 3, 4, and 5 becomes impossible. When a failure occurs in each of the access paths 3 to 5 connected to the nodes 3, 4, and 5, the operation described in the first embodiment is performed.

FIG. 2 shows an example of the configuration of the exclusive control flag management method according to the second embodiment.

In order to cope with a failure in the access path 60, the second embodiment includes an access path-processor correspondence table 20 instead of the node-processor correspondence table 10 of the first embodiment. Other configurations are the same as those of the first embodiment.

Access path-processor correspondence table 2
0 is given to the access path while the node-processor correspondence table 10 of the first embodiment describes the correspondence between the node ID and the processor ID of the processor included in the node corresponding to the node ID. The correspondence between the given access path ID and the processor ID of the processor that accesses the exclusive control flag via the access path is described.

Next, the operation of the present invention in the second embodiment will be described.

When a failure occurs in the access route 60,
The conversion unit 11 refers to the access path-processor correspondence table 20 using the access path ID received from the failure processing control circuit 6 as a reference key, and accesses the exclusive control flag 1 via the access path. Is read and output to the identification means 12. The memory access circuit 7 reads the operating processor in the exclusive control flag 1 in the memory 3 from the processor under exclusive control ID2 and compares it with the processor read from the faulty access path fault information read by the identification means 12. Then, if they match, the clearing unit 13 changes “1” of the exclusive control flag 1 to “0”.
Convert to and clear.

The other operation is the same as the operation described in the first embodiment.

[Third Embodiment] The third embodiment is implemented in the same information processing apparatus (FIG. 5) as the information processing apparatus implemented in the first embodiment.

FIG. 3 shows a configuration example of an exclusive control flag management method according to the third embodiment. In the present embodiment,
The processor ID that is the processor ID2 under exclusive control corresponding to the exclusive control flag 1 in the memory 3 is defined as a bit string having two fields. Processor ID
Is composed of a node ID field 30 capable of identifying a node including the processor, and an intra-node identification field 31 capable of identifying the processor among processors included in the node. If the processor ID has this structure, the processor ID
By referring to the inside node ID field, the node ID of the node including the processor having the processor ID can be obtained.

While the first embodiment has the node-processor correspondence table 10, the conversion means 11, and the identification means 12 shown in FIG. 7, in the third embodiment, the node-processor correspondence table 10 Node ID
Is stored together with the processor ID, and the node ID and the processor ID are stored in the reference key register 75 in the conversion means 11.
Are input, and the node ID in which the failure has occurred in the node identification means 32 and the processor ID under exclusive control from the memory access circuit 7 are input.

FIG. 9 shows a configuration example of the node identification means 32. The node identification means 32 includes a comparison register A90, a comparison register B91, an address holding register 92, a comparator 9
3 The comparison register A90 stores the node ID. The comparison register B91 is a memory access circuit 7
The exclusive control processor ID2 output from the
Only the node ID field 30 is output to the clear unit 13. The address holding register 92 holds the address in the memory 3 of the processor under exclusive control ID2 in the comparison register B91 output from the memory access circuit 7. The comparator 93 includes a comparison register A91 and a comparison register B92.
Are compared with each other in the node ID field.

Next, the operation of the present invention in the third embodiment will be described. When a failure occurs in the node, the node ID output by the failure processing control circuit 6 and the node identification field 30 of the exclusive control processor ID 2 output from the memory access circuit 7 are output by the node identification means 32.
Is compared, and if the comparison result in the node identification field 30 indicates a match, the clear means 13 sends an exclusive control flag 1 indicating the paired relationship between the node ID field 30 and the intra-node identification field 31 for the address. "
The clear is instructed to the memory 30 so as to switch from “1” to “0”.

The other operations are the same as in the first embodiment.

[Fourth Embodiment] In a fourth embodiment, the same information processing apparatus (FIG. 6) as the information processing apparatus according to the second embodiment is provided, that is, a plurality of inter-node connection devices are provided. This is performed by an information processing apparatus having a cluster configuration.

FIG. 4 shows a configuration example of an exclusive control flag management method according to the fourth embodiment. This embodiment is different from the first embodiment in that the node-processor correspondence table 10
Is replaced with the access route-node correspondence table 40,
Further, a configuration is adopted in which the identification means 12 is replaced with the node identification means 32 in the third embodiment.

Access route-node correspondence table 40
In the information processing apparatus having a large-scale cluster configuration as shown in FIG. 6, a correspondence between an access path and a node that cannot access the exclusive control flag when a failure occurs in the access path is described. You. In the example of FIG. 6, the nodes to be connected to each other are described for the access path 54 between the node-to-node connecting device, and the access path 60 between the node-to-node connecting device-to-node connecting device
, Three nodes of node 3, node 4, and node 5 are described.

Next, the operation of the present invention in the fourth embodiment will be described. When a failure occurs in the access path, the conversion means 11 refers to the access path-node correspondence table 40 using the access path ID received from the failure processing control circuit 6 as a reference key, and passes through the access path ID. The node ID of the node that accesses the exclusive control flag is read out by the
Is output to

As in the case of the third embodiment, the node ID output from the conversion means 11 and the node ID field 30 of the exclusive-controlling processor ID 2 output from the memory access circuit 7 are output by the node identification means 32. Is performed, and if the comparison result in the node identification field 30 is a match, the clearing unit 13 is instructed to clear the exclusive control flag 1 for the node identification field 30 of the address.

Other operations are the same as those of the first embodiment.

[Fifth Embodiment] FIG. 10 shows the configuration of a fifth embodiment. Unlike the above embodiments, the node 1
00 has a plurality of nodes 100 to 10n each including a processor 110 and a memory 114, and an inter-node connection device 120 for connecting the nodes.
The information processing apparatus having the memory resource management means 112 above has a configuration in which a shared register 123 accessible from the processor 110 on each node is provided on the inter-node connection device 120. In such an information processing apparatus, the memory resource management unit 11 of each of the nodes 100 to 10n
2 can perform the process of securing / releasing the memory resource 114 across the nodes using the shared register 123.

However, when the memory resource management means 114 of one of the nodes 100 to 10n secures the memory resource 114 on the shared register 123, a connection failure occurs between the node-to-node connection device 120 and the system When the node is disconnected from the node, the secured information on the shared register 123 cannot be reset, and the resource resources of the memory 114 secured by the connection failure node cannot be reused.

The inter-node connection device 120 in the information processing device
Connection failure detecting means 121 and failure information notifying means 122
The fault information relay means 131 is provided in the diagnostic processor 130 connected by the bus, the fault information receiving means 111 is provided on the processor of each node, and the fault node resource releasing means 113 is provided in the memory resource management means 112. When a connection failure occurs, the memory resource management unit 112 on a node other than the connection failure node is notified of the invalidation of the shared register 123, and the memory resource secured in the node having the connection failure is released. To make things possible.

A plurality of nodes 100 to 10 n on which the processor 110 and the memory 114 are mounted, an inter-node connecting device 120 connecting between the nodes, and a diagnostic processing device 13 connecting to the nodes 100 to 10 n and the inter-node connecting device 120
0, and a memory resource management unit 112 on the processor 110, and a shared register 123 accessible from the processor 110 on each node on the internode connecting device 120,
0-10n, the fault information notifying means 122, the fault information relay means 131 on the diagnostic processing device 130, and the fault information receiving means 1 on the processor 110.
11 has a failed node resource release unit 113 in the memory resource management unit 112.

When a connection failure occurs between a certain node-node connection device constituting the information processing device, the node is disconnected from the system. After this, the shared register 123 in the node-to-node connection device 120 changes from the connection failure node.
Becomes inaccessible, and normal memory resource management becomes impossible.

At the time of disconnection of the connection failure node, the connection failure node detects a connection failure by the connection failure detecting means 121, and the diagnostic processing unit 13 by the failure information notifying means 122.
0 is notified of failure information. The diagnostic processing device 130 notifies the failure information relay unit 131 of failure information to each node other than the connection failure node.

Processor 11 of each of nodes 100 to 10n
When the fault information receiving means 111 receives the fault information, it notifies the memory resource managing means 112 of the occurrence of the connection fault.

The memory resource management means 112 determines that the normal memory resource management cannot be executed by being notified of the occurrence of the connection failure, and the memory resource secured by the failed connection node by the failed node resource release means 113. To release. At the same time, the information on the shared register 123 is determined to be invalid.

By the above operation, the memory resources secured by the nodes 100 to 10n in which the connection failure has occurred can be reused.

In this embodiment, the configuration of the nodes 100 to 10n is different from those of the first to fourth embodiments, and the inter-node connecting device 120, the diagnostic processing device 130, and the memory 114 usable from each node are connected to each other. Of course, even when included in the connection device 63, the same operation as in the present embodiment is performed.

[0088]

As described above, according to the present invention,
Information processing apparatus having a cluster configuration including a node composed of a plurality of processors and an inter-node connection device connecting the plurality of nodes, or information on a cluster configuration connecting a plurality of nodes through a plurality of inter-node connection devices In the processing device, when access to the exclusive control flag from the node including the processor under exclusive control becomes impossible due to a failure, the exclusive control flag set by the processor that cannot access the exclusive control flag. , The exclusive control state for the shared resource can be released.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of an embodiment according to the present invention.

FIG. 2 is a schematic block diagram of an embodiment according to the present invention.

FIG. 3 is a schematic block diagram of an embodiment according to the present invention.

FIG. 4 is a schematic block diagram of an embodiment according to the present invention.

FIG. 5 is a schematic block diagram of an information processing apparatus having a cluster configuration according to an embodiment of the present invention.

FIG. 6 is a schematic block diagram of an information processing apparatus having a cluster configuration according to an embodiment of the present invention.

FIG. 7 is a schematic block diagram of a node-processor correspondence table and a conversion unit of the embodiment according to the present invention.

FIG. 8 is a schematic block diagram of an identification unit and a clear unit of the embodiment according to the present invention.

FIG. 9 is a schematic block diagram of an identification unit of an embodiment according to the present invention.

FIG. 10 is a schematic block diagram of an embodiment according to the present invention.

[Description of Signs] 1 Exclusive control flag 2 Processor ID under exclusive control 3 Memory 4 Bus 5 Exclusive control access control circuit 6 Fault processing control circuit 7 Memory access circuit 10 Node-processor correspondence table 11 Conversion means 12 Identification means 13 Clear means 20 Access route-processor correspondence table 30 Node ID field 31 Intra-node identification field 32 Node identification means 40 Access route-node correspondence table 90, 91 Comparison register 123 Shared register 130 Diagnostic processing device

Claims (6)

[Claims] 1. An information processing apparatus having a cluster configuration including a node including a plurality of processors and an inter-node connecting device for connecting the plurality of nodes, wherein the processor ID, an exclusive control flag corresponding to the processor ID, A conversion unit for converting the node ID into the processor ID by referring to a node-processor correspondence table in which the node ID of the node and the processor ID are paired, and a processor under exclusive control of the processor ID output by the conversion unit ID means for comparing the ID with an ID, and clearing means for clearing an exclusive control flag if a match of the processor ID is identified by the identifying means. Clearing the set exclusive control flags of all the processors included in the node. The information processing apparatus according to claim. 2. An information processing apparatus having a cluster configuration including a node including a plurality of processors and an inter-node connecting device connecting the plurality of nodes, wherein the processor ID, an exclusive control flag corresponding to the processor ID, A conversion unit for converting the node ID into the processor ID by referring to a node-processor correspondence table in which the node ID of the node and the processor ID are paired, and a processor under exclusive control of the processor ID output by the conversion unit ID means for comparing the IDs with each other, and clearing means for clearing an exclusive control flag if a match of the processor ID is identified by the identifying means. Clearing the set exclusive control flags of all the processors included in the node. Information processing apparatus according to symptoms. 3. A cluster comprising a node composed of a plurality of processors and an inter-node connecting device connecting the plurality of nodes, wherein an exclusive control flag is provided on the inter-node connecting device to perform exclusive control between the processors. In the exclusive control flag management method of the information processing apparatus having the configuration, a storage means for storing an exclusive control processor ID indicating a processor ID of a processor which sets the exclusive control flag paired with the exclusive control flag; Storage means for storing a node-processor correspondence table describing a correspondence between a node ID and a processor ID of the processor included in the node; and, when a failure occurs in the node, referencing the node-processor correspondence table. Conversion means for converting the node ID into the processor ID; An identification means for comparing the processor ID output from the stage with the processor ID under exclusive control and identifying whether or not the processor ID is identical; and Clearing means for clearing a flag, and when a failure occurs in the node,
An exclusive control flag management method that enables the exclusive control flags set by all the processors included in the node to be cleared. 4. A node comprising a plurality of processors and a plurality of nodes are connected by a plurality of inter-node connecting devices, an exclusive control flag is provided on one of the inter-node connecting devices, and In an exclusive control flag management method for an information processing apparatus having a cluster configuration that performs exclusive control, the exclusive control flag, an exclusive control processor ID indicating a processor ID of a processor that has set the exclusive control flag, and the node with the node Path IDs assigned to access paths between the interconnecting devices and between the inter-node connecting device and the inter-node connecting device, and the processor of the processor that accesses the exclusive control flag via the access route An access path-processor correspondence table describing correspondence with an ID, and the access path When a failure occurs, the conversion unit refers to the access path-processor correspondence table and converts the access path ID to the processor ID. The processor ID output by the conversion unit and the exclusive control processor ID And an identification unit for identifying whether or not they match each other, and a clearing unit for clearing the exclusive control flag if the identification unit identifies the match of the processor ID, An exclusive control flag management method that enables all processors that access the exclusive control flag via the access path to clear the exclusive control flag that has been set when a failure occurs. 5. A cluster configuration comprising a node composed of a plurality of processors and an inter-node connecting device for connecting the plurality of nodes, wherein an exclusive control flag is provided on the inter-node connecting device to perform exclusive control between the processors. An exclusive control flag management method for an information processing apparatus according to claim 1, wherein a processor ID of said processor is a node ID for storing a node ID of said node including said processor.
Storage means for storing, as a pair, a field and an in-node identification field capable of identifying a processor in the node; an exclusive control processor indicating the processor ID of the processor that has set the exclusive control flag and the exclusive control flag An ID, and if the node fails, the node ID;
A node identification unit that compares the node ID field of the processor ID under the exclusive control and determines whether or not the node ID field matches the node ID field; Clearing means for clearing the exclusive control flag, wherein when a failure occurs in the node, the exclusive control flag set by all the processors included in the node can be cleared. . 6. A node comprising a plurality of processors and a plurality of nodes are connected by a plurality of inter-node connecting devices, an exclusive control flag is provided on one of the inter-node connecting devices, and an exclusive control between processors is provided. In the exclusive control flag management method for an information processing apparatus having a cluster configuration, a processor ID of the processor is set as a node ID storing a node ID of the node including the processor.
A field, a storage unit that stores the processor in the node in a node identification field capable of identifying the processor, the exclusive control flag, and an exclusive control indicating the processor ID of the processor that has set the exclusive control flag. A processor ID, an access path ID assigned to an access path between the node and the inter-node connection device, and an access path between the inter-node connection device and another inter-node connection device, and the exclusion via the access path. The access path-node correspondence table describing the correspondence between the node and the node ID of the node that accesses the control flag, and if a failure occurs in the access path, the access path-node correspondence table is referred to, and the access is performed. Conversion means for converting a path ID into the node ID, and an output from the conversion means A node identification unit that compares the node ID with the node ID field of the exclusive-controlling processor ID and determines whether or not the node ID matches each other; Clearing means for clearing the exclusive control flag, wherein when a failure occurs in the access path, the node is included in all the nodes that access the exclusive control flag via the access path. An exclusive control flag management method for an information processing apparatus that enables the exclusive control flag set by a processor to be cleared.