JPH10313103A - Semiconductor device having a capacitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a capacitor dielectric layer in high specific inductive capacity as well as small leakage current. SOLUTION: A storage node is formed on an interlayer insulating layer 27, so as to be in contact with source/drain regions 15 of a MOS transistor 20 passing through a plug layer 9. Further, a cell plate 5 is formed opposite to this storage node 1 via a capacitor dielectric layer 3. In such a constitution, the storage node 1 is made of Ru in orientation degree (002) which exceeds 95%.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a capacitor, and more particularly, to a semiconductor device having a capacitor in which a capacitor dielectric layer containing a high dielectric constant material is sandwiched between a pair of electrodes. It is.

[0002]

2. Description of the Related Art In recent years, with the remarkable spread of information devices such as computers, demand for semiconductor devices has been rapidly expanding. Functionally, it has a large storage capacity,
What can be operated at high speed is required. Along with this, technology development for high integration and high-speed response or high reliability of semiconductor devices has been promoted.

[0003] Among semiconductor devices, a DRAM (Dynamic Rand) which can randomly input and output stored information is known.
om Access Memory) is generally known. This DR
The AM includes a memory cell array, which is a storage area for storing a large amount of storage information, and peripheral circuits necessary for input / output with the outside.

[0004] The memory cell array occupies a large area on the DRAM semiconductor chip thus configured. In this memory cell array, a plurality of memory cells for storing unit storage information are arranged in a matrix. This memory cell is generally composed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto, and is widely known as a one-transistor one-capacitor type memory cell. The memory cell having such a structure has a simple structure, so that it is easy to improve the degree of integration of the memory cell array, and a large-capacity DRA
M is widely used.

When the high integration of DRAM is pushed to the Gbit class represented by 1 Gbit (gigabit), the size of the memory cell must be reduced. As the memory cell size decreases, the planar occupation area of the capacitor also decreases at the same time. As a result, the amount of charge stored in the capacitor (the amount of charge stored in a 1-bit memory cell) decreases, and the DRAM as a storage area
Operation becomes unstable, and the reliability decreases.

In order to prevent the operation of the DRAM from becoming unstable, it is necessary to increase the capacitance of the capacitor within a limited plane occupation area. As one of the means, a method of using a material called a so-called high dielectric constant material for a capacitor dielectric layer is being studied. Here, the high dielectric constant material is generally a material having a dielectric constant several times to several hundred times that of the silicon oxide film. By using this high dielectric constant material for the capacitor dielectric layer, the shape of the capacitor can be relatively reduced. It is possible to easily increase the capacity while maintaining the simple shape.

[0007] It should be noted that a material called a high dielectric constant material is used.
As an example, barium strontium titanate ((B
a, Sr) TiO_Three: BST), tantalum oxide (Ta)
_TwoO _Five), Lead zirconate titanate (Pb (Zr, Ti)
O_Three: PZT), lead lanthanum zirconate titanate ((P
b, La) (Zr, Ti) O_Three: PLZT), titanic acid
Strontium (SrTiO_Three: STO), titanium titanate
Li (BaTiO)_Three: BTO).

Hereinafter, a conventional memory cell structure using a high dielectric constant material for a capacitor dielectric layer will be described.

FIG. 7 is a sectional view schematically showing a configuration of a conventional semiconductor device. Referring to FIG. 7, on the surface of silicon substrate 11 separated by element isolation insulating layer 13,
A MOS transistor 20 is formed.

The MOS transistor 20 has a pair of source / drain regions 15, a gate insulating layer 17, and a gate electrode layer 19. A pair of source / drain regions 15 are formed on the surface of silicon substrate 11 at a distance from each other. The source / drain region 15 has an LDD (Lightly Doped Drain) structure including a low impurity concentration region 15a and a high impurity concentration region 15b. Gate electrode layer 19 is formed on a region interposed between a pair of source / drain regions 15 with gate insulating layer 17 interposed.

The periphery of the gate electrode layer 19 is covered with an insulating layer 21, and a bit line 23 is electrically connected to one of the source / drain regions 15. An insulating layer 25 is formed to cover bit line 23. Then, an interlayer insulating layer 27 is formed so as to cover the MOS transistor 20, the bit line 23, and the like. In the interlayer insulating layer 27, a contact hole 27a reaching the other of the source / drain region 15 is formed. Plug layer 9 is formed so as to fill contact hole 27a, and capacitor 110 is formed to be electrically connected to source / drain region 15 through plug layer 9.

The capacitor 110 is connected to the storage node 1
01, the capacitor dielectric layer 103, and the cell plate 1
05. Storage node 101 is formed on interlayer insulating layer 27 and is electrically connected to plug layer 9. The capacitor dielectric layer 103 is made of the above-mentioned so-called high dielectric constant material.
01 is formed. Cell plate 105
Are formed to face storage node 101 with capacitor dielectric layer 103 interposed therebetween.

An interlayer insulating layer 31 is formed so as to cover the capacitor 110. On the interlayer insulating layer 31,
A conductive layer 33 patterned into a desired shape is formed. The interlayer insulating layer 3 is formed so as to cover the conductive layer 33.
5 is formed, and a conductive layer 37 patterned in a predetermined shape is formed on the interlayer insulating layer 35.

When a high dielectric constant material is used for the capacitor dielectric layer 103, it is difficult to form an oxide in the material of the storage node 101, it is possible to maintain conductivity even if it becomes an oxide, A material that easily obtains the perovskite structure of the layer 103 is required. As a material satisfying these characteristics, Ru (ruthenium), Ir (iridium), Re (rhenium), Pt (platinum), Pd (palladium), Rh (rhodium) and the like are selected.

In this case, the storage node 101
In order to eliminate the asymmetry of the electrical characteristics between the cell plate 105 and the cell plate 105, the storage node 1
It is preferable to use the same material as 01.

In the conventional method for manufacturing a semiconductor device, when the storage node 101 and the cell plate 105 are formed of the above-mentioned materials, the substrate temperature is from room temperature to 200 ° C., the sputtering pressure is from 5 to 10 mTorr, and the sputtering gas is argon. The film is formed by sputtering under the condition of 100%.

[0017]

In a conventional capacitor, the leakage current of the capacitor dielectric layer is large, the relative dielectric constant of the capacitor dielectric layer is small, and the Gbit class D
It is not always sufficient for application to a RAM or the like, and there is room for improvement.

An object of the present invention is to provide a semiconductor device having a capacitor including a capacitor dielectric layer having a small leakage current and a high relative dielectric constant.

[0019]

A semiconductor device having a capacitor according to the present invention is a semiconductor device having a capacitor in which a capacitor dielectric layer containing a high dielectric constant material is sandwiched between first and second electrodes. (002) in X-ray diffraction of at least one material of the first and second electrodes
The diffraction peak intensity is at least seven times the (101) diffraction peak intensity in the stacking direction of the first and second electrodes.

In the above aspect, preferably, in the stacking direction of the first and second electrodes, the (002) diffraction peak intensity is at least 17.5 times the (100) diffraction peak intensity.

In the above aspect, preferably, in the stacking direction of the first and second electrodes, the (002) diffraction peak intensity is (102), (103), (110), (11).
It is at least 28 times the intensity of each diffraction peak in 2).

In the above aspect, it is preferable that 95% or more of the crystal of at least one of the materials of the first and second electrodes is (00) in the stacking direction of the first and second electrodes.
2) It has an orientation.

In the above aspect, preferably, the crystal grain size of at least one of the first and second electrodes is 0.1 μm.
m or less.

[0024] In the above aspect, preferably, one of the first and second electrodes is formed on a layer containing at least one of titanium and a titanium compound, and a layer containing at least one of titanium and a titanium compound. And a surface opposite to the surface in contact with the capacitor dielectric layer.

In the above aspect, preferably, one of the first and second electrodes has at least one of Ru and Re.

In the above aspect, preferably, the high dielectric constant material contained in the capacitor dielectric layer is barium strontium titanate, tantalum oxide, lead zirconate titanate, lanthanum lead zirconate titanate, strontium titanate, barium titanate At least one material selected from the group consisting of:

[0027]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a sectional view schematically showing a configuration of a semiconductor device having a capacitor according to Embodiment 1 of the present invention. With reference to FIG. 1, a memory cell structure of a DRAM will be described here as an example of a semiconductor device having a capacitor.

On the surface of the silicon substrate 11 separated by the element isolation insulating layer 13, a MOS transistor 20 is formed.

The MOS transistor 20 has a pair of source / drain regions 15, a gate insulating layer 17, and a gate electrode layer 19. A pair of source / drain regions 15 are formed on the surface of silicon substrate 11 at a distance from each other. The source / drain region 15 has an LDD structure including a low impurity concentration region 15a and a high impurity concentration region 15b. Gate electrode layer 19 is made of, for example, doped polycrystalline silicon, and has a gate insulating layer 1 on a region sandwiched between a pair of source / drain regions 15.
7 are formed.

The periphery of gate electrode layer 19 is covered with insulating layer 21 made of, for example, a silicon oxide film, and bit line 23 made of, for example, doped polycrystalline silicon is electrically connected to one of source / drain regions 15. It is connected to the. The periphery of bit line 23 is covered with insulating layer 25 made of, for example, a silicon oxide film. And M
The upper surface is flattened to cover the OS transistor 20, the bit line 23, etc., for example, BPSG (Boron-do
interlayer insulating layer 27 made of ped Phospho-Silicate Glass)
Are formed. The interlayer insulating layer 27 has a source /
Contact hole 27 reaching the other side of drain region 15
a is formed. Plug layer 9 made of, for example, doped polycrystalline silicon is formed to fill contact hole 27a, and capacitor 10 is formed to be electrically connected to source / drain region 15 through plug layer 9. I have.

The capacitor 10 is connected to the storage node 1
, A capacitor dielectric layer 3 and a cell plate 5. Storage node 1 is formed on interlayer insulating layer 27 and is electrically connected to plug layer 9. The barrier layer 7 is formed of, for example, a single-layer structure of titanium nitride, a two-layer structure of titanium nitride and titanium, or a three-layer structure of titanium, titanium nitride, and titanium. The capacitor dielectric layer 3 is made of the above-mentioned high dielectric constant material, and is formed so as to cover the storage node 1. Cell plate 5 is formed to face storage node 1 with capacitor dielectric layer 3 interposed therebetween.

The storage node 1 is made of, for example, metal ruthenium (Ru), and the (002) diffraction peak intensity of the Ru in X-ray diffraction is seven times or more the (101) diffraction peak intensity, and (100) 17.5 times or more of the diffraction peak intensity of (102), (103),
It is at least 28 times the intensity of each diffraction peak of (110) and (112). That is, 95% of Ru of the storage node 1
The above crystal grains are aligned in the (002) direction in the thickness direction (perpendicular to the surface of the silicon substrate 11).

The storage node 1 has a plane projection size of, for example, 0.2 μm × 1 Gbit DRAM.
It is preferable that the crystal grain size of Ru forming storage node 1 is not more than 0.1 μm.

The cell plate 5 is made of, for example, Ru, similarly to the storage node 1, and the crystal orientation of Ru may be the same as that of the storage node 1.

An interlayer insulating layer 31 is formed so as to cover capacitor 10, and a patterned conductive layer 33 is formed on interlayer insulating layer 31. This conductive layer 3
3, an interlayer insulating layer 35 is formed.
A patterned conductive layer 37 is formed thereon.
Conductive layers 33 and 37 are made of, for example, a material containing aluminum.

The film forming conditions for obtaining the Ru orientation and the crystal grain size in the storage node 1 as described above are, for example, a substrate temperature of 350 ° C. and a sputtering gas pressure of 12 mTorr.
r, sputtering gas: argon / oxygen = 90/10. The condition is not limited to this condition, and the substrate temperature: 200 to 6
At a temperature of 00 ° C., a sputter gas pressure of 1.5 to 24 mTorr, and a sputter gas of argon / oxygen = 95/5 to 70/30, R having the above-described orientation and crystal grain size is used.
u can be produced. The reason why oxygen is added to the sputtering gas under the above conditions is to suppress the growth of crystal grains by mixing oxygen and achieve a finer grain size. In this case, Ru
The oxygen concentration in the film is 0.01 atomic% to 1 atomic%.

Next, an experiment performed by the present inventor will be described. First, as shown in FIGS. 1 and 7, a Ru film is formed on the entire surface of the interlayer insulating layer 27 so as to be in direct contact with the plug layer 9 made of doped polycrystalline silicon embedded in the contact hole 27a of the interlayer insulating layer 27. Films were formed by sputtering under various conditions in the embodiment and the conventional example. A silicon oxide film having a thickness of 50 nm was formed on the Ru film, and this silicon oxide film was patterned by a usual photolithography technique and etching technique. Using the patterned silicon oxide film as a mask, a Ru film is formed by RIE (Reactive Ion Etchi
ng) to obtain a storage node pattern.

When the shape of the storage node after patterning was observed by SEM, it was confirmed that the storage node was roughly classified into two types shown in FIGS. 2 and 3.

FIG. 2 is a plan view (a) and a sectional view (b) showing the shape of a storage node pattern when a film is formed under the conditions of the conventional example, and FIG. 3 is a film formed under the conditions of the present embodiment.

Referring to FIG. 2, in storage node 101 made of Ru formed under the condition of the conventional example, the crystal grains were large and the crystal orientation was random according to the X-ray diffraction evaluation. On the other hand, referring to FIG. 3, in storage node 1 made of Ru formed under the conditions of the present embodiment, crystal grains are fine and uniform, and according to the same X-ray diffraction evaluation, (002) system It was found that the diffraction peak intensity was very strong, and the orientation was preferentially oriented in this direction in the film thickness direction (the direction of arrow D). Also, when viewed from the cross-sectional shape, in the storage node 101 (FIG. 2) manufactured under the condition of the conventional example,
One side wall was cut into a rectangular shape, and the dimensions of the storage node were smaller than planned. On the other hand, in the storage node 1 (FIG. 3) manufactured under the conditions of the present embodiment, each side wall has a shape substantially perpendicular to the surface of the interlayer insulating layer 27.

The orientation of Ru crystal grains 1a and 101a forming storage nodes 1 and 101 shown in FIGS. 2 and 3 was examined. As a result, the degree of orientation of (002) was 95% or more in the storage node 1 shown in FIG. 3, whereas the degree of orientation was lower in the storage node 101 shown in FIG.

Regarding the degree of (002) orientation of Ru,
It measured using the X-ray diffraction peak intensity as follows. When the storage nodes shown in FIGS. 2 and 3 are subjected to X-ray diffraction evaluation, for example, a distribution of X-ray diffraction peaks as shown in FIG. 4 is obtained. In FIG. 4, the diffraction angle is 15 ° to 105 °.
In addition, in addition to the (002) diffraction peak of Ru, relatively strong (100), (101), (102), (10)
3), (110) and (112) may be recognized. In FIG. 4, Ru (100), (10)
No diffraction peaks of (2) and (110) were observed.

Here, the (002) diffraction peak intensity of Ru is 7 times or more for (101), 17.5 times or more for (100), (102), (103), and (11).
If each of 0) and (112) is 28 times or more, it means that 95% or more of the Ru crystal grains of the storage node are aligned in the (002) direction in the film thickness direction.

Further, the change in the leakage current and the relative dielectric constant of the capacitor dielectric layer with respect to the change in the Ru orientation of the storage node was examined. The result is shown in FIG.

Referring to FIG. 5, the Ru of the storage node
As the degree of (002) orientation increases, the leakage current value of the capacitor dielectric layer decreases and the relative dielectric constant increases.

In particular, when the (002) orientation degree is 93%, the leakage current value of the capacitor dielectric layer is 105 nA / cm ² , and when the (002) orientation degree is 95%, 68 nA / cm ^2.
Met.

From this, the inventor of the present application has found that the leakage current and the relative permittivity of the capacitor dielectric layer depend on the (002) orientation of Ru of the storage node.

The reason why the leakage current value increases as the (002) orientation degree decreases is that the crystal orientation of Ru becomes random as shown in FIG. It is conceivable that the sharp dependence of the crystal orientation on the side wall of the storage node 101 causes an acute angle due to gouging, and the electric field concentration occurs at the acute angle.

The reason why the relative dielectric constant of the capacitor dielectric layer increases as the degree of (002) orientation increases is that the crystal orientation of (002) is consistent with the capacitor dielectric layer of a high dielectric constant material having a perovskite structure. Is better, this (00
2) It is considered that by growing a capacitor dielectric layer on a storage node having a high degree of orientation, a capacitor dielectric layer with good crystallinity can be obtained.

From the above, it was found that the reason why the leakage current value of the capacitor dielectric layer was high and the relative dielectric constant was low in the conventional example was that the (002) orientation degree of Ru of the storage node was low.

Further, the inventor of the present application has found that the result of FIG.
It has been found that in order to obtain a leakage current value of the capacitor dielectric layer of not more than 00 nA / cm ^2, the (002) orientation degree of Ru crystal grains must be 95% or more. Here, the leakage current value of the capacitor dielectric layer is 100 nA / cm
^The reason why the value is set to ² or more is that if the capacitor dielectric layer has a leakage current higher than this, a Gbit-class DRAM
This is because a problem arises in the application to the device.

From the above, it has been found that the (002) orientation degree needs to be 95% or more, which cannot be obtained by the conventional manufacturing method, in order to be applied to the Gbit class DRAM.

As described above, when a storage node made of Ru is formed under the conditions of the present embodiment, R
u has a degree of (002) orientation of 95% or more, and the above (0)
02) The condition of the degree of orientation is satisfied. Therefore, in the present embodiment, it is possible to obtain a capacitor having a small leak current of the capacitor dielectric layer and a high relative dielectric constant.

In FIG. 1, the storage node 1
The size of the Ru crystal grains may be large as long as the orientations are aligned as described above, but in a 1 Gbit DRAM, the planar projection size of the capacitor is 0.2 μm × 0.5.
Since it is considered to be about μm, it is preferable that the size is reduced to 0.1 μm or less.

In the present embodiment shown in FIG. 1, Ru has been described as a material of storage node 1, but the same effect can be obtained with Re.

In the present embodiment, the (002) diffraction peak intensity in the X-ray diffraction of the storage node 1 is (10)
1) Since the diffraction peak intensity is 7 times or more, the degree of (002) orientation of crystal grains can be 95% or more. Therefore, the side wall of the storage node 1 can be made substantially flat during the etching when the storage node 1 is patterned. Therefore, it is possible to prevent the leakage current of capacitor dielectric layer 3 from increasing due to the concentration of the electric field in the recess formed on the side wall of storage node 1. Therefore, it is possible to obtain the capacitor 10 with a small leakage current of the capacitor dielectric layer 3.

The (002) orientation of the crystal grains has good matching with the capacitor dielectric layer 3 made of a high dielectric constant material having a perovskite structure. For this reason, (00)
2) When the degree of orientation is 95% or more, the capacitor dielectric layer 3 formed on the storage node 1 has good crystallinity. Therefore, the capacitor 10 having a high relative dielectric constant of the capacitor dielectric layer 3 can be obtained.

Second Embodiment FIG. 6 is a sectional view schematically showing a configuration of a semiconductor device having a capacitor according to a second embodiment of the present invention. 6, the configuration of the present embodiment is different from the configuration of Embodiment 1 shown in FIG. 1 in that an adhesion layer 7 is provided.

Adhesion layer 7 is located between storage node 1 and interlayer insulating layer 27 and electrically connects storage node 1 and plug layer 9. This adhesion layer 7
For example, it has a laminated structure of TiN (titanium nitride) / Ti (titanium).
TiN / Ti laminated structure, TiN / TiSiN / TiS
i or a laminated structure of TiN / TiSiN / Ti.

The storage node 1 has, for example, R
and the degree of orientation of Ru (002) in the direction perpendicular to the surface of the interlayer insulating film 27 is 99% or more.

The remaining structure is the same as that of the first embodiment shown in FIG. 1, and therefore, the same members are denoted by the same reference characters and description thereof will not be repeated.

The inventor of the present application conducted an experiment for examining that the orientation of the storage node 1 made of Ru depends on the base.

An adhesion layer Ti / TiN / Ti or a TiN / Ti structure was formed on a plug layer 9 made of doped polycrystalline silicon as a base structure. Specifically, the adhesion layer was formed by the following steps. First, after a film of Ti was formed, the wafer was taken out, and TiSi (reaction between base silicon and titanium) was produced by lamp heating. Since this lamp heating was performed in a nitrogen or ammonia atmosphere, TiN was simultaneously formed on the surface of Ti. The composition of TiN was analyzed to find that Ti-Si-
Since N was mixedly detected, it may be possible that TiSiN was present. Thereafter, a TiN film is formed again, and a lamp heat treatment is performed in a normal nitrogen atmosphere to form the TiN film.
An N / Ti structure was produced.

Since the TiN / Ti structure was manufactured by the above-described steps, the adhesion layer was accurately formed of TiN / TiN /
It is considered that the layered structure has a laminated structure of Ti, a laminated structure of TiN / TiSiN / TiSi, or a laminated structure of TiN / TiSiN / Ti.

On such an adhesion layer having a TiN / Ti structure, a storage node made of Ru is formed by sputtering under the conditions described in the first embodiment, and a high dielectric constant dielectric film is formed on the storage node. CVD (Chemical Vapor Depositio) of barium strontium titanate
The film was formed by the n) method.

After that, the X-ray diffraction evaluation was performed, and the X-ray diffraction pattern was examined. At a diffraction angle of 15 ° to 105 °, Ru (1) was added to the Ru (002) diffraction peak.
01), (103) and (112) diffraction peaks were observed. The (002) diffraction peak intensity of Ru is about 70 times for (101) and about 300 times for (103) and (112), and 99% or more of Ru crystal grains are (002). ) Orientation. Also, regarding the electrical characteristics of the capacitor dielectric layer, the relative dielectric constant is about 185, and the leakage current density is about 50 when 1.5 V is applied.
nA / cm ² .

Further, if the above-mentioned adhesion layer is formed as a base structure, the substrate temperature can be lowered from room temperature to a low temperature, and the sputter gas can be set to argon / oxygen = 100/0 to contain 95% or more in the storage node without including oxygen. Ru
(002) orientation degree can be obtained. Also, even if the sputtering gas is argon / oxygen = 100/0,
When the above-mentioned adhesion layer has a base structure, the size of the Ru crystal grain of the storage node can be set to 0.1 μm or less.

When the above-mentioned adhesion layer is formed as a base structure, the stability of the electrical characteristics is improved, and the variation in the relative dielectric constant of the capacitor dielectric layer is changed from 165 ± 25 to 185 ± 15. The leakage current density of the dielectric layer was about 50 ± 30 nA / cm ² when 1.5 V was applied, but increased to 50 ± 20 nA / cm ² .

In this embodiment, similar effects can be obtained by using Re instead of Ru as the material of the storage node.

Further, when the storage node is formed on the adhesion layer obtained by the conventional general method under the condition of the conventional example, the (0)
02) It was also confirmed that the degree of orientation was only about 70% to 90%. That is, it has been found that a (002) orientation degree of 95% or more cannot be obtained as long as the conventional storage node and adhesion layer forming process and conditions are used.

Here, a conventional general method of manufacturing an adhesion layer is that a film of Ti and TiN is continuously formed as an adhesion layer,
Annealing (lamp heating in nitrogen atmosphere)
This is a method for obtaining TiSi (reacting underlying silicon and titanium).

In this embodiment, since the TiN / Ti structure serving as the adhesion layer 7 is formed between the storage node 1 and the interlayer insulating layer 27, a (002) orientation degree of 99% or more can be realized. Can be. Therefore, Embodiment 1
It is possible to obtain a capacitor dielectric layer having a smaller leak current and a higher relative dielectric constant.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0075]

According to the semiconductor device having the capacitor of the present invention, at least one of the first and second electrodes has an X.
(001) diffraction peak intensity in X-ray diffraction is (101)
Since the diffraction peak intensity is 7 times or more, the (00)
2) The degree of orientation can be 95% or more. For this reason, at the time of etching when patterning at least one of the first and second electrodes, the side wall surfaces of these electrodes can be made substantially flat. Therefore, it is possible to prevent the leakage current from increasing due to the concentration of the electric field in the recesses formed on the side walls of these electrodes. Therefore, a capacitor dielectric layer having a low leakage current can be realized.

Further, the (002) orientation of at least one of the crystal grains of the first and second electrodes has good matching with the capacitor dielectric layer made of a high dielectric constant material having a perovskite structure. Therefore, when the degree of (002) orientation of the crystal grains is 95% or more, the capacitor dielectric layer formed on the electrode has good crystallinity. Therefore, a capacitor dielectric layer having a high dielectric constant can be realized.

In the above aspect, preferably, in the stacking direction of the first and second electrodes, (0000) in X-ray diffraction of at least one material of the first and second electrodes.
2) The diffraction peak intensity is at least 17.5 times the diffraction peak intensity of (100). Thus, a capacitor dielectric layer having a small leak current and a high relative dielectric constant can be obtained.

In the above aspect, preferably, in the stacking direction of the first and second electrodes, the (002) diffraction peak intensity is (102), (103), (110), (11).
It is at least 28 times the intensity of each diffraction peak in 2). As a result, the (002) orientation degree of 95% or more can be realized, and a capacitor dielectric layer having a small leak current and a high relative dielectric constant can be obtained.

In the above aspect, preferably, 95% or more of the crystal of at least one of the materials of the first and second electrodes is (00%) in the direction of lamination of the first and second electrodes.
2) It has an orientation. Thus, a capacitor dielectric layer having a small leak current and a high relative dielectric constant can be obtained.

In the above aspect, preferably, at least one of the first and second electrodes has a crystal grain size of 0.1 μm.
m or less. This facilitates application of the 1 Gbit DRAM to the storage node.

In the above aspect, preferably, one of the first and second electrodes is formed on a layer containing at least one of titanium and a titanium compound, and a layer containing at least one of titanium and a titanium compound is provided. And a surface opposite to the surface in contact with the capacitor dielectric layer. Thereby, a (002) orientation degree of 99% or more can be realized, and the leakage current is further reduced.
In addition, a capacitor dielectric layer having a high relative dielectric constant can be obtained.

In the above aspect, preferably, at least one of the first and second electrodes has at least one of Ru and Re. By selecting an appropriate material for the electrode in this way, a capacitor dielectric layer having a small leak current and a high relative dielectric constant can be obtained.

In the above aspect, preferably, the high dielectric constant material having a perovskite structure is barium strontium titanate, tantalum oxide, lead zirconate titanate,
It comprises at least one selected from the group consisting of lead lanthanum zirconate titanate, strontium titanate, and barium titanate. By selecting an appropriate material in this manner, the charge amount of the capacitor can be increased.

[Brief description of the drawings]

FIG. 1 is a cross sectional view schematically showing a configuration of a semiconductor device having a capacitor according to a first embodiment of the present invention.

FIGS. 2A and 2B are a plan view and a cross-sectional view illustrating a structure of a storage node when a storage node is formed under the conditions of a conventional example.

FIGS. 3A and 3B are a plan view and a cross-sectional view illustrating a structure of the storage node when the storage node is formed under the conditions according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a distribution of diffraction peak intensities when an X-ray diffraction evaluation of a storage node is performed when Ru is used for the storage node.

FIG. 5 is a graph showing the relationship between the (002) orientation of Ru of the storage node, the leakage current of the capacitor dielectric layer, and the relative permittivity.

FIG. 6 is a sectional view schematically showing a configuration of a semiconductor device having a capacitor according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view schematically showing a configuration of a semiconductor device having a conventional capacitor.

[Explanation of symbols]

1 storage node, 3 capacitor dielectric layer, 5
Cell plate, 10 capacitor.

Claims (8)

[Claims] 1. A semiconductor device having a capacitor in which a capacitor dielectric layer containing a high dielectric material is sandwiched between first and second electrodes, wherein at least one of the first and second electrodes is made of a material. A semiconductor device having a capacitor, wherein the (002) diffraction peak intensity in the X-ray diffraction is 7 times or more the (101) diffraction peak intensity in the stacking direction of the first and second electrodes. 2. The (002) diffraction peak intensity is (100) in the stacking direction of the first and second electrodes.
2. The semiconductor device having the capacitor according to claim 1, which has a diffraction peak intensity of 17.5 times or more. 3. The (002) diffraction peak intensity in the stacking direction of the first and second electrodes is (10)
3. The semiconductor device having the capacitor according to claim 2, wherein the intensity is at least 28 times the diffraction peak intensity of each of (2), (103), (110), and (112). 4. A crystal of at least 95% of a material of at least one of the first and second electrodes has a (002) orientation with respect to a lamination direction of the first and second electrodes. A semiconductor device having the capacitor according to claim 1. 5. The crystal grain size of at least one of the first and second electrodes is 0.1 μm or less.
A semiconductor device having the capacitor according to item 1. 6. One of the first and second electrodes is formed on a layer containing at least one of titanium and a titanium compound, and is in contact with a layer containing at least one of the titanium and the titanium compound. The semiconductor device having the capacitor according to claim 1, wherein the surface facing the surface is in contact with the capacitor dielectric layer. 7. The semiconductor device having a capacitor according to claim 1, wherein one of said first and second electrodes has at least one of Ru and Re. 8. The high dielectric constant material contained in the capacitor dielectric layer comprises barium strontium titanate, tantalum oxide, lead zirconate titanate, lanthanum lead zirconate titanate, strontium titanate, and barium titanate. The semiconductor device having the capacitor according to claim 1, comprising at least one material selected from the group.