JPH10313113A - Semiconductor device - Google Patents

Abstract

(57) Abstract: In a semiconductor device having an LDD structure having a gate electrode side wall (sidewall) insulating film, electrostatic breakdown voltage (ESD) is improved without increasing a manufacturing process and an occupied area. In the same transistor, only a part of a drain region has a region in which a low concentration impurity diffusion region is not formed. In the AA 'cross section of the MOSFET, the source region 102 is composed of the low concentration impurity diffusion region 108 and the high concentration impurity diffusion region 107, while the drain region 101 is composed of only the high concentration impurity diffusion region. I have. On the other hand, in the BB 'section, both the source region 102 and the drain region 101 are composed of a low concentration impurity diffusion region and a high concentration impurity diffusion region. [Effect] An avalanche breakdown phenomenon can be generated at a low voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a circuit structure for protecting a semiconductor device from high voltage such as static electricity.

[0002]

2. Description of the Related Art In a MOSFET, in order to prevent deterioration of transistor characteristics due to hot carriers, a high-concentration impurity diffusion region is separated from immediately below a gate electrode, and a low-concentration impurity diffusion region is formed closer to a channel than a high-concentration impurity diffusion region. In this way, an LDD (Lightly Doped Drain) for improving performance and preventing deterioration of characteristics can be obtained.
n) A structure has been adopted. In the transistor having the LDD structure, as shown in FIG. 6, after the gate electrode 606 is formed, the low concentration impurity diffusion regions 608 and 611 are formed by introducing impurities, and then the gate electrode 606 and the insulating film 605 on the side wall (side wall) of the gate electrode are formed. Using as a mask, high-concentration impurity diffusion regions 604 and 609 are also formed by introducing impurities. Therefore, the output transistor connected to the input / output pad and the MOSFET forming the protection circuit for protecting the semiconductor device from static electricity and the like have the same structure as the transistor forming the logic, and are provided in the low-concentration impurity diffusion region having high resistance. Since a discharge such as static electricity is performed in a state where a high voltage is applied, an ESD (Electro Static) is generated.
Discharge), resulting in a remarkable decrease in breakdown voltage. In order to solve this problem, Japanese Patent Application Laid-Open No. 63-275160
Patent Application Publication
MO that constitutes the logic of the low-concentration impurity region of the FET
There is a method of lowering the resistance of the low-concentration diffusion layer than that of the SFET. Further, as disclosed in JP-A-2-180068, there is a method in which a drain connected to a pad is formed only of a high-concentration diffusion region, and an avalanche breakdown voltage is reduced to improve an ESD withstand voltage.

[0003]

However, Japanese Patent Application Laid-Open No.
In the method disclosed in Japanese Patent No. 275160, it is necessary to form two concentrations of the low concentration diffusion layer, which leads to an increase in the number of manufacturing steps. Further, reliable operation cannot be expected only by changing the transistor structure disclosed in Japanese Patent Application Laid-Open No. 2-180068, and furthermore, it can be used only as a protection circuit, and operation as a MOSFET cannot be expected, resulting in an increase in area. . Therefore, the present invention is to solve such a problem, and the purpose is to:
An object of the present invention is to improve the electrostatic withstand voltage of a semiconductor device having an LDD structure without increasing the number of steps and areas.

[0004]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention is a MOS type semiconductor device having a side wall insulating film on a gate electrode, in which a source / source of a MOSFET electrically connected to an input / output pad by a metal wiring layer. Gate of drain region
The low concentration impurity diffusion region is not formed under a part of the gate electrode side wall insulating film. Further, in a MOS type semiconductor device having a side wall insulating film on a gate electrode, a first source / drain region is electrically connected to an input / output pad by a metal wiring layer, and is connected to a second source / drain region. A first MOSFET in which a first gate electrode formed on a channel region between the first and second source / drain regions is connected to a power supply line for supplying a first potential is provided. ,
The low concentration diffusion layer formed between the gate electrode forming step and the gate electrode side wall insulating film forming step is not formed in the first and second source / drain regions, and the third source / drain region is not formed. A source / drain region is electrically connected to an input / output pad by a metal wiring layer, a fourth source / drain region is connected to a power supply line for supplying a first potential, and the third and fourth A lightly doped diffusion layer is formed in a second MOSFET in which a second gate electrode formed on a channel between a source / drain region and a signal line is connected to the signal line.
Is disposed between the second MOSFET and the input / output pad. Further, in a MOS type semiconductor device having a side wall insulating film in a gate electrode, a first source / drain region is electrically connected to an input / output pad by a metal wiring layer, and is connected to a second source / drain region. The first
And a first MOSFET having a first gate electrode formed on a channel region between the second source / drain regions connected to a power supply line for supplying a first potential. The low concentration diffusion layer formed between the gate electrode forming step and the gate electrode side wall insulating film forming step is not formed in the first and second source / drain regions, and the third source is formed. / Drain region is electrically connected to an input / output pad by a metal wiring layer, a fourth source / drain region is connected to a power supply line supplying a first potential, and the third and fourth sources are connected to each other. Second gate formed on the channel between the source / drain regions.
In the second MOSFET whose gate electrode is connected to the signal line,
A low concentration diffusion layer is formed, and the first MOSFET has a lower impedance with respect to the input / output pad than the second MOSFET.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device according to the present invention will be described below with reference to FIGS. 1, 2, 3, 4, and 5. FIG.

FIG. 1A is a diagram showing a planar structure of a MOSFET according to the present invention, and FIG. 1B and FIG.
Is a diagram showing a cross-sectional structure at AA 'and BB', respectively. A drain region 101 is electrically connected to a pad for bonding to the outside of the semiconductor device via a metal wiring layer or the like, and a drain region 102 is connected to a power supply potential or a ground potential via the metal wiring layer. Source region. Reference numeral 103 denotes a gate electrode, and a MOSFET performs a logical operation according to a signal processed inside the device. As shown in FIG. 1B, in the AA 'cross section of this MOSFET, the source region 102 is composed of a low concentration impurity diffusion region 108 and a high concentration impurity diffusion region 107, while the drain region 101 is It is composed only of the high concentration impurity diffusion region. In FIG. 1A, a hatched area 110 corresponds to this area. On the other hand, in FIG.
In FIG. 1C, which is a cross-sectional view taken along line BB ′,
Both the source region 102 and the drain region 101 are composed of a low concentration impurity diffusion region and a high concentration impurity diffusion region. Accordingly, the same transistor has a structure in which only a part of the drain region has a region 110 in which the low-concentration impurity diffusion region is not formed.

FIG. 2 is a diagram showing another embodiment according to the present invention. In this example, only the shaded region 210 in FIG. 2A is a region where the low concentration impurity diffusion region is not formed. As shown in FIG. 2B, a low-concentration impurity diffusion region 209 is also formed in the drain region 201, but no low-concentration impurity diffusion region is formed in the region indicated by 210 on the gate electrode side. The junction is formed only by the high concentration impurity diffusion region.

The operation of the MOSFET shown in FIGS. 1 and 2 when a high voltage such as static electricity is applied to the drain region connected to the pad will be described with reference to FIGS. 1 and 3. When the potential of the drain region 101 rises due to charges injected into the MOSFET drain region 101 from the outside of the device via the pad, the PN junction formed by the drain region and the well region causes an avalanche breakdown phenomenon, and Charge is injected. As a result, the well potential rises, and a diode formed by the source region and the well region starts flowing a current in the forward direction, causing a bipolar operation to discharge from the source region 103 to the power supply wiring. Done. At this time, the voltage at which the low-concentration impurity diffusion region starts to cause the avalanche breakdown phenomenon is the voltage 301 in the current-voltage curve of FIG. 3, and the voltage at which the high-concentration impurity diffusion region starts to cause the avalanche breakdown phenomenon is lower than 302. Voltage. On the other hand, the clamp voltage during the bipolar operation is determined by the distance between the drain region corresponding to the base region of the bipolar transistor and the source region. In the case of only the structure of FIG.
Reference numeral 304 in FIG. 3 indicates that only the structure shown in FIG.
The discharge is performed at a lower voltage as the interval is smaller. In the case of the MOSFET according to the present invention in which the structures of FIGS. 1B and 1C are both present, the solid line in FIG. Draw the curve shown. Therefore, the maximum value of the voltage applied to the MOSFET is reduced, and the voltage during the discharge is also reduced, so that the excessive voltage stress applied to the MOSFET is greatly reduced. Further, in the MOSFET according to the present invention, only a part of the MOSFET is a region where the low concentration impurity diffusion region is not formed.
There is no hindrance to the function as an FET.

FIG. 4 is a cross-sectional view of a MOSFET according to the present invention in the order of manufacturing steps. FIG. 4A is a cross-sectional structure diagram after the gate oxide film 402 is formed. Element isolation region 401
A gate oxide film 402 is formed in an element formation region surrounded by. Thereafter, as shown in FIG.
The gate electrode 403 is formed by depositing a polycrystalline silicon layer and patterning it. Next, a low-concentration impurity diffusion region is formed. In order to prevent a low-concentration impurity diffusion region from being formed in a part of the source / drain region 404, an impurity is implanted after a resist mask 406 is formed. Source /
The case where low concentration impurity diffusion regions 407 and 408 are formed only in the drain region 404 and a part of the source / drain region 405 is shown. Further, the gate electrode side wall insulating film 4
In FIG. 4E, only a part of the source / drain region shown in FIG. 4E is formed of only the high-concentration impurity diffusion region. The element structure is formed.

FIG. 5 is an arrangement diagram of an output circuit using a MOSFET according to the present invention as a dedicated protection circuit. 50
Reference numeral 1 denotes a pad for making connection with the outside of the device. The drain 503 of the MOSFET according to the present invention and the drain 508 of the output transistor having the LDD structure are electrically connected to each other through a metal wiring layer 502 through a contact 510. I have. The drain region 503 having a structure in which only the high-concentration impurity diffusion region or a portion in which the low-concentration impurity diffusion region is not formed has a larger concentration difference at the junction than the drain region 508 having the low-concentration impurity diffusion region, so that avalanche breakdown occurs. Is easy to occur. This drain 503
With a low impedance with respect to the input / output pad 501,
By arranging between the pad and the output transistor, when a high voltage is applied to the pad, avalanche breakdown occurs only in the high-concentration impurity diffusion region or only in the drain 503 having a structure in which the low-concentration impurity diffusion region is not partially formed. Since the avalanche breakdown does not occur at the drain 508 of the output transistor connected in parallel, the discharge is reliably performed only by the protection circuit.

[0011]

As described above, the gate according to the present invention is used.
In a semiconductor device having a gate electrode side wall insulating film, a low concentration impurity diffusion region is formed only in a part of a source / drain region of a MOSFET used as a protection circuit for protecting the semiconductor device from high voltage such as static electricity. By adopting a structure in which the impurity diffusion region does not extend directly below the gate electrode, the avalanche breakdown generation voltage can be reduced, and the avalanche breakdown phenomenon can be generated at a low voltage. The avalanche breakdown phenomenon occurring at the junction between the high-concentration impurity diffusion region and the well region spreads to the peripheral drain region where the low-concentration impurity diffusion region is formed, and promotes bipolar operation. On this occasion,
Since discharge is performed at a low clamp voltage in the region where the low concentration impurity diffusion region is formed, it is possible to have a high ESD withstand voltage. Further, according to the present invention, the MOSFE
Since the function of T is not lost, the protection circuit area is not unnecessarily increased. Also, the MOSFE according to the present invention
When T is used as a protection circuit and the output terminal is provided together with the output transistor, a protection structure having a drain structure in which only the high-concentration impurity diffusion region or only a part of the low-concentration impurity diffusion region is not formed between the pad and the output transistor By arranging the MOSFET, it is possible to prevent avalanche breakdown from occurring in the output transistor, and to prevent deterioration in the characteristics of the output transistor. Moreover, the drain region in which only the high-concentration impurity diffusion region or only the low-concentration impurity diffusion region is not formed is formed by not implanting the impurity in the low-concentration impurity diffusion region. It is possible to form without performing.

[Brief description of the drawings]

FIG. 1 is a diagram of an embodiment of a MOSFET of a semiconductor device according to the present invention.

FIG. 2 is a diagram of an embodiment of a MOSFET of a semiconductor device according to the present invention.

FIG. 3 is a current-voltage curve during discharge of a semiconductor device according to the present invention.

FIG. 4 is a process cross-sectional view showing a manufacturing process of the semiconductor device according to the present invention.

FIG. 5 is a diagram showing a circuit arrangement of output terminals of a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

101: MOSFET drain region 102: MOSFET source region 103: MOSFET gate electrode 104: MOSFET high concentration impurity diffusion region 105: Gate electrode side wall insulating film 106: Gate oxide film 107: High High concentration impurity diffusion region 108: Low concentration impurity diffusion region 109: Low concentration impurity diffusion region 110: A region where the low concentration impurity diffusion region is not formed 201: MOSFET drain region 202: MOSFET source region 203: MOSFET gate Electrode 204: High concentration impurity diffusion region 205: Gate electrode side wall insulating film 206: Gate oxide film 207: High concentration impurity diffusion region 208: Low concentration impurity diffusion region 209: Low concentration impurity diffusion region 210: Low concentration impurity A region where a diffusion region is not formed. Avalanche breakdown phenomenon generation voltage 302: avalanche breakdown phenomenon generation voltage due to low concentration impurity diffusion region 303: clamp voltage in the presence of low concentration impurity diffusion region 304: clamp voltage in the absence of low concentration impurity diffusion region 401: element isolation region 402: Gate oxide film 403: Gate electrode 404: MOSFET drain region 405: MOSFET source region 406: Resist mask 407: Low concentration impurity diffusion region 408: Low concentration impurity diffusion region 409: Gate Electrode side wall insulating film 410: high concentration impurity diffusion region 411: high concentration impurity diffusion region 501: input / output pad 502: metal wiring connecting input / output pad and drain region of MOSFET 503: drain region of protection MOSFET 504: protection Gate electrode 505 for protection MOSFET: Protection MOS ET source region 506: power supply wiring 507: output MOSFET source region 508: output MOSFET drain region 509: signal line 510: contact hole 601: input / output pad 602: input / output pad and MOSFET drain 603: High-concentration impurity diffusion region 605: Gate electrode side wall insulating film 606: Gate electrode 607: Gate oxide film 608: MOSFET source region 609: High concentration impurity diffusion region 610: Low concentration impurity diffusion region 611: Low concentration impurity diffusion region

Claims (3)

[Claims] In a MOS type semiconductor device having a side wall insulating film in a gate electrode, a source / drain region of a MOSFET electrically connected to an input / output pad by a metal wiring layer under a gate electrode side wall insulating film. A semiconductor device, wherein a low concentration impurity diffusion region is not formed in a part of the semiconductor device. 2. A MOS type semiconductor device having a side wall insulating film in a gate electrode, wherein a first source / drain region is electrically connected to an input / output pad by a metal wiring layer, and
Source / drain region and a first gate electrode formed on a channel region between the first and second source / drain regions are connected to a power supply line for supplying a first potential. The first MOSFET thus formed has a low-concentration diffusion layer formed between the gate electrode forming step and the gate electrode side wall insulating film forming step in the first and second source / drain regions. Is not formed, the third source / drain region is electrically connected to the input / output pad by a metal wiring layer, and the fourth source / drain region is connected to the power supply line supplying the first potential. A low-concentration diffusion layer is formed in a second MOSFET in which a second gate electrode formed on a channel between the third and fourth source / drain regions is connected to a signal line. And the first MOSFET is connected to the second MOSFET.
A semiconductor device disposed between T and an input / output pad. 3. A MOS type semiconductor device having a side wall insulating film on a gate electrode, wherein a first source / drain region is electrically connected to an input / output pad by a metal wiring layer, and
Source / drain region and a first gate electrode formed on a channel region between the first and second source / drain regions are connected to a power supply line for supplying a first potential. The first MOSFET thus formed has a low-concentration diffusion layer formed between the gate electrode forming step and the gate electrode side wall insulating film forming step in the first and second source / drain regions. Is not formed, the third source / drain region is electrically connected to the input / output pad by a metal wiring layer, and the fourth source / drain region is connected to the power supply line supplying the first potential. A low-concentration diffusion layer is formed in a second MOSFET in which a second gate electrode formed on a channel between the third and fourth source / drain regions is connected to a signal line. And the first MOSFET is connected to the second MOSFET.
A semiconductor device having a lower impedance with respect to an input / output pad than T.