JPH10313302A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a 64 k PLL circuit, simplified with a small size without needing an oversampling circuit and a frequency divider or the like. SOLUTION: A bipolar/unipolar(B/U) converter 1 applies B/U conversion to input 64 kbps data, a phase of an extracted clock is compared with the phase of a clock of a VCO 6 at a phase comparator 5 to recover a 64 kHz clock that is synchronized at a normal phase (0 deg.) or at a phase shifted by 180 deg.. In the case of the synchronization at a phase shift of 180 deg., frame asynchronizing information from a frame synchronization circuit 3 resets the phase comparator 5 to conduct phase-locking again, and any block above is recovered. The processing above is repeated until synchronization at the normal phase is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a PLL circuit. 64 kb specified by 703
it / s Directional Interf
The present invention relates to a clock 64k PLL circuit to which an ace signal is input.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional 64k PLL circuit. The configuration of this PLL circuit will be described together with its operation. FIG. 4 is a time chart for explaining the operation.

In 64 kbps DATA, "0" is
It is represented by a signal of 128 kHz, and "1" is represented by a signal of 64 kHz. The B / U converter 101 converts a single column of bipolar signals into two columns of unipolar signals on the positive and negative sides of the bipolar. The two columns of unipolar signals are converted to 64 k by the oversampling circuit 102.
× S VCO (Voltage Controlled Oscillator) 106 is oversampled using an S-times clock of 64 kHz output from the VCO 106, and transmits two columns of oversampled unipolar signals to the encoding processing circuit 103.
A single column unipolar signal obtained by synthesizing two columns of unipolar signals is transmitted to the k CLK (clock) generation circuit 104.
The 64k CLK generation circuit 104 uses a single clock of S times 64 kHz from the input unipolar signal of one column.
64 kHz DATA rising edge and falling edge,
The rising edge of the 128 kHz DATA is detected and 12
A clock having a period of 8 kHz is generated. Further dividing the frequency by 2 generates a clock of 64 kHz. The phase comparison circuit 105 converts the 64 kHz clock from the 64 k CLK generation circuit 104 and the 64 k × SHz clock output from the 64 k × S VCO 106 into a 1 / S frequency divider 1
A comparison is made with the 64 kHz clock frequency-divided at 06, and the comparison result is input to the control unit of the 64 kHz SVCO 106, and a 64 kHz clock synchronized with the input signal is obtained.

[0004]

The conventional 64 kP
The LL circuit uses a technique such as oversampling using a high-speed clock since the input signal is asynchronous and has twice the clock component. Therefore, an oversampling circuit, a frequency divider, and the like are required, and there is a problem that the circuit is complicated and large-scale.

An object of the present invention is to provide a simplified circuit of a 64 kHz PLL circuit without using a technique such as oversampling.

[0006]

SUMMARY OF THE INVENTION A 64k PLL according to the present invention.
In the circuit, ITU-TG. 64k specified by 703
Hz Directional Interface
Focusing on the regularity of e, a circuit for resetting the phase comparator until the clock is normally synchronized and the frame is synchronized without using a technique such as oversampling is provided.

[0007] The present invention relates to ITU-TG. 64 kbit / s Directional specified in 703
64 kbps DAT which is an interface signal
A 64k PLL circuit for encoding and clock synchronization of A converts the input 64 kbps DATA from a bipolar signal to two columns of unipolar signals.
/ U conversion means, means for synthesizing the two columns of unipolar signals by exclusive OR, voltage-controlled oscillating means for outputting a 64 kHz clock, and Phase comparing means for performing a phase comparison and supplying an output thereof to the voltage controlled oscillating means, encoding processing means for reproducing DATA by the 64 kHz clock signal, encoding the DATA, and outputting a timing pulse; Frame synchronization means for detecting whether frame synchronization is established by a frame defined by the obtained DATA and timing pulse, and reset pulse generation means for generating a reset pulse when frame synchronization is not established, Until the frame synchronization circuit changes from an asynchronous state to a synchronous state, Set, characterized in that to establish frame synchronization.

[0008]

FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG.

A 64 kbps PLL circuit for encoding 64 kbps DATA and synchronizing clocks is 64 kbps.
A B / U converter 1 for performing B / U conversion of DATA;
An exclusive OR circuit 4 for combining the two columns of converted output unipolar signals by exclusive OR, and the combined signal and 6
The phase comparator 5 compares the phase of the output of the 4k VCO 6 and reproduces a synchronized clock, and encodes the timing-pulse and encodes the B / U-converted data based on the DATA reproduced by the synchronized 64 kHz clock signal. An encoding processing circuit 2 for outputting, a frame synchronization circuit 3 for putting information on a predetermined frame by the encoded DATA and timing pulse, and detecting whether or not the frames are synchronized; and a synchronization of the frame. , A reset pulse generating circuit 7 for generating a reset pulse from the asynchronous information and supplying the reset pulse to the phase comparator.

FIG. 1 shows the operation of the embodiment of the present invention.
This will be described with reference to FIG. FIG. 2 is a time chart showing the operation.

In 64 kbps DATA, “0” is 1
It is represented by a signal of 28 kHz, and "1" is represented by a signal of 64 kHz. The 64 kbps DATA is converted by the B / U converter 1 into two rows of unipolar signals on the plus side and the minus side of the bipolar signal. These signals are input to the exclusive OR circuit 4, and the output thereof is compared with the output of the 64 k VCO 6 by the phase comparator 5. As a result, either a normally synchronized 64 kHz clock or a synchronized 64 kHz clock at a position shifted by 180 degrees is reproduced. In the latter case, as shown in FIG. 2, since the clock extracted from the data contains a component of 128 kHz, the clock is synchronized at a position shifted by 180 degrees. At this time,
The frame synchronization circuit 3 outputs the frame asynchronous information and resets the phase comparator 5 by the reset pulse generation circuit 7. Synchronization is started again, and any of the 64 kHz clocks is reproduced. By repeating this, a clock synchronized normally can be obtained.

[0012]

As described above, according to the present invention, 64
k PLL circuit is based on ITU-TG. 64 kHz Directional Inte specified in 703
Focusing on the regularity of the rface, a circuit configuration that resets the phase comparator until the clock is normally synchronized and the frame is synchronized without using a technique such as oversampling can provide a simplified and miniaturized circuit. This has the effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a 64k PLL circuit of the present invention.

FIG. 2 is a time chart showing the operation of the embodiment of the 64k PLL circuit of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional 64k PLL circuit.

FIG. 4 is a time chart showing the operation of a conventional 64k PLL circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 B / U converter 2 encoding circuit 3 frame synchronization circuit 4 exclusive OR circuit 5 phase comparator 6 64 k VCO 7 reset pulse generation circuit 101 B / U converter 102 oversampling circuit 103 encoding processing circuit 104 64 k CLK generation circuit 105 Phase comparator 106 64k × S VCO 107 1 / S frequency divider

Claims (3)

[Claims] An input data is converted from a bipolar signal into two.
B / U conversion means for converting into a column unipolar signal, means for synthesizing the two columns of unipolar signals by exclusive OR, voltage control oscillation means for outputting a clock of a predetermined frequency, and the synthesized signal Phase comparing means for comparing the phase with the output clock of the voltage controlled oscillating means, voltage controlled oscillating means for outputting the clock of the predetermined frequency by the output of the phase comparing means, and reproducing data by the clock signal of the predetermined frequency Encoding processing means for encoding data and outputting a timing pulse; frame synchronization means for detecting whether frame synchronization is established by a frame defined by the encoded data and the timing pulse; and establishing frame synchronization. And reset pulse generating means for generating a reset pulse when not performed. PLL circuit frame synchronization circuit resets said phase comparing means until the synchronization state from the asynchronous state, characterized in that to establish frame synchronization. 2. A 64k PLL circuit for encoding and clock synchronization of 64 kbps DATA, a B / U conversion means for converting the input 64 kbps DATA from a bipolar signal to two columns of unipolar signals, and the two columns of unipolar signals. Means for combining signals by exclusive OR, voltage-controlled oscillating means for outputting a 64 kHz clock, phase comparison between the combined signal and the output clock of the voltage-controlled oscillating means, Phase comparing means for supplying to the oscillating means, encoding processing means for reproducing DATA by the 64 kHz clock signal, encoding DATA, and outputting timing pulses, and a frame defined by the encoded DATA and timing pulses To detect if frame synchronization has been established Frame synchronization means, and reset pulse generation means for generating a reset pulse when frame synchronization is not established, resetting the phase comparison means until the frame synchronization circuit changes from an asynchronous state to a synchronized state, 64k PLL circuit characterized by establishing: 3. The system according to claim 1, wherein the 64 kbps data is ITU-
TG. 64 kbit / s Cod specified in 703
3. The 64k PLL circuit according to claim 2, wherein the circuit is an electrical interface signal.