JPH1031460A - Liquid crystal display panel drive device - Google Patents

Abstract

(57) [PROBLEMS] To realize a drive circuit with a reduced memory capacity in a drive device of an STN liquid crystal display panel for simultaneously selecting a plurality of rows. SOLUTION: An image data frame memory 1 develops image data input in a column direction in a row direction as Y column vectors and outputs the image data at an arbitrary speed. Matrix generation circuit 2
Outputs the row vector of one row of the orthogonal matrix in the output section of the column vector for 1H. The arithmetic circuit 3 converts the image data into column signal data by a matrix operation. The column driver 6 drives the simple matrix type liquid crystal display panel 7 using the column signal data as the column signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus for a liquid crystal display panel for driving a simple matrix type liquid crystal display panel by using a method for simultaneously selecting a plurality of rows.

[0002]

2. Description of the Related Art At present, liquid crystal display panels are widely and generally used as flat panel displays. One of the typical types is an STN simple matrix type liquid crystal display panel. Hereinafter, the STN simple matrix type liquid crystal display panel is abbreviated as STN liquid crystal display panel. As shown in FIG. 17, the STN liquid crystal display panel has a structure in which a liquid crystal layer 104 responsive to an effective voltage is sandwiched between two glass substrates 103a and 103b.

A plurality of striped transparent electrodes, row electrodes 101, are formed on a glass substrate 103a, and a plurality of striped transparent electrodes, column electrodes 102, are also formed on a glass substrate 103b. The column electrodes 102 have a relationship orthogonal to each other. From such a simple structure, ST
The N liquid crystal display panel has an advantage that it can be manufactured at low cost. At the same time, high-speed STN liquid crystal display panels capable of displaying video-rate moving images are being developed.
The field of application is expanding.

However, for a high-speed STN liquid crystal display panel, a selection voltage is applied to one row electrode 101 only once in one frame period, and information on pixels on the row is supplied from a column electrode 102. When the conventional line sequential driving method is used, the contrast is significantly reduced. This phenomenon is illustrated in FIG.
It is explained in. In FIG. 18, the signal (a) is a row signal applied to one row electrode 101, the signal (b) is a column signal applied to one column electrode 102,
The signal (c) is a difference signal between the signal (a) and the signal (b) applied to one pixel at the intersection of the row electrode 101 and the column electrode 102.

Since the signal shown in FIG. 18A is a row selection pulse, each row electrode 101 has one pulse in the conventional driving method.
It is selected only once during the frame period. The liquid crystal having a fast response speed in the liquid crystal layer 104 is driven by the signal shown in FIG. 18C, exhibits an optical response like the waveform shown in FIG. 18D, and a phenomenon of a decrease in ON luminance and a rise in OFF luminance appears. ing. Since the human eye perceives the ON luminance and the OFF luminance indicated by the two broken lines on the waveform of FIG. The contrast of the resulting image is reduced. This phenomenon is called a frame response phenomenon.

Therefore, in recent years, a new driving method called a multiple-row simultaneous selection driving method has been proposed. This is a technique for simultaneously selecting a plurality of rows at a time to select one row a plurality of times during one frame period, thereby suppressing a frame response phenomenon. FIG. 19 shows that the frame response phenomenon is suppressed by the multiple row simultaneous selection driving method. FIG.
9, the signal (a) is a row signal applied to one row electrode 101, and the signal (b) is a row signal applied to one column electrode 10.
2 is a column signal applied to (2).
And the signal of FIG.

[0007] As shown in the signal of FIG.
In order to select one row many times at regular intervals within the frame period, the liquid crystal of the pixel driven by the signal in FIG. 19C shows an optical response like the waveform in FIG. A decrease in ON luminance and an increase in OFF luminance as in the sequential driving method are prevented, and high contrast is obtained. FIG. 20 shows an outline of specific processing of the multiple-row simultaneous selection driving method. First, a row signal to the row electrode 101 will be described. In the orthogonal matrix 111, each data is made up of binary values of 1, -1 or ternary values of 1, 0, -1. Of the column vectors constituting the matrix, the inner product value of any two different column vectors is , Are always zero. The row driver 5 repeatedly applies a voltage proportional to the data of the orthogonal matrix 111 to the row electrode 101 as a row signal. Such an orthogonal matrix 111
Of the three values of the row electrode 101
Is the selection pulse for Therefore, the orthogonal matrix 11
The row electrodes 111 are simultaneously selected by the total number of 1, -1 of one row vector of 1, and one row electrode 101 is selected by the total number of 1, -1 of one column vector of the orthogonal matrix 111.
The selection is made in one frame period.

Next, a column signal to the column electrode 102 will be described. For one frame of digital image data 112 (-1 corresponds to ON, 1 corresponds to OFF) to be displayed on the liquid crystal display panel, column signal data 113 which is a product of the orthogonal matrix 111 is created. The column driver 6 applies a voltage proportional to each data value of the column signal data 113 to the column electrode 102 as a column signal.

Two signals of a row and a column are ith (i is an integer of 0 or more and less than X) 1H period (1 frame period = 1
In the H period × X), the data on the i-th row of the orthogonal matrix 111 is applied to the row electrode 101, and the data on the i-th row of the column signal data 113 is applied to the column electrode 102. In this way, an effective value voltage proportional to the image data 112 to be displayed is accumulated in each pixel between the electrodes 101 and 102 in one frame period. The liquid crystal layer 104 of each pixel is
Since light is transmitted according to the effective voltage between the row electrode 101 and the column electrode 102, an image is displayed on the liquid crystal display panel.

In the driving device that performs this driving method, an operation is performed on data of one column of the image data 112 to obtain one data of the column signal data 113. The order of outputting each data of the image data 112 will be described with reference to the matrix of the image data 112 in FIG. 20. x _1,1 → x _2,1 → x _3,1 → x _4,1 → x _1,2 → x _2,2 →... → x _4,4 , but the input of image data 112 is x _1,1 → x _1,2 → x _1,3 → x _1,4 → x _{2, 1} → x _2,2 →... → x ₄ , ₄

That is, since the input and output access directions are different, in order to temporarily store and output the image data 112, two frame memories having a capacity capable of holding the image data 112 are used, and one of the frame memories is used for the input. Do
The operation of outputting the image data 112 one frame before held in the other frame memory in the direction necessary for performing the operation needs to be alternately performed for each frame.

On the other hand, each data of the column signal data 113 is
As shown in FIG. 20, the inner product value of the column vector of the image data 112 and the row vector of the orthogonal matrix 111 is obtained.
Is calculated while advancing the row vector in order from the first row to the last row, so that the column signal data 113 is created in the following order.

Y _1,1 → y _2,1 → y _3,1 → y _4,1 → y _1,2 → y _2,2 →... → y _4,4 Column signal data created in this way Since 113 is used in units of one row as shown in FIG. 20, it is sent to the column driver 6 in the following order. y _1,1 → y _1,2 → y _1,3 → y _1,4 → y _2,1 → y _2,2 → ... → y _4,4 Therefore, in the case of the column signal data 113, the image data 1
As in the case of 12, a frame memory having a capacity twice as large as the data size is required.

Further, even if the number of rows to be selected simultaneously is reduced by inserting 0 into an orthogonal matrix consisting of binary values of 1 and -1 as the orthogonal matrix, the same contrast as in the case of simultaneous selection of all rows can be obtained. (See 1993 SID Dige for details)
st of Papers, pp.89-92), but conventionally, 1,0, -1
The calculation was performed using the matrix Z of (Expression 1) consisting of the three values of

[0015]

(Equation 1)

[0016]

(Equation 2)

[0017]

(Equation 3)

[0018]

(Equation 4)

[0019]

(Equation 5) On the other hand, the matrix Za of (Equation 2) is obtained by combining an orthogonal matrix N composed of binary values of 1 and -1 as in (Equation 3) and a unit matrix L as in (Equation 4). It can be obtained by expansion by the method represented by the equation, and by using the matrix Za of (Equation 2), it is possible to reduce the number of image data necessary for calculating the column signal data 113. However, in order to do so, it is necessary to expand the image in the time direction so as not to lower the contrast, but the method is not specified.

[0020]

Therefore, when the above-described multiple row simultaneous selection driving method is attempted, the column signal data 1
In order to calculate 13, it is necessary for the frame memory to have twice the capacity for each of the image data and the column signal data. Further, since the writing direction and the reading direction of the frame memory are different, it is necessary to use memories having the same access speed in each direction. Therefore, when a standard dynamic RAM is used, the speed in one access direction is insufficient and cannot be used, and an expensive video RAM (VR) is used.
AM) must be used. Therefore, there is a problem that the cost of the entire driving device increases.

An object of the present invention is to provide a driving apparatus for a liquid crystal display panel which realizes a driving method equivalent to the conventional driving method using only a frame memory for image data and can reduce the memory capacity and the cost of the entire driving apparatus. It is to be.

[0022]

According to a first aspect of the present invention, there is provided a driving apparatus for a liquid crystal display panel, wherein a liquid crystal responding to an effective value voltage is sandwiched between X number of row electrodes and Y number of column electrodes. The STN liquid crystal display panel is driven by using a method of driving n of the row electrodes at the same time. Input / output of digital image data of X rows and Y columns is performed in the column direction, and a plurality of times of input is performed. A frame memory consisting of n memories having twice the capacity of X / n rows and Y columns outputting at a speed, a matrix generating circuit for holding and outputting a row signal pattern for driving a row electrode as an n-order matrix, An arithmetic circuit that converts image data output from the buffer memory with output data of the matrix generation circuit and outputs the converted signal as column signal data, a row driver that drives a row electrode using the output data of the matrix generation circuit, and an arithmetic circuit. Output And a column driver for driving the column electrodes with a signal data.

According to this configuration, the image data, which is a column vector, is input to the arithmetic circuit from the buffer memory for each clock obtained by multiplying the system clock, which is the input unit time of the digital image data of one pixel, by n rows and one column. , The output data of the matrix generation circuit is input to the arithmetic circuit as a row vector in the column signal data processing section. Further, the image data which is a column vector is developed in the time direction by switching in the row direction for each column signal data processing of n rows and 1 column. Therefore, the column signal data output from the arithmetic circuit is output at a multiple speed in the column direction, and the desired column signal data can be created to drive the column electrodes.

According to a second aspect of the present invention, a liquid crystal display panel driving device includes a liquid crystal responsive to an effective value voltage between X number of row electrodes and Y number of column electrodes. The STN liquid crystal display panel is driven by using a method of driving the LCD panel. The input / output of the digital image data of X rows and Y columns is performed in the column direction, and the output is performed at a speed several times as fast as the input. A frame memory consisting of 2n memories having a capacity of / n rows and Y columns, a matrix generation circuit for holding and outputting a pattern of a row signal for driving a row electrode as an n-order matrix, and a buffer of output data of the matrix generation circuit An arithmetic circuit that converts image data output from the memory and outputs it as column signal data, a row driver that drives a row electrode using output data of the matrix generation circuit, and a column signal data output from the arithmetic circuit. And a column driver for driving the electrodes.

According to this configuration, the image data, which is a column vector, is input to the arithmetic circuit from the buffer memory for each clock obtained by multiplying the system clock, which is the unit time for inputting digital image data of one pixel, by n rows and one column. , The output data of the matrix generation circuit is input to the arithmetic circuit as a row vector in the column signal data processing section. Further, the image data which is a column vector is developed in the time direction by switching in the row direction for each column signal data processing of n rows and 1 column. Therefore, the column signal data output from the arithmetic circuit is output at a multiple speed in the column direction, and the desired column signal data can be created to drive the column electrodes.

According to a third aspect of the present invention, there is provided a driving apparatus for a liquid crystal display panel, wherein a liquid crystal responding to an effective value voltage is sandwiched between X number of row electrodes and Y number of column electrodes. The STN liquid crystal display panel is driven by using a method of driving n pixels at the same time. Digital image data of X rows and Y columns is input / output in the column direction, and output is performed at twice the speed of input. A frame memory composed of n memories having a capacity 1.75 times as large as X / n rows and Y columns, a matrix generation circuit for holding and outputting a pattern of a row signal for driving a row electrode as an n-order matrix, and a matrix An operation circuit that converts image data output from the buffer memory with output data of the generation circuit and outputs it as column signal data, a row driver that drives row electrodes using output data of the matrix generation circuit, and an output circuit that is output from the operation circuit. Column signal And a column driver for driving the column electrodes with over data.

According to this configuration, the image data, which is a column vector, is input from the buffer memory to the arithmetic circuit at every clock that is twice the system clock, which is the input unit time of the digital image data of one pixel, and n rows and one column , The output data of the matrix generation circuit is input to the arithmetic circuit as a row vector in the column signal data processing section. Further, the image data which is a column vector is developed in the time direction by switching in the row direction for each column signal data processing of n rows and 1 column. Therefore, the column signal data output from the arithmetic circuit is output at twice the speed in the column direction, and the desired column signal data can be generated to drive the column electrodes.

According to a fourth aspect of the present invention, there is provided a driving device for a liquid crystal display panel, wherein a liquid crystal responding to an effective value voltage is sandwiched between X number of row electrodes and Y number of column electrodes. The STN liquid crystal display panel is driven using a method of driving n pixels at the same time, and is 1.5 times as large as X / n rows and Y columns for inputting / outputting digital image data of X rows and Y columns in the column direction. A frame memory composed of n memories having a capacity, a matrix generation circuit for holding and outputting a pattern of a row signal for driving a row electrode as an n-dimensional matrix, and an image output from the buffer memory with output data of the matrix generation circuit An arithmetic circuit that converts data and outputs the data as column signal data, a row driver that drives row electrodes using output data of the matrix generation circuit, and a column that drives column electrodes using column signal data output from the arithmetic circuit Driver and It is provided.

According to this configuration, the image data as the column vector is input from the buffer memory to the arithmetic circuit from the buffer memory at every system clock which is the input unit time of the digital image data of one pixel, and the column signal data processing of n rows and 1 column is performed. Output data of the matrix generation circuit is input to the arithmetic circuit as a row vector in the section. The image data that is a column vector is n
By switching in the row direction for each column signal data processing in the row 1 column, the data is developed in the time direction. Therefore, column signal data output from the arithmetic circuit is output in the column direction, and desired column signal data can be created to drive the column electrodes.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a driving device for a liquid crystal display panel according to a first embodiment of the present invention. In FIG. 1, a frame memory 1 for image data has Y columns in the horizontal direction and 2X / n in the vertical direction.
This is a group of n buffer memories having a capacity to hold the image data signal of the row,
A matrix A of X rows and Y columns, which is digital image data for a frame, is divided into n buffer memories and temporarily stored in each buffer memory as shown in FIG.

The n buffer memories holding the image data of X rows and Y columns output the image data, which is the column vector required for the n-th matrix operation, in the column direction every clock. Here, one clock indicates a unit time obtained by multiplying an input clock of digital image data of one pixel by a plurality of times, and is hereinafter abbreviated as one clock. In addition, the output order of the image data is changed in the row direction for each 1H output section and output, whereby the development in the time direction is performed. Here, the 1H output section indicates a Y clock section for processing column signal data of n rows and 1 column.
Abbreviated as 1H output section.

Although it is described that the output clock is a multiple of the input clock, it is necessary to increase the frame frequency in order to prevent vertical line noise (splicing) generated in the STN liquid crystal panel. Therefore, the output clock is multiplied a plurality of times. The multiple is
There is no particular relation to the numerical value n, and the frame frequency may be multiplied by a multiple (an integer multiple of 2 or more).
In view of other characteristics such as liquid crystal display performance and memory speed,
In reality, it is assumed to be about twice. However, even if it is necessary to increase the frequency by three to four times in view of the performance of the liquid crystal panel, it can be realized by the same circuit.

The matrix generation circuit 2 is constituted by a ROM,
Data of one row of an n-row, n-column orthogonal matrix N consisting of binary values of -1 is output as a row vector in a 1H output section. The arithmetic circuit 3 calculates the inner product of the row vector of the orthogonal matrix N input from the matrix generation circuit 2 and the image data which is the column vector output from the frame memory 1, and calculates a matrix B of X rows and Y columns as column signal data. Are sequentially obtained and transferred to the column driver 6.

The column driver 6 converts the data sent from the arithmetic circuit 3 into a voltage corresponding to the analog data corresponding to the column signal data of the matrix B corresponding to the time t within one frame period, and converts the data to the STN liquid crystal display panel 7. To the Y column electrodes. Further, the matrix generation circuit 2 sequentially outputs the row vectors of the nth-order orthogonal transform N in correspondence with the output of the column signal data. The row driver 5 applies a voltage corresponding to the data output from the matrix generation circuit to X row electrodes of the STN liquid crystal display panel 7.

Thus, after performing a matrix operation using the orthogonal matrix Za obtained by expanding the orthogonal matrix N of n rows and n columns shown in (Equation 5) with a unit matrix, (Equation 2) is converted into (Equation 1). A voltage corresponding to each data of one row expanded in the time direction can be applied to the X row electrodes of the STN liquid crystal display panel so as to correspond to the converted column signal data.

Hereinafter, the individual components will be described in detail. First, the configuration of the frame memory 1 will be described.
In the present embodiment, the frame memory 1 stores n shown in FIG.
Buffer memories 12 to 14 having independent input and output
And an input / output control circuit 11. The input addresses are stored in the input / output control circuit 1 in the n buffer memories 12 to 14.
In response to the input of valid image data from the outside, one buffer memory capable of inputting is selected and input. An output address is input from the input / output control circuit 11 to the n buffer memories 12 to 14, and data output from the n buffer memories holding data for one frame is represented by a column vector image. 1 as data
Output every clock. As shown in FIG. 3, each of the buffer memories 12 to 14 has a two-dimensional memory 17 composed of Y pixels, which is the number of pixels in the horizontal direction, and 2X / n pixels, which is the number of pixels in the vertical direction. Be composed. Reference numeral 15 denotes an input address counter, and 16 denotes an output address counter.

Next, the detailed operation of the input / output timing of the frame memory 1 will be described with reference to FIG. First, image data input from the outside is input in the order of arrows as shown in FIG. 5 based on the frame reference signal of (a). In the XH section among these, as shown by the buffer memory input control signals (c) and (d), input is sequentially performed to the n buffer memories for each line reference signal (b). Therefore, image data for one field is held in the n buffer memories from the first line to the X / n-th line shown in the input control mode (e). When the next field reference signal (a) is input, the input is performed from the n / X + 1 line to the 2X / n line.

On the other hand, the image data of one frame input to the n buffer memories is divided into the output control mode section (f) and the 1st to X / n lines of the buffer memory every 1H output section. The data is supplied to the arithmetic circuit 3 while being converted in the row direction. As a result, the data is developed in the time direction. At the same time when the input to the buffer memory is completed from the X / n + 1 line to the 2X / n line, the calculation of the X row and the Y column using the first line to the X / n line is completed, and the first line of the buffer memory is again executed. And the X / nth line can be input, and the X / n + 1th line to the 2X / nth line are similarly output. By sequentially performing this, the image data as the column vector is sequentially output from the frame memory 1, and it becomes possible to sequentially perform the operation on the row vector of one row in the orthogonal matrix N of n rows and n columns.

Next, the operation of the matrix generation circuit 2 and the operation circuit 3 will be described with reference to the drawings. The matrix generation circuit 2 is constituted by a ROM, and generates a row vector of the orthogonal matrix N once to generate a row vector of the orthogonal matrix N during the output 1H period. The image data is output as a column vector shown in FIG. 7A Y times in the 1H output section as shown in FIG. 7B. The matrix operation is performed in n rows Y as shown in FIG.
By calculating the row vector of one row of the n-th orthogonal matrix for the image data of the column, column signal data of one row and Y columns is output. By switching the row every 1H output section and outputting n times in the output section of one frame, column signal data of one frame is created as shown in FIG. Since the output column signal data is developed in the time axis direction, the column driver 6
Supplied to In this embodiment, the matrix generation circuit 2
Although the OM is used, a similar effect can be obtained by using a RAM.

As described above, according to the first embodiment of the present invention, the Y column of the image data, which is the column vector, and the same row vector of the orthogonal matrix in the 1H output section at a multiple speed of the system clock. , The column signal data can be output in the column direction, and the desired column signal data can be created to drive the column electrodes. As described above, according to the liquid crystal display panel driving device of this embodiment, a driving method equivalent to the conventional driving method can be realized only by the frame memory for image data, and the memory capacity can be reduced and the cost of the entire driving device can be reduced. it can.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. The block diagram of the driving device of the liquid crystal display panel according to the second embodiment of the present invention is the same as the configuration described above with reference to FIG. 1, and therefore the description thereof is omitted, and the detailed configuration of the frame memory 1 of the present invention is shown in FIG. An explanation will be given using the following.

In this embodiment, the frame memory 1 includes 2n buffer memories 12 to 15, an input / output control circuit 11, and an output selection circuit 16 shown in FIG. 2n
The input addresses are input to the buffer memories 12 to 15 from the input / output control circuit 11, and one input-capable buffer memory is selected and input in response to input of valid image data from the outside. Also, n buffer memories 12 to
An output address is input to the input / output control circuit 11 from the input / output control circuit 11, and data output from n memories holding image data for one frame is output as image data as a column vector every clock. Each of the buffer memories 12 to 15 is a one-port memory having a two-dimensional capacity including Y pixels, which is the number of pixels in the horizontal direction, and X / n pixels, which is the number of pixels in the vertical direction.

Next, the detailed operation of the input and output timings of the frame memory 1 will be described with reference to FIG. First, image data input from the outside is input in the order of arrows as shown in FIG. 5 based on the frame reference signal of (a). In the XH section, (c), (d)
As shown by the buffer memory input control signal of (b), input is sequentially performed for each line reference signal of (b) into the 2n buffer memories, and as shown in the input control mode (e) of FIG. The data is input to the buffer memories up to the first.
Therefore, one field of image data is stored in the n buffer memories from the first line to the X / nth line. When the next field reference signal of (a) is input, the input is performed to the (n + 1) th to (2n) th buffers.

On the other hand, the image data of one frame input to the n buffer memories is divided into the output control mode section (f) and the first to nth buffer memories in the row direction every 1H output section. And outputs the result to the arithmetic circuit 3. As a result, the data is developed in the time direction.
Further, at the same time when the input to the buffer memory is completed from the (n + 1) th to the (2n) th, the X using the first to the nth is used.
When the calculation of the row Y column is completed, the first to n-th buffer memory can be input again,
The same applies to the n-th output. By sequentially performing this, the image data as the column vector is sequentially output from the frame memory 1, and it becomes possible to sequentially perform the operation on the row vector of one row in the orthogonal matrix N of n rows and n columns.

As described above, according to the second embodiment of the present invention, the Y column of the image data as the column vector and the same row vector of the orthogonal matrix in the 1H output section at a multiple speed of the system clock. , The column signal data can be output in the column direction, and the desired column signal data can be created to drive the column electrodes. As described above, according to the liquid crystal display panel driving device of this embodiment, a driving method equivalent to the conventional driving method can be realized only by the frame memory for image data, and the memory capacity can be reduced and the cost of the entire driving device can be reduced. it can.

Third Embodiment Next, a third embodiment of the present invention will be described with reference to the drawings. The block diagram of the driving device of the liquid crystal display panel according to the third embodiment of the present invention is the same as the configuration described above with reference to FIG. 1, and therefore the description thereof is omitted, and the detailed configuration and operation of the buffer memory 1 of the present invention will be described. FIGS. 12, 13 and 14 show the case where the number of input lines X = 16 and the number of selected lines n = 4.
This will be described in detail with reference to FIG. The third embodiment and the first
Is that the memory capacity is doubled to 1.75.
That is, the clock speed is changed from multiple times to double. In the first embodiment, the clock speed can be set to any number of times. However, in this embodiment, the memory capacity is limited to 1.75 times.
The frame frequency can only be increased up to twice (up to one).

First, the image data frame memory 1
The buffer memory group includes n buffer memories each having a capacity of holding Y pixels in the horizontal direction and data signals of 1.75 X / n rows in the vertical direction. As shown in FIG. 12, four buffer memories each having a capacity of 7 lines in the vertical direction are provided. It consists of a buffer memory. As shown in FIG. 13, the image data is sequentially input to each buffer memory every 1H. As shown in FIG. (B), (c),
(D) and (e) are input to the buffer memories 1-4.

Here, as shown in FIG. 13 (f), since the n buffer memories holding the image data are output at the double speed clock, it is necessary to output the data twice in the 1H input section. become. Here, the double speed clock is obtained by doubling a system clock to which digital image data of one pixel is externally input, and is hereinafter abbreviated as a double speed clock. In this case, it is necessary to read out the data of the same line from the buffer memory during the section where the (e) input line to the buffer memory 4 is the fourth line. In this case, as shown in FIG. 14, this can be realized by preceding the input reference signal of (b) with the output reference signal of (d). In FIG. 14, (a) shows the input H line No. (C) is the input valid period, and (e) is the output valid period.

Here, the point that the input reference signal of (b) precedes the output reference signal of (d) will be described. When the output frequency is twice the input frequency, if the output start of the half cycle is delayed, the end of writing and the end of reading are simultaneous. However, the memory does not output the written data unless it is delayed by one clock or more after the writing is completed.
If the output side is delayed by one clock or more, desired data will be output.

As described above, according to the third embodiment of the present invention, the Y column of image data, which is a column vector, and the same row vector of an orthogonal matrix are calculated in a 1H output section using a double speed clock. By performing the above, column signal data can be output in the column direction while reducing the number of frame memories, and desired column signal data can be created to drive the column electrodes.

As described above, according to the liquid crystal display panel driving apparatus of this embodiment, a driving system equivalent to the conventional driving method is realized only by the frame memory for image data, and the memory capacity is reduced and the cost of the entire driving apparatus is reduced. can do. (Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to the drawings.

The block diagram of the driving device of the liquid crystal display panel according to the fourth embodiment of the present invention is the same as that described with reference to FIG. Regarding the operation, the number of input lines X = 1
6 and FIG. 15 and FIG.
6 will be described in detail. The difference between the fourth embodiment and the first embodiment is that the memory capacity is doubled to 1.5 times.
That is, the clock speed is changed from multiple times to one time. Hereinafter, this point will be described. In the first to third embodiments, the frame frequency is increased to a multiple of a multiple. However,
If the frame frequency is doubled at the time of input, a desired matrix operation can be performed with a reduced memory capacity.
In the case of the embodiment, the embodiment is shown as a configuration for a signal whose frame frequency is increased. When the memory capacity is 1.5 times, the clock speed is limited to 1 time.

First, the image data frame memory 1
N buffer memory groups each having a capacity of holding data signals of Y pixels in the horizontal direction and 1.5X / n rows in the vertical direction;
As shown in FIG. 12, 4 lines having a capacity of 6 lines in the vertical direction
It is composed of a number of buffer memories. Further, as described above, the data is sequentially input to each of the buffer memories 1 to 4 every 1H, and as shown in FIG. (B), (c),
(D) and (e) are input to the buffer memory.

Here, as shown in FIG. 16 (f), the n buffer memories holding the image data output the data once for an input section of 1H. In that case,
In the section (e) where the input line to the buffer memory 4 is input to the fourth line, it is necessary to read the data of the same line from the buffer memory. However, this can be realized by preceding the input reference signal with the output reference signal as described above. In the section (b) in which the input line to the buffer memory 1 is input to the first line, it is necessary to read the data of the previous line from the buffer memory. In this case, the output reference signal can be realized by preceding the input reference signal.

As described above, according to the fourth embodiment of the present invention, the Y-column of the image data, which is the column vector, and the same row vector of the orthogonal matrix are calculated in the 1H section, thereby obtaining the frame memory. It is possible to output column signal data in the column direction while reducing the number of columns, and it is possible to generate desired column signal data and drive column electrodes. in this way,
According to the liquid crystal display panel driving device of this embodiment, the same driving method as that of the related art can be realized only by the frame memory for image data, and the memory capacity can be reduced and the cost of the entire driving device can be reduced.

[0056]

As described above, according to the present invention, the output of the frame memory is performed as a column vector in the same access direction as the image data, so that the capacity of the image data memory can be reduced and a low-cost memory can be realized. A drive circuit equivalent to that used in the related art can be provided at a low price.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a drive device for an STN liquid crystal display panel according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an image data frame memory 1;

FIG. 3 is a block diagram showing a configuration of an image data buffer memory 12;

FIG. 4 is a timing chart showing an operation of the image data frame memory 1;

FIG. 5 is an explanatory diagram showing an input order of image data to the image data frame memory 1;

FIG. 6 is an explanatory diagram showing an input order of image data to the image data buffer memory 12;

FIG. 7 is an explanatory diagram showing one unit output from the image data frame memory 1 and an output order of image data output in a 1H output section.

FIG. 8 is an explanatory diagram showing column signal data output in a 1H output section.

FIG. 9 is an explanatory diagram showing an output order of column signal data from the arithmetic circuit 2.

FIG. 10 is a block diagram showing a configuration of an image data buffer memory 1 according to a second embodiment of the present invention.

FIG. 11 is a timing chart showing an operation of the image data frame memory 1 according to the second embodiment of the present invention.

FIG. 12 is an explanatory diagram showing a configuration of an image data buffer memory 1 according to a third embodiment of the present invention.

FIG. 13 is a timing chart showing an operation of the image data buffer memory 1 according to the third embodiment of the present invention.

FIG. 14 is a detailed timing chart showing an operation of the image data buffer memory 1 according to the third embodiment of the present invention.

FIG. 15 is an explanatory diagram showing a configuration of an image data buffer memory 1 according to a fourth embodiment of the present invention.

FIG. 16 is a timing chart showing an operation of the image data buffer memory 1 according to the fourth embodiment of the present invention.

FIG. 17 is a schematic view showing the structure of a conventional simple matrix type liquid crystal display panel.

FIG. 18 is a driving waveform diagram and an optical response waveform diagram when a conventional line-sequential selection driving method is used.

FIG. 19 is a drive waveform diagram and an optical response waveform diagram when a multiple-row simultaneous selection drive method is used.

FIG. 20 is an explanatory diagram showing the concept of a multiple row simultaneous selection driving method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Frame memory for image data 2 Matrix generation circuit 3 Operation circuit 5 Row driver 6 Column driver 7 Simple matrix type liquid crystal display

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Hideyuki Nakanishi 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] 1. A matrix type liquid crystal display using a method in which a liquid crystal responding to an effective value voltage is sandwiched between X row electrodes and Y column electrodes, and n of the X row electrodes are simultaneously driven. A driving apparatus for a liquid crystal display panel for driving a panel, wherein input / output of digital image data of X rows and Y columns is performed in a column direction, and X / n outputs at a plurality of times the input speed.
A frame memory consisting of n memories having twice the capacity of the row Y column; a matrix generating circuit for holding and outputting a pattern of a row signal for driving the row electrodes as an n-dimensional matrix; and an output of the matrix generating circuit An arithmetic circuit for converting image data output from the frame memory with data and outputting it as column signal data; a row driver for driving a row electrode using output data of the matrix generating circuit; and an output from the arithmetic circuit A driving device for a liquid crystal display panel, comprising: a column driver that drives a column electrode using column signal data. 2. A matrix type liquid crystal display using a method in which a liquid crystal responsive to an effective value voltage is sandwiched between X row electrodes and Y column electrodes and n of the X row electrodes are driven simultaneously. A drive device for a liquid crystal display panel for driving a panel, wherein X / n performs input / output of digital image data of X rows and Y columns in a column direction and outputs at a plurality of times speed of input.
A frame memory consisting of 2n memories having a capacity of row Y columns; a matrix generation circuit for holding and outputting a pattern of a row signal for driving the row electrodes as an n-th order matrix; An arithmetic circuit that converts image data output from the frame memory and outputs it as column signal data; a row driver that drives a row electrode using output data of the matrix generation circuit; and a column signal data output from the arithmetic circuit A driving device for a liquid crystal display panel, comprising: a column driver that drives a column electrode by using the same. 3. A matrix type liquid crystal display using a method in which a liquid crystal responding to an effective value voltage is sandwiched between X row electrodes and Y column electrodes and n of the X row electrodes are driven simultaneously. A drive device for a liquid crystal display panel for driving a panel, wherein input / output of digital image data of X rows and Y columns is performed in a column direction and output of X / n rows and Y columns is performed at twice the speed of input. A frame memory consisting of n memories having a capacity of 1.75 times, a matrix generation circuit for holding and outputting a pattern of a row signal for driving the row electrodes as an n-dimensional matrix, and output data of the matrix generation circuit An arithmetic circuit that converts image data output from the frame memory and outputs it as column signal data; a row driver that drives a row electrode using output data of the matrix generation circuit; and a column signal output from the arithmetic circuit Driving device for a liquid crystal display panel and a column driver for driving the column electrodes with over data. 4. A matrix type liquid crystal display using a method in which a liquid crystal responding to an effective value voltage is sandwiched between X row electrodes and Y column electrodes, and n of the X row electrodes are simultaneously driven. A liquid crystal display panel driving device for driving a panel, comprising: n memories having a capacity 1.5 times that of X / n rows and Y columns for inputting / outputting digital image data of X rows and Y columns in a column direction. A frame memory, a matrix generation circuit for holding and outputting a pattern of a row signal for driving the row electrodes as an n-order matrix, and converting image data output from the frame memory with output data of the matrix generation circuit to form a column. An arithmetic circuit that outputs signal data; a row driver that drives row electrodes using output data of the matrix generation circuit; and a column driver that drives column electrodes using column signal data output from the arithmetic circuit. Driving device for a liquid crystal display panel having.