JPH10318708A - Proximity detection method for centering a signal within the dynamic range of a peak detection proximity detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a proximity detector having a magnetic field to voltage transducer and automatically centering a transducer output voltage within a dynamic range of the transducer signal detector. A Hall voltage amplifier (12) has an analog voltage (Vs) having a locus of one polarity corresponding to the passage of a magnetic substance.
ig. Reference voltages V _P2 and V _N2 are generated which are equal to the positive and negative trajectories of the most recent peak at Vsig, respectively. Is above and below the center of the dynamic voltage range of each detector DC offset limit voltage V _A and V _B
Is given, the signal Vsi when the entire signal Vsig at the output of the median Vos time is greater than V _A amplifier Vsig is biased in the negative direction, also is less than V _B Vos
g is moved in a smaller positive direction, and Vos is
Keep in the range from _B to _VA .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak-based threshold.
threshold (hereinafter referred to as "peak reference threshold") detection-type proximity detector, and more particularly, to an iron gear tooth transducer including a Hall element and a Hall voltage amplifier, and more particularly, the output voltage signal peak of the transducer is a detector. Automatically centered within the dynamic range of the transducer. In addition, this application is 1
It is a continuation-in-part of U.S. patent application Ser. No. 08 / 587,406, filed Jan. 17, 996, pending. As used herein, the term "magnetic material" applies to magnetized bodies, iron bodies, and other bodies with low magnetic reluctance that have a tendency to change the surrounding magnetic field.

[0002]

BACKGROUND OF THE INVENTION U.S. Pat. No. 5,442,283, issued Aug. 15, 1995, describes an integrated circuit Hall voltage proximity detector employing a peak reference threshold detector for Hall signals. The integrated circuit chip is mounted on the poles of a magnet. A peak-based threshold type signal detector tracks the slope of the Hall voltage (e.g., corresponding to the approach of a passing gear tooth) and (e.g., corresponds to the approach of a valley between two gear teeth). The subsequent peak voltage is temporarily held before generating an output signal indicating the onset of the subsequent Hall voltage gradient in the opposite direction.

In the above patent, the Hall voltage holding circuit comprises a capacitor and means for controllably leaking charge from or to the capacitor to prevent false tripping of the comparator providing transitions in the binary output signal. Including. Thus, the holding voltage of the capacitor has a drop in the loss of maintaining accuracy as the speed of passage of the gear teeth slows, and thus the detector is capable of accurate detection Has the minimum speed of the gear teeth. Capacitors used in automobile engine compartments are typically required to operate over a temperature range of -40C to 170C. US Patent No. 5,44
When a peak reference threshold detector of the type described in U.S. Pat. No. 2,283 is so used, its associated peak holding capacitor is provided to prevent missed correct cylinder firings at start-up (start of crank). Must have a very high leakage resistance. Even with such expensive capacitors,
Missing one or two of the first ignitions will occur.

Many prior art proximity detectors produce a high binary output voltage that indicates the approach and proximity of a passing object, and a low binary voltage when the object is farther from the detector. The signal detector is usually a threshold detector based on an intermediate signal, or of a type sometimes referred to as just an intermediate signal detector type, in which a low-to-high transition in the detector output voltage is , Typically triggered by a comparator that determines when the transducer voltage rises (or falls) to a fixed internal threshold voltage referenced to a voltage level corresponding to the median or average value of the Hall signal. Alternatively, in the case of the peak-referenced threshold detector in that patent, a detector output transition occurs when the transducer voltage peak has just occurred and the transducer signal voltage has dropped from the peak value by an amount equal to the predetermined threshold voltage.

Proximity detectors having a fixed threshold voltage generate a low-to-high (or high-to-low) binary transition in the output signal that indicates the approach of a magnetic object. In practice, the closest transit distance (sometimes called the air gap) does not remain constant.

[0006] Variations in air gap size cause a shift in the actual distance of approaching and moving objects, with the transducer voltage exceeding or falling below a fixed threshold. This results in the lack of accuracy in detecting passage may preclude their use as position detectors for passage objects such as cams and gear teeth.

[0007] Changes in the air gap between the pass-through to be detected and the transducer can affect the mechanical and electrical properties of the detector, as well as the pass-through properties, especially as a function of temperature.

[0008] Other sources of inaccuracies are that the gear teeth (magnetic material) have different ferromagnetic properties from tooth to tooth, and / or that undulating changes in the spacing (gap) of the gear teeth with respect to the detector. When it is caused by the eccentricity of the gear, the amplitude of the Hall voltage changes. Also, temperature changes cause changes in the size of the air gap and changes in the sensitivity of the transducer and the transducer voltage amplifier.
Whether detected by sensing Hall voltage peaks or by using a voltage threshold criterion to indicate the approach of a pass-through, changes in the median amplitude of the transducer voltage reduce the accuracy of position detection. This is because the Hall signal is not centered within the dynamic range of the Hall signal detector.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a proximity detector having a magnetic field to voltage transducer and automatically centering the transducer output voltage within the dynamic range of the transducer signal detector. It is in. It is another object of the present invention to provide automatic gain control and a peak-to-threshold type capacitorless transducer signal detector within the dynamic range of the transducer output voltage to provide excellent detection accuracy at zero speed. Combining automatic centering.

[0010]

Proximity detection method for detecting a magnetic substance which passes SUMMARY OF THE INVENTION includes the steps of sensing the ambient magnetic field, generating a voltage V _H having an amplitude directly related to the magnetic field, the V _H Generating an amplified voltage Vsig at the output of the amplifier applied to the input of the amplifier. It is also provided with a signal detector to which Vsig is applied, wherein the signal detector is one at Vsig.
A binary proximity detector output voltage V having one polarity transition each time the one polarity trajectory reaches a predetermined point therein
Generate out. Source of DC offset limit voltage V _A and V _B corresponding to the positive and negative limits of the dynamic range of the detector is provided. At the output of the amplifier, when the median voltage Vos is greater than V _A of Vsig, the entire signal Vsig is moved in the negative direction, and when the median Vos of Vsig is less than V _B, the entire signal Vsig positive is moved in a direction, kept between the for Vos within the dynamic range of the detector, that is, from V _B to V _a.

The median voltage Vos is determined by continuously generating one reference voltage V _P2 equal to the positive going trajectory of the most recent peak at Vsig and to the negative going trajectory of the most recent peak at Vsig. By continuously generating another equal reference voltage V _N2 , the median value Vos is further reduced by about 10% of the center of the voltage range between V _P2 and V _N2.
Generated within.

[0012] In yet another method, the movement of the signal Vsig is such that during the interval when Vos is greater than V _A , Vout is shifted during the interval.
By counting at least one polarity transition at Vout and generating a digital signal to apply a negative compensation offset bias voltage to Vsig by one predetermined negative bias increment at each polarity transition at Vout. and Vos counts transitions of at least one polar in Vout during intervals when less than V _B, and only one predetermined positive bias increment at each transition of one polarity in Vout positive compensation offset bias voltage By generating a digital signal to add to Vsig.

The method of the present invention also includes an automatic gain control (AG) wherein the amplifier is a digitally gain controlled amplifier.
C) may be included. Comparing the amplitude of the trajectory of at least one polarity in Vsig with a predetermined target value _VTG; and changing the binary value from one binary level to another binary level every time the Vsig exceeds the target value. Generating the signal Vbig, applying the binary signal Vbig to a digitally gain controlled amplifier, and digitally controlling the gain when Vbig changes from one binary level to another binary level. An additional step of changing the gain of the amplifier by one predetermined gain increment in a direction that brings the peak value at Vsig just below a predetermined target value is added. Finally, a binary proximity detector output voltage V with one polarity transition each time a one polarity trajectory in Vsig reaches a predetermined point therein.
out is generated.

When the above-mentioned AGC feature is included in the present invention, the step of changing the gain of the amplifier includes the step of:
clocking the incremental change in gain by a transition at out, whereby the speed at which the gain can be changed is directly related to the speed at which the magnet is passing. this is,
Limit the speed at which the gain adjustment can be made, and guarantee a rate of gain change that is less than the rate of gain change that would lead to a large change at that point in the continuous trajectory at Vsig where proximity detection is performed. It is advantageous for In other words, the "jitter" at the timing of the transition in the binary output signal Vout from the detector will be less.

Similarly, the automatic offset adjustment feature of the present invention may include the step of clocking the incremental change in gain at the transition at Vout so that the offset adjustment rate is only incrementally at each transition at Vout. Change, so that the change at that point in the continuous trajectory in Vsig at which the proximity detection takes place is kept small again. The result is higher proximity detection accuracy and less jitter on transitions in the detector output signal.
Preferably, the signal detector is a peak reference threshold detector that retains at least one polarity peak until the signal drops from each peak by a predetermined threshold voltage value defining a predetermined point in Vsig.
A feature of the automatic offset control of the present invention is that it provides the largest possible Hall signal within the dynamic range of the Hall signal detector, leading to unprecedented accuracy in proximity detector accuracy, even at magnetic object speeds down to zero. Make it possible.

[0016]

DETAILED DESCRIPTION OF THE INVENTION The Hall element 10 of FIG. 1 has an output connected to the input of a Hall voltage amplifier 12. The Hall element 10 may be attached to a magnetic pole of a magnet (not shown), so that when an iron object approaches, the Hall voltage V
_H , and thus the amplified Hall voltage Vsig increases (or decreases). As the object moves away, _VH and Vsig decrease (or increase depending on the polarity of the magnetic poles of the magnet). Alternatively, the detector circuit of FIG. 1 may be used to detect magnetic material that is itself magnetized, in which case the Hall element need not have a magnet attached.

A magnetoresistor bridge (not shown) can be used instead of a Hall element. And, two Hall elements whose outputs are differentially connected to the inputs of a Hall voltage amplifier (not shown) represent a second alternative magnetic field to voltage transducer. Amplified Hall voltage Vsig
Is processed by the remaining circuitry in the proximity detector of FIG. 1 to generate a square wave proximity detector output signal Vout that represents the contour of the pass-through, such as a shaded graph. The amplified Hall voltage Vsig is applied to the positive input of the first comparator 14, passes through the AND gate 15, and is applied to the positive input of the second comparator 16. Amplified Hall voltage Vsig
Is also connected to the negative input of another first comparator 24 and to another second
Is applied to the positive input of the comparator 26.

As a starting point, counter 17 is at zero count and when the output of first comparator 14 goes high,
Counter 17 begins counting clock pulses from clock 18. The resulting count is provided to a digital-to-analog converter (PDAC1) 20 which outputs an output analog voltage V _{P1 that} is always somewhere in the range from zero to the DC supply voltage + Vreg. Generate In any moment the amplitude of V _P1 is a positive linear function of the count signal from the counter 17. When power is first applied to the detector circuit, a logic block (not shown) senses when the DC supply voltage + Vreg is turned on and resets the circuit's counter to a zero count. Comparator 14 has hysteresis and is therefore a Schmidt-type comparator. The output of DAC 20 (PDAC1) is connected to the negative input of comparator 14 so that Vsig
Is (voltage V _P1 ) + (small hysteresis of comparator 14)
Whenever it exceeds the threshold voltage, the output of comparator 14 goes high. If Vout is low at that point, the output of AND gate 15 goes high and counter 17 is enabled and counts. When Vsig grows more positive, V _P1, as illustrated in Figure 2, it is caused to so track the Vsig stepwise. The vertical trajectory of the stepped V _P1 increment is Vreg / 2 ⁿ
Where n is the number of bits in the DAC. Horizontal time delta _t1 increments, increases as the slope of Vsig is reduced.

As shown in FIG. 2, when the peak positive voltage of Vsig is reached, the counter 17 starts counting at time t.
stops at _pp1, V _P1 holds this peak voltage until time t _ppk. At time _tppk , Vsig is the held voltage V _P1
4 drops by an amount Vhys equal to the threshold of comparator 16 and the output of comparator 16 goes high to temporarily set flip-flop 33, so that Vout is
Go from low to high as seen in. Vout is applied through the delay circuit 29 to the reset input of the counter 17, the time t _ppk (Figure 5) to reset the count in counter 17 to zero hold the reset state as long as the reset signal V _{Pre The set} is high I do. Thus, V _P1 also remains at zero volts for the above time. In subsequent positive pulse in the signal Vsig, V _P1 begins to track to its peak and the subsequent positive pulse again, to hold the new peak voltage. The reset signal (FIG. 6) resets the counter 27 at time t _npk and holds the reset state as long as the reset signal V _Nreset is high.

The lower (N) circuit portion of the proximity detector of FIG. 1 essentially reflects the configuration of the upper (P) portion just described. The lower circuit portion processes the negative pulse at Vsig in the same way as the upper portion does for the positive pulse at Vsig. For example, as shown in FIG. 3, when the peak negative voltage of Vsig is reached,
The counter 27 stops counting at time t _np1 ,
V _N1 holds this peak voltage until time t _npk . At time t _npk , Vsig is set to the value of comparator 2 from the held voltage V _N1.
The output of comparator 26 goes high to reset flip-flop 33, and Vout goes from high to low as seen in FIG. 4, rising by an amount Vhys equal to the threshold of six.

Some of the aforementioned proximity detectors of FIG. 1 operate in a peak-based threshold detection mode. Such a detector is known under the title “DETECTION OF P
ASSING MAGNETIC ARTICLES
AT SPEED DOWNTO ZERO ", a patent application Serial No. 08 / 587,405. The above patent application was assigned to the same assignee as the present application and was filed at the same time. That patent application describes the proximity detector circuit and operation in more detail and is incorporated herein by reference.

The rest of the circuit in FIG. 1 relates to the circuit relating to the automatic gain control circuit of the Hall voltage. The count signals from counters 17 and 27 are also supplied to PDAC2 44 and NDAC via latches 42 and 52, respectively.
254 respectively. P-latch 42 and N-latch 52 are _enabled by signals V _Platch (FIG. 8) and V _Nlatch (FIG. 7) from one-shot generators 41 and 51, respectively.

The one-shot generators 41 and 51 are triggered by a low-to-high transition on signal Vout and a high-to-low transition (FIG. 4) at Vout, respectively. PDAC2 44 and NDAC2 54
The output signal V _P2 and V _N2 from each is shown in FIG. 9 so that they are associated with each other and Vsig, Vo
ut is drawn to the same scale in FIG. To repeat the point here, the outputs of comparators 24 and 26 go high only when Vsig goes negative. Thus, only when Vsig is going negative, the AND gate 25, counter 27, NDAC1 30, N latch 52, NDAC2
There is a change in the state of the signals of 54, buffer 58 and window comparator 56. The upper (P) and lower (N) portions of the circuit share the clock 18 and reset delay circuit 29. Referring to FIG. 3, this tracking of Vsig begins at the time _tppk at which a low-to-high transition at Vout occurs.

The counters 17 and 27 count only upward. DC reference voltage + Vreg and ground are NDA
PDAC1 for C1 30 and NDAC2 54
When the count of counter 27 goes up, the output V _{N1 of} NDAC1 30 goes down as seen in FIG. 3 as 20 and their connections to PDAC2 44 go up. However, if the counter 27 is of the type that counts down from the maximum count, the PDA
Like C 20 and 44, both NDACs 30 and 54 may be connected to a DC reference voltage. Counter 1
7 and 27 are counter overflows (an) that prevent wrapping of the counts when the maximum count is exceeded.
ti-overflow).

The signals V _P2 and V _N2 are applied to two inputs of a fixed gain differential amplifier 60 via buffer stages 48 and 58. The output signal V _PP of the differential amplifier 60 is V _P2 and V _P2.
N2, which is essentially Vsig
Equals the peak-to-peak value of As Vsig grows, it is tracked by V _PP as seen in FIG. Signal V _PP is applied to one input of comparator 62.
A reference voltage V _TG is applied to the other input of comparator 62.
When V _PP exceeds V _TG , the output signal V _{to obig} of the comparator 62
Is at the high binary level. If V _PP is less than V _TG ,
V _toobig is at the low binary level. The Hall voltage ( _VH ) amplifier 12 comprises a fixed gain amplifier stage 65, a programmable gain amplifier comprising a digital-to-analog converter G-DAC 67, two resistors 71 and 73 and an operational amplifier 69, and an operational amplifier 75. , Three resistors 7
Includes a step-adjustable gain amplifier consisting of 7, 79 and 81 and a switch 83, and an automatic offset adjustment circuit. The automatic offset adjustment circuit includes a DAC 170 connected to a voltage divider, an up / down counter 171,
Voltage divider network consisting of resistors 172, 173, 174 and 175, two Schmitt comparators 177 and 17
8, a voltage divider consisting of resistors 180 and 181, and a differential amplifier 183.

The counter 85 is an up counter that does not wrap after reaching the maximum count.
It has a counting output connected to AC 67. Signal Vou
t is inverted by the inverter 87, and the counter 85 counts positive transitions in the inverted signal Vout. G-DAC 67 is internally connected as a digitally programmable resistor having a maximum resistance when the input count to the DAC is zero. G-DA
A resistor 71 in parallel with C 67 sets the overall input resistance to operational amplifier 69 to the highest value at zero count, which sets the gain of operational amplifier 69 to the lowest value.

When the first positive and negative trajectories in Vsig generate a signal V _PP1 that is lower than the reference voltage V _TG (FIG. 9), the signal V _toobig is low (FIG. 11) and _causes the counter 85 to invert NOR. Enable through gate 89. The counter 85 responds by counting up by one at the next positive transition in the inverted signal Vout, as shown in FIG. This results in a single increment of gain increase, which is illustrated in FIG. 9 where V _PP1 grows to V _PP2 and Vsig is t ₁
Its amplitude in the period leading up to t ₂ is increased slightly from.
This process of testing the amplitude of (V _PP , and thus Vsig) against the target reference value V _TG and adjusting the gain upward by one increment when the target has not yet been reached, reduces the peak-to-peak amplitude of Vsig to the target. Required to set the value V _TG ,
Continue for many periods in Vsig (and Vout).

When the target value is reached or exceeded, V
_toobig goes high (FIG. 11), where the counter 85 thus disabled does not count further as shown in FIG. 12, and the gain of the amplifier is then reduced (detector is turned off and turned on again). until the start) (e.g., between times t ₃ and t ₄ in FIG. 9) remains fixed. However, when the first positive and negative trajectories in Vsig generate a signal V _PP1 (FIG. 9) higher than the reference voltage V _TG , the signal V _{toobig causes} the counter 85 to invert NOR.
High to disable via gate 89 and to hold the D input of flip-flop 91 high.

The counter 93 is a serial type counter.
Note that the serial counter provides one output whose signal is low until the counter counts two (more generally several) positive trajectories in the inverted signal Vout, at which point The output of inverter 87 goes high and clocks through the high at the D input of flip-flop 91 to the Q output of the flip-flop. This clocking of the high signal through flip-flop 91 occurs when the non-inverted signal Vout (FIG. 10) goes low. After the first two periods at Vsig, switch 83
Closes to connect the feedback resistor 81,
The feedback resistor 81 reduces the gain of the operational amplifier 75 and the amplifier comprising resistors 77 and 79. For example, the gain of the operational amplifier may be reduced by a factor of four, and thus the gain of the Hall voltage amplifier 12 may be reduced by a factor of four.

Thus, the transducer voltage Vsig
During the first two positive pulses at Vsig, it is determined whether the peak-to-peak voltage of Vsig (V _PP ) is too large relative to the target reference voltage V _TG . If the peak-to-peak voltage (V _PP ) of the Vsig is not too large, the G counter is _enabled (by signal V _toobig ) and the G-DAC 6
The resistance value of 7 begins to fall immediately, and the gain of its countable gain stage rises to the target value and then remains there. However, if during the first two positive pulses at the transducer voltage Vsig, the peak-to-peak voltage of Vsig (V _PP ) is determined to be too large relative to the target reference voltage V _TG , then after two pulses at Vsig,
The overall gain of the Hall voltage amplifier 12 is reduced by a factor of four, and the count controllable gain stage brings the peak-to-peak value of Vsig to the target value.

The counter 93 is a non-wrapped serial up counter. It only counts up and is not reset until deactivated and reactivated. The counter 93 has Vsig (or Vout)
Gives a second serial count output going high with a greater count of the 16 trajectories (pulses) at. The x16 output is low until count 16 is reached. The high output signal from the × 16 output of the counter 93 at the count of 16 is a G counter 8
5 and disabled at Vsig (eg, 16)
(E.g., negative going trajectory in Vsig and / or Vout) is a counter 8 to adjust the gain.
Limit what can be counted by five. Alternatively,
It would be equally effective to count the trajectories going positive.

The purpose of automatic gain adjustment for only a few initial pulses at Vsig, following turning on the supply voltage + Vreg and starting to detect passing objects, is based on the conditions at the start. The goal is to obtain an optimal transducer-to-voltage amplifier gain, and then maintain a constant gain to avoid an incremental shift in the actual distance of the approaching object at which the corresponding transition in Vout occurs. As gain changes occur, continuous and frequent shifts in the detected approach distance cause jitter in the transition of Vout. In the foregoing embodiment, the gain of the Hall voltage amplifier 12 is adjusted during the first 16 periods at Vsig (corresponding to the first 16 magnet passes), then held fixed, and then Provides a quick initial gain adjustment with no further adjustments. This feature
It is particularly suitable for proximity detectors used in combustion engine ignition systems where all adjustments in gain occur only during combustion engine crank initiation. The subsequent load of the combustion engine (loadin
g) and during operation, it is desirable to avoid any change in ignition timing that would occur as a result of a change in the amplitude of Vsig, so that the gain adjustment is completed just at the start.

In summary, just after two things have passed,
It is determined whether the signal is too loud, and if so,
The gain of the Hall voltage amplifier 12 is reduced by a large factor, a factor of four in this example. And the following 16
During the passage of an individual object, the gain is the transducer signal V _H
Is adjusted upward based on the maximum of the peak amplitude at, so that the maximum peak amplitude is at a predetermined target value. This target amplitude is just inside the dynamic range of the Hall voltage amplifier 12 to avoid clipping the signal, while at the same time,
Giving a peak just below the target value V _TG large signal Vsig, to enhance accurate detection. DAC 67 acts essentially as a digitally controllable resistor and may use a well-known 2R / R type DAC connected as shown in FIG. Each of the three resistors shown at the top of FIG. 13 has a resistance value R, while the other four resistors have a resistance value of 2R. The corresponding external leads of DAC 67 are shown in FIG.
3 and the DAC 67 illustrated by the blocks in FIG.

The lead 161 is grounded while the lead 16
2 and 164 are connected to the output of the first Hall voltage amplifier 65 and the input of the operational amplifier 69, respectively.
The four switches 151, 152, 153 and 154 are
Represents electronic switches to which are connected four digit count signals D ₀ , D ₁ , D ₂ and D ₃ from a gain counter (eg, 85). Switches 151, 152, 153 and 154 are shown where all four digits in the input count signal are high and the resistance between leads 162 and 164 is at a minimum. Resistor 71 reduces the minimum resistance of the paralleled combination at the input of the operational amplifier, but more importantly reduces the maximum input resistance of the operational amplifier, ie, the maximum R _in . When grounded, GD
AC 67 becomes a digitally controllable voltage divider,
The effective resistance between conductors 162 and 164 is R
Is sufficiently large so that when the resistance between terminals 161 and 162 is much greater than the output impedance of Hall voltage amplifier 65, it is essentially a linear function of the digital count for G-DAC 67. Thus, amplifier gain is a linear function of the count.

The operation of the automatic offset adjustment circuit is as follows. Voltage divider resistors 180 and 181
It is connected between the outputs of both buffer amplifiers 48 and 58. Resistors 180 and 181 have equal values, the voltage Vos at the center of the the voltage divider is midway between the retained peak voltage of Vsig, i.e. V _P2 and V _N2.

The voltage V _A and V _B generated by resistors 172,173,174 and 175 of the divider Vreg /
There 2 equidistant, for example, when Vreg is 3 volts, V _A is 2.0 volts, and V _B is 1.0
It can be a bolt. Further, the voltages V _A and V _B of the voltage divider
_Are preferably (intermediate value Vm) ± (an amount corresponding to 1-bit increment voltage V _Db of DAC 170). This provides the tightest tolerances that can be achieved with a particular DAC 170 without hunting. For example, + Vreg is 3.0 volts,
DAC 170 is a 4-bit DAC, and Vm is V
If reg / 2, the median of Vsig is allowed to deviate from the range Vos ± 0.18 volts before automatic offset correction is performed. And V _A and V _B
Are set to Vm + V _Db and Vm−V _Db , respectively, at the voltage of the divider, and Schmitt comparators 177 and 17
The hysteresis of 8 may be zero.

When enabled, the up / down counter 171 is clocked and counts the negative trajectory in Vout. For example, Vos is Vm ± 0.18
When greater than volts, the output of Schmitt comparator 177 goes high and up / down counter 171 is enabled to count down, and similarly, when Vos is less than Vm ± 0.18 volts, the Schmitt comparator 177 is enabled. The output of unit 178 goes high and up / down counter 171 is enabled to count upward.
Thus, the midpoint voltage Vos in the signal Vsig is automatically kept within the range Vm ± 0.18 volts, which is V _H
, And any offset introduced by the components of the transducer voltage amplifier 12. Alternatively, the range of the automatically adjusted offset voltage at the output of DAC 170 is
83 may be centered at a voltage other than Vreg / 2 to maximize the headroom.

The waveforms of FIGS. 15 and 16 illustrate the operation of the automatic offset feature without automatic gain control. The offset voltage Vos is equal to the amount of one DAC bit (DAC 171).
Decreased in Vdb volts) only when t ₄ in, said time point t ₄ is the time when the peak reference threshold detector clocks the up-down counter 171, to generate a negative going transition in Vout. The ultimate intent is that the signal Vsig at the "offset" level, which centers the signal Vsig within the dynamic range of the detector, is applied to the transducer.
To provide input to the signal detector. To do so more accurately, for example, compensate for the asymmetric signal Vsig (acc
It may be necessary to set Vm out of Vreg / 2 and / or to set Vos away from the center of V _P2 and V _N2 . These deviations from the exact midpoint are, in effect, the power supply Vreg
Or the midpoint of Vsig peak-to-peak voltage V _PP does not exceed 25% of the dynamic range.

The title of the invention is "DETECTION OF
PASSING MAGNETIC ARTICLE
SAT SPEEDS DOWN TO ZERO "
It has been found by computer-generated models that proximity detectors of the type of peak reference threshold transducer-signal detector described in the above-referenced patent application can be advantageously merged with those of the intermediate signal detection type.

[0040] Such a detector has the invention name "DE
TECTION OF PASSING MAGNET
IC ARTICLES WHILE PERIODI
CALLY ADAPTING DETECTION
THRESHOLDS TOCHANGING AMP
LITUDE OF THE MAGNETICFIE
LD ", assigned to the same assignee as the present application, and filed on January 17, 1996, Serial N
o. 08 / 587,407.

The peak reference threshold signal detector comprises:
A peak reference threshold signal detector that is advantageously merged with an intermediate signal detector in computer modeling simulation, and thus can operate down to zero speed, can operate in peak reference threshold mode for a short initial interval after initiation The detector then automatically went into a detection mode based on the intermediate signal-threshold. In addition, automatic gain control features that can operate down to zero speed include a slope activated (slope) to initially set the gain and Vsig levels.
-Activated) detector was incorporated. The automatic gain control was subsequently stopped to avoid a further step function gain shift, which is prone to jitter and instability at magnetic object approach and away detection distances. The method of automatic gain control of the present invention essentially eliminates such an initialisation in such a merged proximity detector due to its fast gain adjustment and its undiminished detection efficiency at very low speeds. Well suited for use.

Many variations on the proximity detector of the present invention are now apparent, some of which are as follows. During tracking of the positive slope of Vsig by V _P1 by the proximity detector of FIG. 1, comparator 14, clock 18, counter 1
7 and PDAC 120 together serve as a generator of a digital count signal at the output of counter 17, tracking a digital signal, ie, Vsig. This digital signal generator is a digitizer of the analog signal Vsig or an analog / digital converter.

Similarly, during tracking by V _N1 , comparator 2
4, clock 18, counter 27 and NDAC1 30
Work together as an analog-to-digital converter that produces a digital signal, a digital count signal at the output of counter 27, which tracks the negative going trajectory of Vsig.

In the proximity detector of the present invention, the digital / analog converter can be formed by circuit means other than the circuit means shown in this specification. For example, G-
Digital gain controllable amplifiers based on the use of a DAC 67 may alternatively have a group of parallel connected branches, each including a resistor and a binary signal controllable switch, G-
It may be based on a prior art digital gain controlled amplifier that replaces the DAC. It is further possible to use only one up / down counter (instead of up counters 17 and 27) that counts up and down in response to a high binary signal from each of comparators 14 and 24. In this case, only one DAC, for example PDAC
120 may be used with outputs connected to the positive and negative inputs of comparators 16 and 26, respectively. In this case, V
It is necessary to disable comparator 16 when tracking a negative trajectory in sig, and to disable comparator 26 when tracking a positive trajectory in Vsig. The circuit portion of FIG. 1 for generating signal V _toobig then latches the up / down counter output to latch 42.
And 52, and enable these latches during each of the count-up and count-down, for example, by using the signal Vout as the latch enable signal.

As mentioned above, the purpose of performing automatic gain adjustment on only the first few pulses in Vsig is to avoid an incremental shift in the actual distance of the approaching object, where the corresponding transition in Vout occurs. That is. In applications such as ignition distributors, the timing of ignition of the engine tends to cause small but annoying jumps in engine shaft power delivery. However, when detection accuracy is a top priority consideration, the counter 93 (FIG. 1) may be cycled periodically, eg, every minute, or a predetermined number of detected objects to allow for occasional readjustment of the gain. It is easily possible to reset after passing through.

Of course, continuous gain adjustment is another option, for example, in the detector of FIG.
_And by directly connecting the V _toobig signal to the enable input of the counter 85. The output voltage Vsig of the Hall amplifier may be considered as the output of a magnetic field to voltage transducer, which includes a Hall element. The above AGC is performed by controlling the gain of a digitally controlled Hall amplifier that can be considered part of the transducer. Alternatively, it is possible to digitally control the excitation current in the Hall element to perform the AGC of the composite transducer, for example, by using a digitally controlled voltage regulator used to energize the Hall element.

[Brief description of the drawings]

FIG. 1 shows a block diagram of a magnetic substance proximity detector according to the present invention.

FIG. 2 shows the waveform of a Hall (transducer) voltage signal during the passage of four magnetics superimposed on the waveform of the output voltage signal from PDAC1.

FIG. 3 is an output voltage signal V from NDAC1 in FIG. 1;
The partial waveform of _N1 is shown and is depicted on the same time scale as FIG.

4 shows the waveform of the output voltage Vout of the proximity detector of FIG. 1 and is drawn on the same time scale as FIG.

FIG. 5 shows the waveform of a reset signal for a counter 17 in the proximity detector of FIG. 1 and is drawn on the same time scale as FIG.

FIG. 6 shows the waveform of a reset signal for the counter 27 in the proximity detector of FIG. 1 and is drawn on the same time scale as FIG.

FIG. 7 shows the waveform of the latch enable signal for the N latch 52 in the proximity detector of FIG. 1 and is drawn on the same time scale as FIG.

FIG. 8 shows the waveform of the latch enable signal for the P-latch 42 in the proximity detector of FIG. 1 and is depicted on the same time scale as FIG.

FIG. 9 shows the waveform of a Hall (transducer) voltage signal during the passage of several magnetic objects, along with the corresponding output signals V _P2 and V _N2 from PDAC2 and NDAC2 in the proximity detector of FIG. 5 shows a superimposed waveform.

FIG. 10 shows the corresponding waveform of the output voltage Vout of the proximity detector of FIG. 1, drawn on the same time scale as FIG.

FIG. 11 shows the waveform of the corresponding output signal V _toobig of the comparator 62 in the proximity detector of FIG. 1 and is drawn on the same time scale as FIG. 9;

12 shows the corresponding waveform of the binary output voltage from the first two bits in the proximity detector gain counter (G-counter) 85 of FIG. 1 and is depicted on the same time scale as FIG.

FIG. 13 shows an R / 2R digital / analog converter (DA)
The circuit diagram of C) is shown.

FIG. 14 shows a block diagram of the DAC 67 of the drawing connected as digitally controllable registers, such as may be used as the G-DAC 85 in FIG.

FIG. 15 shows the waveform of a Hall (transducer) voltage signal in the proximity detector of FIG. 1 without AGC during passage of several magnetic objects, on which the corresponding waveform of the offset level signal Vos is shown; Are superimposed.

16 shows a Vout waveform drawn on the same time scale as the waveforms Vsig and Vos in FIG.

[Explanation of symbols]

 Reference Signs List 10 Hall element 12 Hall voltage amplifier 14, 16, 24, 26, 62 Comparator 17, 27 Counter 177, 178 Schmidt comparator 67 G-DAC

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Ravi Big Longview Drive, New Hampshire, United States 03304, Bo 27 (72) Inventor P. Carl Scheller, New Hampshire, United States 03867, Rochester, Ten Rod Ro De 709 (72) Inventor J.M.Town, New Hampshire, United States 03255, Southbrook Circle, Newbury 12, 12 (72) Inventor Terri Eltou, New Hampshire, United States 03304, Baw, Clough Street 15

Claims (7)

[Claims] 1. A proximity detection method for detecting a passing magnetic object, comprising: a) sensing an ambient magnetic field, generating a voltage V _H having an amplitude directly related to the magnetic field, and applying V _H to an input of an amplifier. Applying and generating an amplified voltage Vsig at the output of the amplifier; b) providing a signal detector to which Vsig is applied, wherein the detector has a predetermined polarity trajectory in Vsig therein. Generating a binary proximity detector output voltage having one polarity transition each time a point is reached; c) a DC offset limit voltage V, each positive and negative from the center of the dynamic voltage range of the detector. _Providing a source of _A and V _B , d) at the output of the amplifier, when the median voltage V s of V sig is greater than V _A , move the entire signal V sig in the negative direction; Median Vos is V
Is smaller than _B, moving the entire signal Vsig in a positive direction, proximity detection method comprising the steps of keeping Vos within the range from V _B to V _A. 2. a) continuously generating one reference voltage V _P2 equal to the positive going trajectory of the most recent peak at Vsig; b) equal to the negative going trajectory of the most recent peak at Vsig. 2. The method of claim 1, further comprising: continuously generating another reference voltage V _N2 ; and c) generating a median voltage Vos substantially at the center of a voltage range between V _P2 and V _N2 . Proximity detection method. 3. The step of moving the entire signal Vsig comprises: counting at least one polarity transition in Vout during the interval when Vos is greater than _VA ;
At each transition of one polarity at t, the negative compensating offset bias voltage is increased by one predetermined negative bias increment to Vs
and generating a digital signal for application to ig, when Vos is less than V _B, counts the transitions of at least one polar in Vout during intervals and Vou
At each transition of one polarity at t, the positive compensation offset bias voltage is increased by one predetermined positive bias increment to Vs
generating a digital signal for addition to the ig. Wherein an amplifier wherein the amplifier is gain controlled to digital, a) comparing the amplitude of at least one polar trajectory to a predetermined target value V _TG in Vsig, b) Vsig is the target value , The binary signal Vbig changes from one binary level to the other binary level every time
C) applying the binary signal Vbig to the digitally gain-controlled amplifier and, when Vbig changes from one binary level to the other binary level, the peak value at Vsig Changing the gain of the digitally-gain-controlled amplifier by one predetermined gain increment in a direction that results just below the predetermined target value. 5. The method according to claim 1, wherein said signal detector is a type of threshold signal detector based on peaks, so that each peak of one polarity equals a predetermined threshold value with a difference between the peak value and Vsig at said point. After the trajectory, one polarity transition at Vout from the signal detector is V
The proximity detection method according to claim 1, wherein the proximity detection occurs at the point in sig. 6. The proximity detection method according to claim 1, wherein the median value Vos of Vsig at the output of the amplifier is the latest voltage level centered between the positive peak and the negative peak of Vsig. 7. The signal detector detects that the signal is Vsig.
2. The proximity detection method according to claim 1, wherein the threshold detector is a threshold detector based on a peak that holds at least one polarity peak until the peak retreats by a predetermined threshold voltage value defining the predetermined point.