JPH10320919A - Digital signal processing method and digital signal reproducing apparatus - Google Patents

Abstract

(57) [Summary] [Problem] To perform high-precision binary discrimination by reducing the occurrence of errors due to the influence of noise. A Nyquist equalized signal Seq is obtained from a reproduced signal Sa by an equalizer. The signal Seq is converted to the digital signal Sf
And an EPR4 equalized signal SEPR is obtained and supplied to the identification circuit 60. An EEPR4 equalized signal SEEPR is obtained and the identification circuit 80 is obtained.
To supply. The comparator 11 obtains a binary signal Sb from the signal Seq. The synchronization circuit 12 generates a synchronization signal Ss having either a predetermined phase or a one-clock delay, and the differentiation circuit 50 generates signals UT and DT indicating rising and falling of the signal Ss. Is supplied to the cycle detection circuit 70. A circuit 60 generates a binary signal TEPR from the signal SEPR, and a circuit 70 determines a waveform pattern based on the signals UT and DT. Using this waveform pattern, the circuit 80 obtains the binary identification signal Sg from the signal SEEPR. High-precision identification is performed using information of a waveform including intersymbol interference.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal processing method and a digital signal reproducing device. More specifically, the reproduction signal obtained by reproducing the recording medium on which the digital signal is recorded is provisionally identified, and the phase of the change point is limited to either the correct phase or the phase delayed by a predetermined amount, and the obtained change is obtained. For example, the EPR4 equalized signal obtained by processing the reproduced signal is identified based on the phase of the point, and the phase of the change point before and after the target identification change point is determined from the identification result.
Further, the period of the signal obtained by identifying the EPR4 equalized signal is detected, and the waveform pattern is limited from the detected period. This waveform pattern and the EEPR4 equalized signal obtained by processing the reproduced signal, for example, , A highly accurate binary identification signal is obtained.

[0002]

2. Description of the Related Art Conventionally, in a magnetic recording / reproducing apparatus and an optical disk apparatus, various methods have been proposed for binary identification of a reproduced signal obtained by reproducing a recording medium on which a digital signal is recorded.

For example, in a method called integral detection, FIG.
As shown in FIG. 6, the reproduction signal Sa is supplied to an integral equalizer 10 composed of a cosine equalizer or the like. In the integral equalizer 10, the reproduced signal Sa is processed so as to satisfy a condition called the Nyquist condition so as to have a characteristic as shown in FIG. 17, thereby suppressing intersymbol interference. This integral equalizer 10
The Nyquist equalization signal Seq obtained by performing the equalization processing in is supplied to the comparator 11. FIG. 18 shows an eye pattern of the Nyquist equalization signal Seq. When the recording signal WS is as shown in FIG. 19A, the Nyquist equalization signal Seq is as shown in FIG. 19B.

The comparator 11 determines whether the signal level of the Nyquist equalization signal Seq is on the positive side or the negative side, and generates a binary signal Sb as shown in FIG. 19C. This binarized signal Sb is transmitted to the synchronization circuit 12 and the PLL (Phas
e Locked Loop) circuit, and is supplied to a phase comparator 21 of a clock generation circuit 20 configured.

A clock signal C from a voltage controlled oscillator (VCO) 22 is supplied to a phase comparator 21 of the clock generation circuit 20.
LK is supplied, the phase of the binary signal Sb is compared with the phase of the clock signal CLK, and an error signal PD indicating a phase difference is provided.
Is supplied to the voltage controlled oscillator 22 via the integrator 23. Therefore, in the voltage controlled oscillator 22, the error signal PD
19D, the frequency of the clock signal CLK is controlled, and the phase of the falling edge of the clock signal CLK is made equal to the edge of the binary signal Sb, for example, as shown in FIG. 19D. The clock signal CLK having the same phase as the binary signal Sb generated by the clock generation circuit 20 in this manner.
Is supplied to the synchronization circuit 12.

In the synchronization circuit 12, the clock signal C
The binarized signal Sb is latched based on LK, and FIG.
As shown in E, a binary identification signal Sc synchronized with the rising edge of the clock signal CLK is generated.

If amplitude equalization is performed for binary identification by this integration detection method, a low-frequency noise component is considered to have an emphasized low-frequency component, and an error may occur due to the low-frequency noise. Therefore, low-frequency components are not required.
A method called amplitude detection is also used as a value identification method.

In the amplitude detecting method, a reproduced signal Sa is supplied to an integral equalizer 10 as shown in FIG. The integration equalizer 10 and a comparator and a clock generation circuit, which will be described later, are the same as those of the integration detection method, and the description is omitted.

The Nyquist equalized signal Seq obtained by the integral equalizer 10 is compared with a comparator 11 and a PR (1, -1) equalizer 30.
Supplied to The PR (1, -1) equalizer 30 is a filter having the characteristic of "1-D (subtract the signal one clock before from the current signal)". The intersymbol interference of the signal eq is suppressed by the device 30. The signal S (1-D), which is a signal in which intersymbol interference is suppressed, has a characteristic in which a high frequency band is emphasized as shown in FIG. PR
The signal S (1-D) obtained by the (1, -1) equalizer 30 is supplied to the non-inverting input terminal of the comparator 31 and the inverting input terminal of the comparator 32. This signal S (1-D) is a ternary signal, and the eye pattern is shown in FIG. When the recording signal WS is as shown in FIG. 23A, the signal S (1-
D) is as shown in FIG. 23B.

The inverting input terminal of the comparator 31 is connected to the connection point between the resistor 33 and the resistor 34, and is obtained by dividing the positive power supply voltage + V and the negative power supply voltage -V by the resistors 33, 34 and 35. The supplied threshold voltage Vthu is supplied. Similarly, the non-inverting input terminal of the comparator 32 is connected to a resistor 34
And the connection point of the resistor 35 and the positive power supply voltage +
A threshold voltage Vthl obtained by dividing V and the negative power supply voltage -V by the resistors 33, 34, 35 is supplied.

For this reason, the comparator 31 outputs the signal S (1
-D) is compared with the threshold voltage Vthu to generate a signal CU indicating that the signal S (1-D) is higher than the threshold voltage Vthu as shown in FIG. 23C. This signal CU is supplied to the J input terminal of the JK flip-flop 36. Similarly,
In the comparator 32, the signal S (1-D) and the threshold voltage Vthl
Are compared to generate a signal CL indicating that the signal S (1-D) is smaller than the threshold voltage Vthl as shown in FIG. 23D. This signal CL is equal to the K of the JK flip-flop 36.
It is supplied to the input terminal.

A clock signal CLK shown in FIG. 23E is supplied from the clock generation circuit 20 to the JK flip-flop 36, and the signal level of the J input terminal and the K input terminal of the JK flip-flop 36 at the timing of the clock signal CLK. Is generated and output as the binary identification signal Sd shown in FIG. 23F.

[0013]

By the way, in such an integral detection method, a large amount of low-frequency components is required. Therefore, in a magnetic recording / reproducing system in which a DC component cannot be reproduced, the low-frequency components are excessively emphasized. As a result, low-frequency noise such as crosstalk becomes a problem.

In the amplitude detection method, the signal S (1-D) obtained by processing the reproduced signal Sa by the integration equalizer 10 and the PR (1, -1) equalizer 30 is a ternary signal. For this reason, if the level of the signal S (1-D) fluctuates, ternary identification cannot be performed correctly. For this reason, AG
Although a level change is prevented by providing a C (Automatic Gain Controller) or the like, a highly accurate binary identification signal cannot be obtained.

Further, a PRML (Partial Response Maximetric) using a partial response system for equalizing a reproduced signal and using Viterbi decoding which is a maximum likelihood decoding system for data detection.
An identification method called “mumLikelihood” has been put to practical use. However, in this method, partial response equalization is performed, and the most probable code sequence is obtained retrospectively in consideration of the intersymbol interference, and since the configuration is complicated and the processing of the feedback system is included. It is not suitable for decoding data at high speed.

Accordingly, the present invention provides a digital signal processing method and a digital signal reproducing apparatus capable of performing highly accurate identification with a simple configuration.

[0017]

According to the digital signal processing method of the present invention, a reproduced signal obtained by reproducing a recording medium on which a digital signal is recorded is provisionally identified and the phase of a change point is limited to a predetermined range. Then, based on the phase of the obtained change point, the signal equalized to a different equalization criterion is identified, and from this identification result, the phase of the change point before and after the identified change point of interest is determined, and more intersymbol interference is obtained. Limiting the waveform pattern that the partial response equalized signal can take,
A binary identification signal is obtained based on this waveform pattern.

Further, the digital signal reproducing device temporarily identifies a reproduced signal obtained by reproducing a recording medium on which the digital signal is recorded, and limits the phase of a change point to a predetermined range; First equalizing means for equalizing a signal to an equalization criterion for increasing inter-symbol interference;
A second identification unit that equalizes to an equalization criterion different from the first identification unit, a period detection unit that detects a period of the identification result of the second identification unit based on the identification result of the first identification unit, A second equalizing means for equalizing the signal obtained by the equalizing means to an equalization criterion for increasing inter-symbol interference, and a period limited by the identification result of the first identifying means and the period detecting means. And a third identification means for obtaining a binary identification signal based on the waveform pattern and a signal obtained by the second equalization means.

According to the present invention, the reproduction signal obtained by reproducing the recording medium on which the digital signal is recorded is provisionally identified, and the phase of the change point is either correct or delayed by a predetermined amount. Limited. EPR obtained by processing a reproduced signal, for example, based on the phase of the obtained change point
The four equalized signals are identified, the phase of the change point before and after the discrimination change point of interest is determined from the identification result, and the EPR4
The period of the signal obtained by identifying the equalized signal is detected.
The waveform pattern is limited from the detected cycle, and binary identification is performed based on this waveform pattern and, for example, an EEPR4 equalized signal obtained by processing a reproduced signal.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, provisional identification based on an equalization criterion of an integration system which is hardly affected by level fluctuation is first performed, and the phase of a change point (1 → 0 and 0 → 1) of a recording signal is determined by a predetermined phase. Is limited to within two clocks, that is, the identified signal has either a predetermined phase or a phase delayed by one clock.

Further, an equalized signal obtained by performing the provisional identification based on the equalization standard of the integration system is converted into a digital signal, and a predetermined operation is performed using the digital signal, for example, EPR4 (Extended Partial). A signal equalized to the equalization standard of Response 4) and EEPR4 (Extended EPR4) is generated.

Here, the peak phase of the EPR4 waveform indicates the change point of the above-mentioned recording signal, and the peak phase is narrowed down to two phases by the discrimination based on the equalization standard of the integration system. The peak phase is identified by detecting whether the phase is close to the peak phase.

Further, based on the obtained result, the signal equalized according to the EEPR4 equalization reference is identified, and a final identification result is obtained in consideration of the intersymbol interference caused by the identified peak phase. Things.

Next, a digital signal processing method and a digital signal reproducing apparatus according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a configuration of a main part of a digital signal reproducing apparatus. A reproduction signal Sa obtained by reproducing the recording medium is supplied to an integral equalizer 10 composed of a cosine equalizer or the like, and processed so as to have a characteristic satisfying the Nyquist condition. Interference is suppressed. The Nyquist equalized signal Seq obtained by performing the equalizing process by the integral equalizer 10 is supplied to the comparator 11 and the A / D converter 40.

Comparator 1 constituting first identification means
In step 1, it is determined whether the signal level of the Nyquist equalization signal Seq is on the positive side or the negative side, and a binary signal Sb is generated. This binarized signal Sb is supplied to a clock generation circuit 20 configured using a synchronization circuit 12 and a PLL circuit. The first identification means includes a comparator 11, a synchronization circuit 12, which will be described later, and a differentiation circuit 50.

The clock generation circuit 20 includes the phase comparator 21, the voltage controlled oscillator 22, and the integrator 23, as described above.
And the clock signal CL supplied from the voltage controlled oscillator 22
An error signal PD indicating the phase difference is generated by comparing the phase with K. The error signal PD is supplied to the voltage controlled oscillator 22 via the integrator 23, and the frequency of the clock signal CLK is adjusted so that the phase of the clock signal CLK generated by the voltage controlled oscillator 22 becomes equal to the phase of the binary signal Sb. Controlled. The clock signal CLK generated by the clock generation circuit 20 is supplied to the synchronization circuit 12 and an A / D converter 40 described later,
The (1 + D) filters 42 and 46, the (1-D ² ) filter 44, the differentiation circuit 50, the identification circuits 60 and 80, and the period detection circuit 70 are supplied.

In the synchronization circuit 12, the clock signal CLK
, The binarized signal Sb is latched, and the synchronization signal Ss
Is output to the differentiating circuit 50.

In the A / D converter 40, the clock signal CL
The Nyquist equalized signal Seq is converted into a digital signal Sf based on K and supplied to the (1 + D) filter 42.

The (1 + D) filter 42 constituting the first equalizing means has (1 + D) characteristics, that is, the current signal and the 1
It has the characteristic of adding signals before the clock, and a PR1 equalized signal SPR1 is obtained from the digital signal Sf. This PR1 equalized signal SPR1 is calculated based on equation (1). Note that “n” is used in the equation (1) and the following equation.
Indicates a sampling point (clock). SPR1 (n) = Sf (n) + Sf (n-1) (1) The PR1 equalized signal SPR1 thus obtained is represented by (1
-D ² ) is supplied to the filter 44. The first equalizing means includes the (1 + D) filter 42 and the following (1-
D ² ) A filter 44 is provided.

The (1-D ² ) filter 44 has the characteristic of (1-D ² ), that is, the characteristic obtained by subtracting the signal two clocks earlier from the current signal, and outputs the E1 signal from the PR1 equalized signal SPR1 to the E1 signal.
The PR4 equalized signal SEPR is obtained. This PR1 equalized signal SPR1 is calculated based on equation (2). SEPR (n) = SPR1 (n) -SPR1 (n-2) (2) The EPR4 equalized signal SEPR is obtained by the (1 + D) filter 46 as the second equalizing means and the second identifying means. It is supplied to a certain identification circuit 60.

The (1 + D) filter 46 has the characteristic of (1 + D), and converts the EPR4 equalized signal SEPR to the EEPR
A four equalized signal SEEPR is obtained. This EEPR4 equalized signal SEEPR is calculated based on equation (3). SEEPR (n) = SEPR (n) + SEPR (n-1) (3) The EEPR4 equalization signal SEEPR is supplied to the identification circuit 80.

The differentiating circuit 50 is configured as shown in FIG. 2. The synchronizing signal Ss is supplied to a delay unit 51 and an AND gate 52, and is logically inverted by an inverter 53 to output A.
The signal is supplied to the ND gate 55. The delay unit 51 delays the synchronization signal Ss by one clock. The synchronization signal Ss delayed by one clock is supplied to the AND gate 55 as the delay signal Scd, and is also logically inverted by the inverter 54 and supplied to the AND gate 52. Therefore, AN
From the D gate 52, a signal UT whose signal level is set to the high level “H” for one clock from the rise of the synchronization signal Ss is generated. Further, the AND gate 55 generates a signal DT whose signal level is set to the high level “H” for one clock from the fall of the synchronization signal Ss. The signals UT and DT are supplied to the identification circuit 60, the cycle detection circuit 70, and the identification circuit 80.

The discriminating circuit 60 has the configuration shown in FIG. 3, and the EPR4 supplied from the (1-D ² ) filter 44.
The equalized signal SEPR is supplied to a delay unit 61 and a subtractor 62. In the subtractor 62, the EPR4 equalized signal SEPR delayed by one clock in the delay unit 61 from the EPR4 equalized signal SEPR
Is subtracted. Therefore, EPR4 is output from the subtractor 62.
A signal in which the equalized signal SEPR is equalized to the characteristic of PR (1, -1) is output as an equalized signal SEPR (1-D). This equalized signal SEPR (1-D) is supplied to the delay unit 63.

The delay unit 63 has an OR gate 65 described later.
Supplies the integration detection identification signal GT, and the equalization signal SEPR (1-D) at a timing based on the integration detection identification signal GT.
Are latched and supplied to the sign determination unit 64 as a sign signal MF. The sign determination unit 64 is supplied with the signal DT obtained by the differentiating circuit 50, and the sign of the sign signal MF is inverted based on the signal DT. The code signal MF processed by the code determination unit 64 is the selection signal CHC
Is supplied to the signal selector 68.

The signals UT and DT obtained by the differentiating circuit 50
Is supplied to the OR gate 65. The integration detection identification signal GT obtained by the OR gate 65 is supplied to the above-described delay unit 63 and is also supplied to the signal selection unit 68 via the delay unit 66 as a signal GTA. Further, the integral detection identification signal GT is supplied to the signal selection unit 68 as the signal GTB via the delay units 66 and 67.

Therefore, the signal selecting section 68 selects the selection signal C
Either the signal GTA or GTB is selected based on the HC and output as the binary signal TEPR. This 2
The digitized signal TEPR is supplied to a cycle detection circuit 7 serving as cycle detection means.
0 is supplied.

The cycle detection circuit 70 has the configuration shown in FIG. In FIG. 4, the binarized signal TEPR supplied from the discriminating circuit 60 includes a delay unit 71-1 at one end of 2n delay units 71-1 to 71-2n connected in series, and a series connection. The supplied 2n delay units 74-1 to 74-2n are supplied to one end side of the delay units 74-1.

The delay units 71-1 to 71- (n-1), 71- (n +
Outputs of 1) to 71-2n are connected to the ROM table unit 73. The signal UT is connected to n delay units 7 connected in series.
2-1 to 72-n are supplied to one end side of the delay unit 72-1. The output of the final stage delay unit 72-n is supplied to the ROM table unit 7.
3 is connected. Here, the number of the delay units 71 and 72 is set based on the modulation method of the recording signal. For example, in the case of the RLL (1, 7) code, since there is no code of 9 clocks or more, n = 8 Is set to

In the ROM table 73, the delay units 72-n
Delay units 71-1 to 71- based on the signal UTn output from
2n outputs T1-1 to T1-2n are detected, and a period signal FDU corresponding to the period of the peak phase of the binarized signal T1 before and after the timing of this detection is generated. This periodic signal FDU is supplied to the identification circuit 80.

Similarly, the delay units 74-1 to 74-2n, the signal D
The signal DT output from the delay unit 75-n is supplied to the delay units 75-1 to 75-n and the ROM table unit 76 to which T has been supplied.
Based on n, outputs T4-1 to T4-2 of delay units 74-1 to 74-2n.
n is detected, and a period signal FDD corresponding to the period of the peak phase of the binarized signal T4 before and after the timing at which the detection is performed is output from the ROM table unit 76. This periodic signal FDD is also supplied to the identification circuit 80.

FIG. 5 shows the structure of the identification circuit 80 as the third identification means. In this identification circuit 80, (1 + D)
EEPR4 equalization signal SEEPR supplied from filter 46
, And the final binary identification signal Sg using a signal MD indicating the obtained operation result M.
Is what you get. M = (P ₋₃ −P ₀ ) + (P ₋₂ −P ₁ ) (4) Note that “P ₁ ” is an EE input to a delay unit 82 described later.
A waveform value of the PR4 equalized signal SEEPR, "P _0" indicates the waveform of the signal output from the delay unit 82, "P _{- 2"}
Represents the waveform value of the signal output from the delay unit 84, and "P _-3 " represents the waveform value of the signal output from the delay unit 85.

In FIG. 5, the EEPR4 equalization signal SEEPR supplied from the (1 + D) filter 46 is supplied to the timing adjustment unit 81. In the timing adjustment unit 81, the periodic signals FDU and FDD generated based on the output signal UTn of the delay unit 72-n of the n-th stage and the output signal DTn of the delay unit 75-n of the n-th stage, and the EEPR4 equalized signal S
This is for adjusting the timing of EEPR. The EEPR whose timing has been adjusted by the timing adjusting unit 81
The four equalized signal SEEPR is connected to four delay units 82 connected in series.
８５85 to one end side of the delay unit 82 and to the subtractor 87. Output signal STD82 of delay unit 82
Is supplied to a subtractor 86, and the output signal STD84 of the delay unit 84 is supplied to a subtractor 87. The output signal STD85 of the delay unit 85 is supplied to a subtractor 86.

In the subtractor 86, the output signal STD82 is subtracted from the output signal STD85, and a signal PA indicating the operation result is supplied to the adder 88. Further, the subtracter 87 subtracts the EEPR4 equalization signal SEEPR from the output signal STD84 and supplies a signal PB indicating the operation result to the adder 88. In the adder 88, the signal PA and the signal PB are added to obtain an equation (4).
Is generated and supplied to the ROM table unit 89 and the ROM table unit 93.

The ROM table 89 is supplied with the periodic signal FDU from the cycle detecting circuit 70, and outputs a selection signal CHU indicating the sign of the final evaluation value obtained based on the signal MD and the periodic signal FDU to the signal selector 92. Supplied to

The signal selection section 92 is supplied with the signal UT supplied from the differentiating circuit 50 via the timing adjustment section 90 and the signal UTd delayed by one clock by the delay unit 91. The timing adjustment unit 90 generates the signal MD based on the output signal STD82 of the delay unit 82 as described later, and performs the binary identification based on the signal MD. Therefore, the timing adjustment unit 90 determines the timing of the signal MD and the signal UT. It is to match. Note that this timing adjustment unit 9
At 0, the timing of the signal DT is also adjusted.

In the signal selection section 92, the ROM table section 8
Either the signal UT whose timing has been adjusted or the signal UTd obtained by delaying the signal UT by one clock based on the selection signal CHU from No. 9 is selected and supplied to the JK flip-flop 96 as the output signal OTU. .

The ROM table 93 is supplied with the periodic signal FDD from the cycle detecting circuit 70, and the selection signal CHD indicating the sign of the final evaluation value obtained based on the signal MD and the periodic signal FDD is selected. It is supplied to the unit 95.

The signal selecting section 95 is supplied with the signal DT supplied from the differentiating circuit 50, and outputs 1
A clock delayed signal UTd is provided. In the signal selection section 95, either the signal DT or the signal DTd delayed by one clock is selected based on the selection signal CHD from the ROM table section 93, and supplied to the JK flip-flop 96 as the output signal OTD. You.
In the JK flip-flop 96, the supplied output signal O
A final binary identification signal Sg is output from the Q output terminal based on TU and OTD.

Next, the operation of the digital signal processing device will be described with reference to FIGS. When the recording signal WS is as shown in FIG. 6A, the Nyquist equalized signal Seq shown in FIG. 6B is output from the integral equalizer 10. The comparator 11 determines whether the signal level of the Nyquist equalization signal Seq is on the positive side or the negative side, and generates the binary signal Sb as shown in FIG. 6C. Clock generation circuit 20
Then, based on the binarized signal Sb, as shown in FIG. 6D, the clock signal CL is adjusted so that the phase of the edge of the binarized signal Sb and the rising edge of the clock signal CLK become equal.
The frequency of K is controlled.

In the synchronization circuit 12, the clock signal C
The binarized signal Sb is latched based on LK, and FIG.
As shown in (1), a synchronization signal Ss synchronized with the rising edge of the clock signal CLK is generated.

For this reason, in the synchronization signal Ss, even if the reproduced signal Sa includes noise or the like, the phase of the synchronization signal Ss is set to either the solid line or the broken line, and the phase variation is kept within one clock. . For this reason, the signals UT and DT output from the differentiating circuit 50 are also as shown in FIGS.
It is assumed that the phase change is within one clock.

The Nyquist equalized signal Seq is converted to an A / D converter 4
The EPR4 equalized signal SEPR obtained by processing by the 0 or (1 + D) filter 42 and the (1-D ² ) filter 44 is
Since this is the difference between the PR1 equalized signal SPR1 and the PR1 equalized signal SPR1 two clocks before the PR1 equalized signal SPR1 and the PR1 equalized signal SPR1 two clocks before the PR1 equalized signal SPR1 as shown in FIG. An EPR4 equalized signal SEPR is generated. In FIG. 7, the signal levels are normalized.

FIG. 7A shows a PR1 equalized signal S
FIG. 7B shows a PR1 equalized signal SPR1 (n-2) which is a signal two clocks before.
Since the PR1 equalized signal SPR1 (n−2) two clocks before is subtracted from the PR1 equalized signal SPR1 (n), the PR1 equalized signal SPR1 (n−2) two clocks before shown in FIG. 7B. 2) shows a state where the sign is inverted.

The PR1 equalized signal SPR1 (n) and PR1
From the equalized signal SPR1 (n-2), an EPR4 equalized signal SEPR is generated as shown in FIGS. 7C to 7G. FIG.
7C shows a case where the recording signal is “1T (T is a bit interval)”, FIG. 7D is “2T”, FIG. 7E is “3T”, and FIG.
F shows a case of “4T”, and FIG. 7G shows a case of “5T”.
Thus, after “4T”, “0” is inserted after “1, 2, 1”, and the process ends with “−1, −2, −1”.

Here, the peak value of the EPR4 equalized signal SEPR indicates the phase of the change point (1 → 0 and 0 → 1) of the recording signal WS, and the obtained EPR4 equalized signal SEPR is obtained.
Is detected by the identification circuit 60.

In the identification circuit 60 shown in FIG. 3, the EPR4 equalized signal SEPR is equalized to the characteristic of PR (1, -1) to obtain an equalized signal SEPR (1-D). Further, based on the integral detection identification signal GT obtained from the OR gate 65, the equalization signal SEP
The sign of R (1-D) is determined. Here, when the recording signal WS is 4T-4T as shown in FIG. 8A, the EPR4 equalization signal SEPR is as shown in FIG. 8B, so that either the predetermined phase or the phase delayed by one clock is used. The peak phase is limited to the position A or the position B by performing the determination based on the integral detection identification signal GT indicating the two phases.

Further, the level "P0" at the position A or the position B and the level "P-1" at the preceding sample point are obtained.
When Expression (5) is satisfied, this position is the peak phase, and when Expression (6) is satisfied, the position one clock before the position is determined as the peak phase. P0-P-1> 0 (5) P0-P-1 <0 (6) The discrimination of the peak phase is performed by the identification circuit 60 using the equalized signal S.
This is performed by determining the sign of EPR (1-D).

In the delay unit 63, the sign of the equalized signal SEPR (1-D) is latched based on the integral detection identification signal GT, and the sign signal MF indicating the sign is supplied to the sign judgment unit 64. The sign of the equalized signal SEPR (1-D) is changed from “+” to “−” at time ta, for example, as shown in FIG. 9A, and is changed from “−” to “+” at time tb. Shall be. 9B, 9C, and 9D show signal UT and signal D, respectively.
T and the integral detection identification signal GT.

In this case, at time t1, the equalized signal SEPR (1-
Since the sign of D) is “+”, the signal level of the sign signal MF is, for example, a high level “H”. afterwards,
At time t5, since the sign of the equalized signal SEPR (1-D) becomes "-", the signal level of the sign signal MF is set to the low level "L".

The sign judging section 64 latches the sign signal MF shown in FIG.
Is set to the high level "H", the sign signal MF is inverted. For this reason, as shown in FIG.
HC is at a high level “H” from time t2 to time t6, and the logic level of the code signal MF is inverted because the signal DT is at a high level “H” during the period from time t5 to t6. The high level "H" is maintained from time t6.

When the signal level of the selection signal CHC is at the low level "L", the signal selection section 68 determines that the phase is delayed, and the signal selection section 68 switches to FIG. 9G one clock phase earlier than the signal GTB shown in FIG. 9H. The signal GTA shown is selected. When the signal level of the selection signal CHC is at the high level “H”, it is determined that the phase is correct, and the signal GTB is selected.

Here, since the selection signal CHC is at the high level "H", it is determined that the phase is correct, the signal GTB is selected, and the binarized signal TEPR is changed from the time t3 to the time t3.
4. High level "H" during the period from t7 to t8.

When the phase is delayed, the signals shown in FIGS. 9B to 9D and FIGS. 9G and H are delayed by one clock from the case where the phase is correct, as shown in FIGS. 10B to 10D and 10G and 10H. The signal is set to the high level “H”. Note that FIG.
In B to D and FIGS. 10G and 10H, the broken lines show the case where the phase is correct. For this reason, the sign signal MF shown in FIG. 10E indicates the sign of the equalized signal SEPR (1-D) at the time point t2 and is set to the low level "L", and is set to the high level "H" at the time point t6. You. Therefore, the selection signal CHC shown in FIG. 10F is changed to the low level "L" from the time point t3, and at the time point t7, the logic level of the code signal MF is inverted to the low level "L".

For this reason, the signal selecting section 68 determines that the phase is delayed, and the signal GTA shown in FIG. 10G is two clocks earlier than the signal GTB shown in FIG. 10H by one clock phase.
The binarized signal TEPR is selected as the binarized signal TEPR, and during the period from time t3 to t4 and t7 to t8, which is equal to the case where the phase is correct, the binarized signal TEPR is set to the high level "H".

Next, the operation of the cycle detection circuit 70 to which the binarized signal TEPR is supplied will be described. The binarized signal TEPR is
As described above, 2n delay units 71-1 to 7n are connected in series.
71-2n is supplied to a delay unit 71-1 on one end side.
The binarized signal TEPR is sequentially transmitted from the delay unit 71-1 to the delay unit 7
1-2n, and the signal UT is also supplied to the delay unit 72-1 at one end of the n delay units 72-1 to 72-n connected in series. Forwarded to -n.

Here, the outputs of the delay units 71-1 to 71- (n-1) and the delay units 71- (n + 1) to 71-2n and the output of the delay unit 72-1 are stored in the ROM table unit 73. For example, when the signal UT is set to the high level “H”,
That is, when the recording signal WS rises, the delay device 71-1
By determining the output of the binary signal TEPR before and after this timing, it is possible to detect the period of the peak phase of the binary signal TEPR before and after this timing. A period signal FDU is output from the ROM table 73 according to the detected period. This periodic signal FDU is supplied to the identification circuit 80.

Similarly, when the signal DT is set to the high level "H", that is, at the time of the fall of the recording signal WS, the delay units 74-1 to 74- (n-1) and 74- (n + 1) to 74- (n + 1) are output. By determining the output of 74-2n, the period of the peak phase of the binary signal TEPR before and after this timing can be detected, and the periodic signal FDD is output from the ROM table 73 according to the detected period. Is done. This periodic signal FDD is applied to the identification circuit 8
0 is supplied.

The identification circuit 80 has an EEPR4 equalized signal S
EEPR is supplied. This EEPR4 equalization signal SEEPR is
As shown in FIG.
It can be obtained from the PR4 equalized signal SEPR. Note that FIG. 11 also shows the signal levels normalized.

In FIG. 11, FIG. 11A shows an EPR4 equalized signal SEPR (n), and FIG. 11B shows an EPR4 equalized signal SEPR (n-1) which is a signal one clock before. This EPR4 equalized signal SEPR (n) and EPR
By adding the four equalized signals SEPR (n-1), the EEPR4 equalized signal SEEE is obtained as shown in FIGS. 11C to 11G.
A PR is generated. FIG. 11C shows that the recording signal is “1T
(T is a bit interval), FIG. 11D is “2T”, FIG. 11E is “3T”, FIG. 11F is “4T”,
FIG. 11G shows the case of “5T”. in this way,
After “5T”, “0” is inserted after “1, 3, 3, 1”, and the process ends with “−1, −3, −3, −1”.

Here, if the peak of the EEPR4 equalized signal SEEPR is obtained, a desired change point can be identified. However, as shown in FIGS. 11E to 11G, the peak does not exist at the sample point. "-3" and "-3" are identified. In the case of 2T, the recording signal WS
As shown in FIG. 12A, when the preceding and following periods are “2T”, as shown in FIG. 12B, the subsequent “2 (−2)”
When the period after “2T” is “3T or more” as shown in FIG. 12C, “3 (−3)” is identified as shown in FIG. 12D and shown in FIG. 12E. When the cycle before “2T” is “3T or more”, “2 (−2)” is identified as shown in FIG. 12F. Note that the values in parentheses show the case of the falling edge of “2T”. FIG. 11 also shows the case where the recording signal is “1T”, but the modulation method of the recording signal is R
When the code is an LL (1, 7) code, the shortest cycle is “2”.
“1T” does not exist because it is greater than or equal to “T”.

The discrimination point of interest is limited to the correct phase or the phase delayed by one clock by the integration detection, and the intersymbol interference is limited by the EPR4 equalization signal SEPR. Phase and EP
EEPR4 equalized signal S based on phase obtained by R4 identification
The waveform pattern of EEPR is limited to two. For example, based on the periodic signal FDU, if the interval between phases obtained by EPR4 identification is “12T” as shown in FIG. 13A and the phase obtained by integration detection is the position before and after “6T”, Since the phase obtained by the detection is limited to the correct phase or the phase delayed by one clock, when the position before and after “6T” is the correct phase, as shown in FIG. 13B, “6T−6T” and “6T” before and after Is a phase delayed by one clock, as shown in FIG. 13C, "5T-7
T ". Therefore, a desired phase is identified by determining which waveform pattern the EPPR4 equalized signal SEEPR is close to. Note that FIG.
5 shows a case where the phase obtained by the integration detection is the rising edge of the recording signal WS.

Here, the discriminating circuit 80 uses the outputs of the delay units 82 to 85 to which the EEPR4 equalized signal SEEPR whose timing has been adjusted is supplied, by the subtractors 86 and 87 and the adder 88 to obtain the equation (7). The calculation processing shown in FIG.
Is calculated. M = (P−3−P0) + (P−2−P1) (7)

In the equation (7), "P0" indicates the waveform level of the phase identified by the integration detection, and the output signal STD82 of the delay unit 82 corresponds to "P0". "P-2"
Indicates the waveform level two clocks before the phase identified by the integration detection, and “P−3” indicates the waveform level three clocks before the output signal S of the delay units 84 and 85, respectively.
TD84 and STD85 correspond. "P1" indicates the waveform level one clock after, and E1 is input to the delay unit 82.
The EPR4 equalization signal SEEPR corresponds to this.

The evaluation value M is “M” when the waveform pattern of the EEPR4 equalization signal SEEPR is as shown in FIG. 13B.
= −3 ”, and“ M = 3 ”when the waveform pattern is as shown in FIG. 13C.

For this reason, the sign of the signal MD indicating the evaluation value M is determined. If the sign is negative, the phase identified by the integration detection (the phase indicating the rising of the recording signal WS) is the correct phase, and the sign is When it is positive, it can be identified that the phase is delayed by one clock.

By the way, as shown in FIG.
When the phase interval obtained by the 4 identification is “6T”, and the phase obtained by the integration detection is the correct phase and at the position “3T” before and after, “3T-3” as shown in FIG.
When the position of "T" and the position of "6T" before and after are phases delayed by one clock, the waveform T pattern is "2T-4T" as shown in FIG. 14C.

In this case, the evaluation value M is “M = −6” when the waveform pattern of the EEPR4 equalized signal SEEPR is as shown in FIG. 14B, and when the waveform pattern is as shown in FIG. 14C. Since “M = 0” and an offset, it is not possible to correctly determine whether the phase identified by the integration detection is the correct phase or the phase delayed by one clock. Therefore, the correction value CP is added to the evaluation value M according to the period before and after the phase obtained by the integration detection, and the final evaluation value D is obtained. For example, in the case shown in FIG. 14, the correction value CP = 3 is added to the evaluation value M, and when the waveform pattern of the EEPR4 equalized signal SEEPR is that shown in FIG. 14B, "D = -3" and the waveform pattern 14C is the one shown in FIG. 14C, “D = 3” is set, and FIG. 14B shows the correct phase based on the sign of the final evaluation value D.
4C can be identified as a phase delayed by one clock.

FIG. 15 shows an equation for obtaining the final evaluation value D according to the period before and after the phase obtained by the integration detection, and the correction value is added to the evaluation value M according to the period.

When a fixed value is added to the evaluation value M, the phase of the reproduced signal S is determined based on the final evaluation value D.
It is conceivable that it is affected by the amplitude fluctuation of a.
Therefore, the correction value COA or the correction value COB is calculated by the equation (8) or (9), and a value obtained by multiplying the correction value COA or the correction value COB by a coefficient is used as a correction value MC.
Is added to the evaluation value M to obtain the final evaluation value D. From the sign of the final evaluation value D, the phase can be identified without being affected by the amplitude fluctuation of the reproduction signal Sa. COA = P-2 + P-1 + P0 (8) COB = P-1 (9)

For example, in the case of FIG. 13B, the correction value COA
Is set to “+6”. Therefore, the correction value COA is set to “1/3” so that the correction value in the case of “3T−3T” becomes “3”.
2 "is multiplied.

As described above, the final evaluation value D is obtained according to the waveform pattern, and the selection signal CHU indicating the sign of the final evaluation value D is generated by the ROM table section 89.

The selection signal CHU obtained by the ROM table section 89 is supplied to a signal selection section 92. When the sign of the final evaluation value D is positive based on the selection signal CHU, the signal selection unit 92 selects the signal UTd from the delay unit 91 because the phase identified by the integration detection is correct. The output signal is OTU. When the sign is negative, the signal UT supplied from the timing adjustment unit 90 without the delay unit 91 is selected because the phase one clock before the phase identified by the integration detection is correct. Output signal OTU. This output signal OTU is J
It is supplied to the J input terminal of the K flip-flop 96.

In the ROM table section 93, the phase of the falling edge of the recording signal WS is identified in the same manner, and based on the signal MD and the periodic signal FDD, the final evaluation value is obtained according to the waveform pattern. Select signal C shown
HD is generated. In this case, since a negative peak is detected, the correction value shown in FIG. 15 is used with its sign inverted.

When the sign of the final evaluation value is negative based on the selection signal CHD, the signal selection section 95 selects the signal DTd from the delay unit 94 because the phase identified by the integration detection is correct. Output signal OTD. When the sign is positive, the signal DT supplied without passing through the delay unit 94 is selected because the phase one clock before the phase identified by the integration detection is correct, and the output signal OTD is output. Is done. This output signal OTD is supplied to the K input terminal of the JK flip-flop 96.

For this reason, the Q of the JK flip-flop 96
From the output terminal, an output signal OTU and an output signal OTD
, A binary identification signal Sg of a correct phase generated based on the above is output.

As described above, according to the above-described embodiment, E
Unlike the case where Viterbi decoding is applied to a partial response equalized signal having large intersymbol interference such as PR4 and EEPR4, a complicated circuit peculiar to Viterbi decoding is not required.
High-speed identification can be performed with a relatively simple circuit. In addition, since identification can be performed using information of a waveform affected by level fluctuation and including intersymbol interference, highly accurate identification can be performed.

In the above embodiment, RLL (1,
7) The case where the present invention is applied to codes has been described.
A code whose minimum cycle is 3T, such as a (2, 7) code,
Needless to say, the present invention can easily be applied to a code having a minimum cycle of T, such as an NRZI code.

[0089]

According to the present invention, the reproduction signal obtained by reproducing the recording medium on which the digital signal is recorded is provisionally identified, and the phase of the change point is limited. For example, an EPR4 equalized signal obtained by processing a reproduction signal is identified based on the phase of the change point, and the phase of the change point before and after the target identification change point is determined from the identification result. Further, the period of the signal obtained by identifying the EPR4 equalized signal is detected, and based on the limited waveform pattern from the detected period and, for example, the EEPR4 equalized signal obtained by processing the reproduced signal, Value identification is performed.

As described above, identification can be performed from a large amount of information included in a waveform including intersymbol interference, so that highly accurate identification can be performed. Also, the configuration can be relatively simple.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a main part of a digital signal reproducing apparatus according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a differentiating circuit 50;

FIG. 3 is a diagram showing a configuration of an identification circuit 60.

FIG. 4 is a diagram showing a configuration of a cycle detection circuit 70.

FIG. 5 is a diagram showing a configuration of an identification circuit 80;

FIG. 6 is a diagram for explaining the operation of the differentiating circuit 50;

FIG. 7 is a diagram illustrating generation of an EPR4 equalized signal.

FIG. 8 is a diagram for explaining the operation of the identification circuit 60;

FIG. 9 is a diagram for explaining the operation of the identification circuit 60;

FIG. 10 is a diagram for explaining the operation of the identification circuit 60;

FIG. 11 is a diagram illustrating generation of an EEPR4 equalized signal.

FIG. 12 is a diagram for explaining the operation of the identification circuit 80;

FIG. 13 is a diagram for explaining the operation of the identification circuit 80;

14 is a diagram for explaining the operation of the identification circuit 80. FIG.

FIG. 15 is a diagram for explaining a calculation operation of a final evaluation value D.

FIG. 16 is a diagram showing a configuration of a main part of a digital signal reproducing apparatus using an integration detection method.

FIG. 17 is a diagram illustrating frequency characteristics of the Nyquist equalized signal Seq.

FIG. 18 is a diagram showing an eye pattern of a Nyquist equalization signal Seq.

FIG. 19 is a diagram for explaining the operation of the digital signal reproducing device using the integration detection method.

FIG. 20 is a diagram showing a configuration of a main part of a digital signal reproducing apparatus using an amplitude detection method.

FIG. 21 is a diagram illustrating frequency characteristics of a signal S (1-D).

FIG. 22 is a diagram showing an eye pattern of a signal S (1-D).

FIG. 23 is a diagram for explaining the operation of the digital signal reproducing apparatus using the amplitude detection method.

[Explanation of symbols]

10: integral equalizer, 11: comparator, 12
... Synchronization circuit, 20 ... Clock generation circuit, 40
... A / D converter, 42,46 ··· (1 + D) ^{filter, 44 ··· (1-D 2} ) filters, 50 ...
Differentiating circuit, 60, 80 ... discriminating circuit, 70 ... period detecting circuit, 64 ... sign determining unit, 68, 92, 95
..Signal selectors, 73, 76, 89, 93... ROM
Table section

Claims (3)

[Claims] A tentative identification of a reproduced signal obtained by reproducing a recording medium on which a digital signal is recorded, limiting a phase of a change point to a predetermined range, and differentiating a phase based on the obtained phase of the change point. Identify the signal equalized to the equalization criterion, determine the phase of the change point before and after the identification change point of interest from this identification result, and obtain a partial response equalized signal with more intersymbol interference. A digital signal processing method, wherein a waveform pattern is limited, and a binary identification signal is obtained based on the waveform pattern. 2. A first identification means for temporarily identifying a reproduction signal obtained by reproducing a recording medium on which a digital signal is recorded and for limiting a phase of a change point to a predetermined range, First equalizing means for equalizing to an equalization criterion for increasing interference; and a signal obtained by the first equalizing means, the first identification means being based on an identification result of the first identification means. A second identification means for equalizing to a different equalization criterion; a cycle detection means for detecting a cycle of the identification result of the second identification means based on the identification result of the first identification means; A second equalizing means for equalizing the signal obtained by the equalizing means to an equalization criterion for increasing inter-symbol interference; and an identification result of the first identification means and a cycle limited by the cycle detection means. The waveform pattern is limited based on the waveform pattern and obtained by the second equalizing means. Digital signal reproducing apparatus characterized by comprising a third identification means for obtaining a binary identification signal based on the signal. 3. The method according to claim 2, wherein the third identification means corrects an offset of the waveform pattern and obtains a binary identification signal based on the signal obtained by the second equalization means. The digital signal reproducing apparatus according to claim 2, wherein