JPH10321831A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress back gate effects, particularly, their influences on the surrounding regions of an output section by forming the P-well regions of the output section and a protective element in a common well region and the wiring for transmitting output signals and an element connected to the wiring in the common P-well region. SOLUTION: In a semiconductor device, an N-channel FET which is formed as an output stage, a transistor which is formed as a protective element, and wiring 3 which connects the FET and transistor to a pad 4 are formed in, for example, the common P-well 2 of an N-type substrate 1. The common P-well 2 is formed by connecting an the P-wells of an output section and the protective element to each other. Thus the region around the output section of the wiring 3 and pad 4 is separated and electrically isolated from the substrate 1 through the common P-well 2. Therefore, back gate effects by which output signals are modulated and caused by the fluctuation of the potential at the substrate can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having at least an output portion second conductivity type well region and a protection element second conductivity type well region formed on a first conductivity type substrate.

[0002]

2. Description of the Related Art Conventionally, in a MOS integrated circuit, a P-well is formed in an N-type substrate as an output stage, and a source region and a drain region in which a high concentration N-type impurity is diffused are buried in the P-well. An N-channel FET in which a gate having a MOS structure is arranged in a channel is used.

As an example of such a MOS integrated circuit, there is a semiconductor device shown in FIG.

In this semiconductor device, an output portion P-well 6 having an N-channel FET as an output stage, a protection element P-well 5 having a transistor as a protection element, and an external wire are provided on an N-type substrate 1. Pad 4 to be connected
And a wiring 3 for connecting these FETs and transistors to the pad 4 and transmitting an output voltage.

The output section P-type well 6 has a first high concentration N
Mold region 11, a second high-concentration N-type region 12, a third high-concentration N-type region 13, a first high-concentration P-type region 14, a first gate 18, and a second gate 19. Are formed.

The first high-concentration N-type region 11 and the third high-concentration N-type region 13 are formed so as to be separated from each other by a predetermined distance. 18 are attached to form an N-channel FET.
The first high-concentration N-type region 11 is connected to the source terminal 21, the third high-concentration N-type region 13 is connected to the wiring 3, and the first gate 18 is connected to the gate terminal 23.

The second high-concentration N-type region 12 and the third high-concentration N-type region 13 are formed so as to be separated from each other by a predetermined distance, and a channel therebetween is provided with a second gate through an insulating layer. Reference numeral 19 is attached to form an N-channel FET.
The second high-concentration N-type region 12 is connected to the drain terminal 22.
The third high-concentration N-type region 13 is connected to the wiring 3, and the first gate 19 is connected to the input terminal 23. Further, the first high-concentration P-type region 14 is connected to the output unit P-well terminal 25.

The protection element P well 5 is separated from the output part P well 6 by a predetermined distance, and is provided with a fourth high-concentration N-type region 15.
, A second high-concentration P-type region 16 and a third high-concentration P-type region 17 are formed.

A fourth high-concentration N-type region 15 and a second high-concentration P-type region 16, and a fourth high-concentration N-type region 15 and a third
The high-concentration P-type regions 17 are formed at a predetermined distance from each other to constitute a protection transistor.

The fourth high-concentration N-type region 15 is
And the second high-concentration P-type region 16 and the third high-concentration P-type region 17 are connected to the protection element P-well terminal 26. The protection element P well terminal 26 has a predetermined voltage V
L may be applied in some cases. In this case, since the potentials of the protection element P well 5 and the output section P well 6 are different, these P wells are formed separately.

The wiring 3 is a conductive layer formed on the substrate with an insulating layer interposed therebetween.
And the fourth high-concentration N-type region 15 and the pad 4 are connected.

On the N-type substrate 1, a plurality of high-concentration N-type regions 31 are formed, each having a substrate voltage terminal 2
7 is connected.

[0013]

By the way, in the above-mentioned semiconductor device, a so-called back gate effect is known. The back gate effect refers to a phenomenon in which a change in the substrate potential of the N-type substrate 1 appears on the pad 4 as a change in the output voltage.

An example of the back gate effect is a CCD
In a semiconductor device including a solid-state imaging device, a pulse of an electronic shutter applied to a substrate is output from a FET at an output stage.
May affect the video signal.

As for the back gate effect, there is a case where a portion around an output such as a wiring, a resistor, and a capacitor disposed in a semiconductor device is directly affected as a fluctuation of a substrate potential. Due to such a back gate effect, characteristics of an output signal may be deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a semiconductor device in which the back gate effect, particularly the influence on the portion around the output, is suppressed.

[0017]

According to the present invention, there is provided a semiconductor device having at least an output P-well region and a protection element P-well region formed on an N-type substrate. The output portion P-well region and the protection element P-well region are a common P-well region, and a wiring for transmitting an output signal and an element connected to the wiring are formed in the common P-well region.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an example of an embodiment of a semiconductor device according to the present invention will be described in detail.

This semiconductor device, as shown in FIG.
An N-channel FET as an output stage, a transistor as a protection element, and a wiring 3 connecting these FETs and transistors to a pad 4 are formed in a common P well 2 of a mold substrate 1.

That is, this semiconductor device is the same as that of the conventional semiconductor device shown in FIG.
And the protection element P well 5 are connected to form a common P well 2
It is said that.

The common P-type well 2 has a first high-concentration N-type region 11, a second high-concentration N-type region 12, a third high-concentration N-type region 13, and a fourth high-concentration N-type region 13. Mold region 15 and the first
High-concentration P-type region 14 and second high-concentration P-type region 16
And a third high-concentration P-type region 17 and a first gate 18
And a second gate 19 are formed.

The first high-concentration N-type region 11 and the third high-concentration N-type region 13 are formed so as to be separated from each other by a predetermined distance, and a channel between them is provided with a first gate through an insulating layer. 18 are attached to form an N-channel FET.
The first high-concentration N-type region 11 is connected to the source terminal 21, the third high-concentration N-type region 13 is connected to the wiring 3, and the first gate 18 is connected to the gate terminal 23.

The second high-concentration N-type region 12 and the third high-concentration N-type region 13 are formed so as to be separated from each other by a predetermined distance, and a channel therebetween is provided with a second gate through an insulating layer. Reference numeral 19 is attached to form an N-channel FET.
The second high-concentration N-type region 12 is connected to the drain terminal 22.
The third high-concentration N-type region 13 is connected to the wiring 3, and the first gate 19 is connected to the input terminal 23. Further, the first high-concentration P-type region 14 is connected to the output unit P-well terminal 25.

The fourth high-concentration N-type region 15 and the second high-concentration P-type region 16, and the fourth high-concentration N-type region 15 and the third
The high-concentration P-type regions 17 are formed at a predetermined distance from each other to constitute a protection transistor.

The fourth high-concentration N-type region 15 is
And the second high-concentration P-type region 16 and the third high-concentration P-type region 17 are connected to the protection element P-well terminal 26.

The wiring 3 is a conductive layer formed on the substrate with an insulating layer interposed therebetween.
And the fourth high-concentration N-type region 15 and the pad 4 are connected.

The first high-concentration P-type region 14 is connected to an output P-well terminal 25. The N-type substrate 1
Are formed with a plurality of high-concentration N-type regions 31, each of which is connected to a substrate voltage terminal 27.

Thus, in this semiconductor device,
A portion around the output of the wiring 3 and the pad 4 is separated from the N-type substrate 1 via a common P well 2 and is electrically isolated. Therefore, for example, the degree of the fluctuation of the substrate potential applied to the N-type substrate 1 due to the pulse of the electronic shutter of the CCD solid-state imaging device reflected on the output signal as the back gate effect is reduced.

Next, an example of a mode in which the above-mentioned FET is used as an output stage for a signal supplied from the CCD solid-state imaging device will be described.

The CCD solid-state image pickup device 102 is the same as that shown in FIG.
As shown in FIG. 1, the semiconductor device is integrally formed as a part of a semiconductor chip 101 constituting the semiconductor device. Here, for the sake of simplicity, the first FET 103 and the second FE
T104 is shown, and the protection transistor is omitted.

The IC chip 101 has the following terminals:
It has a source voltage terminal 21, a gate voltage terminal 23, a drain voltage terminal 22, a well ground terminal 25, a substrate voltage terminal 27, and an output voltage terminal 105.

The operation of each part of the IC chip 101 will be described in accordance with the flow of signals. Output from the voltage terminal 105. This first FET 1
03, the drain of which is connected to the source and the output voltage terminal 105, is controlled by the gate voltage applied from the gate voltage terminal VGG, and
Acts as a load on ET103.

The drain of the first FET 103 is supplied with the drain voltage VDD from the drain voltage terminal 22, and the source of the second FET is supplied with the source voltage VSS from the source voltage terminal 21. The output voltage terminal 10
Between the terminal 5 and the well ground terminal 25, a transistor (not shown) is formed as a protection element.

Subsequently, in this IC chip 101,
The structure of the semiconductor device shown in FIG. 1 will be described.

As described above, this IC chip 101
Has a CCD solid-state imaging unit 102 in addition to the output-stage FET shown in FIG. Specifically, the second high-concentration N-type region 12, the second gate 19,
N-channel FET comprising the third high-concentration region 13
Corresponds to the first FET 103 of the IC chip 101. Further, the third high-concentration N-type region 1 in FIG.
3, an N-channel FET comprising a first gate 18 and a first high-concentration region 11
FET104.

Further, the wiring 3 and the pad 4 formed in the common P well 2 of FIG. 1 are connected to the output voltage terminal 105 of the IC chip 101. Further, a fourth high-concentration N-type region 15, a second high-concentration P-type region 16,
Although not shown, the transistor formed of the third high-concentration P-type region 17 is inserted between the output voltage terminal 105 of the IC chip 101 and the well ground terminal 25 to serve as a protection element.

In the IC chip 101, a common P well 2 is formed, and portions around outputs such as wirings and pads are formed in the common P well 2.

The source voltage terminal 21, the drain voltage terminal 22, the gate voltage terminal 23, the well ground voltage terminal 25, and the substrate voltage terminal 27 in FIG. Connected.

Such an IC chip 101 has the features of the semiconductor device described above. That is, this IC chip 1
09, a portion around the output, such as wiring and pads connected to the output voltage terminal 105, is formed in the common P-well even when the substrate potential fluctuates due to the pulse of the electronic shutter of the CCD image sensor section 102. Because of the electrical isolation, the influence of the back gate effect that the fluctuation of the substrate potential modulates the output signal is reduced.

In this embodiment, the first conductivity type is illustrated as N-type and the second conductivity type is illustrated as P-type. However, the first conductivity type is P-type, and the second conductivity type is P-type. May of course be N-type.

In the above embodiment, the output voltage wiring 3 and the pad 4 have been exemplified. However, the resistance, the capacitance, the source voltage, the gate voltage, the drain voltage wiring and the pad, and other parts around the output are also included. The back gate effect can be reduced by electrically separating the N-type substrate 1 from the N-type substrate 1 by the P well 2.

Further, the present invention relates to a CCD image pickup device 10
The invention is not limited to this example, and the back gate effect of the device can be reduced by using the device for another device in which the substrate potential fluctuates.

The present invention is not limited to the arrangement of the regions shown in the above embodiment. For example, the high-concentration N-type region 31 formed on the N-type substrate 1 in FIG. 1 can be in contact with the protection element near the protection element by providing a contact region on the island.

[0044]

As described above, the semiconductor device according to the present invention can reduce the back gate effect in which the output signal is modulated by the fluctuation of the substrate potential.
Therefore, for an element such as a CCD image sensor whose substrate potential fluctuates due to the pulse of an electronic shutter, it is not necessary to add an external decoupling capacitor, which not only reduces the number of components but also reduces the number of terminals on the CCD image sensor side. Can be reduced.

Further, by sharing the P-well of the N-type substrate, a substrate region for separating the P-well becomes unnecessary, so that the chip size of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an example of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a circuit diagram of the semiconductor device having a CCD image pickup device.

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 N-type substrate, 2 common P wells, 3 wirings, 4 pads, 102 CCD imaging device

Claims (4)

[Claims] At least an output unit second conductivity type well region in which an active element of an output stage is formed and a protection element second conductivity type well region in which a protection element is formed are formed on a first conductivity type substrate. In the semiconductor device, the output portion second conductivity type well region and the protection element second conductivity type well region are a common second conductivity type well region, and a wiring for transmitting an output signal and an element connected to the wiring are provided. Is formed in the common second conductivity type well region. 2. The semiconductor device according to claim 1, wherein said first conductivity type is N-type, and said second conductivity type is P-type. 3. The semiconductor device according to claim 1, wherein said first conductivity type is P-type, and said second conductivity type is N-type. 4. The semiconductor device according to claim 2, further comprising a CCD image pickup device having an electronic shutter function, wherein a signal from said CCD image pickup device is supplied to said output stage.