JPH10322024A - Build-up multilayer printed wiring board having non-penetrating via holes and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To provide a build-up multilayer printed wiring board excellent in connection reliability of a via hole, low in cost, and suitable for high-density wiring. SOLUTION: Via holes 4a and 4b filled with resin
And the interlayer insulating layer 3 is flattened, and the circuit 2a is formed on the flattened surface.
And a via hole pad 2b were formed. The interlayer insulating layer 3 needs to be flattened only once per layer, and the plating thickness does not increase, so that the circuit 2a can be miniaturized. Further, since the first via hole 4a and the second via hole 4b thereon are connected via the via hole pad 2b,
There is no decrease in plating roundness due to displacement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a build-up multilayer printed wiring board having a non-penetrating via hole.

[0002]

2. Description of the Related Art The use of non-through via holes (hereinafter simply referred to as via holes) as a connection structure between upper and lower wiring layers of a multilayer printed wiring board increases the degree of freedom in wiring design and is suitable for high-density wiring. I have. In order to achieve even higher density wiring, via holes are designed so that via holes and one via layer on the outer layer side of the via hole overlap with each other when viewed from the outer layer surface. A method for realizing such an arrangement is disclosed in
-36591, JP-A-7-307567,
JP-A-7-283538, JP-A-8-24207
No. 7, for example.

[0003] JP-A-2-36591 and JP-A-7-365
The method described in Japanese Patent No. 307567 discloses a first method in which an interlayer insulating layer 39a provided on a substrate 37 having a circuit 38a and a via hole pad 38b formed on the surface thereof, as schematically shown in the sectional view of FIG. A via hole is formed, and the via hole is made conductive by plating. Thereafter, a second via hole 40 is formed on the first via hole without filling the first via hole, and the first via hole is made conductive by plating 41 to electrically connect upper and lower circuits. The first via hole is formed on via hole pad 38b.

Further, the methods described in JP-A-7-283538 and JP-A-8-242077 are disclosed in FIG.
As schematically shown in the cross-sectional view of FIG. 1, a first via hole 45a is formed in an interlayer insulating layer 44 provided on a base material 42 on which, for example, a circuit 43a and a via hole pad 43b are formed. Then, the first via hole 45a, which has been made conductive by the first plating 46, is filled with an insulating resin or a conductive resin 47, flattened, and then subjected to the second plating 48 to form the circuit 4
9 is formed. According to this method, the second via hole 4
5b is connected to the planarized first via hole 45a via the second plating 48.

[0005]

In the method schematically shown in FIG. 8, the depth of the via hole 40 increases with each layer, and it is difficult to form an interlayer insulating layer on the interlayer insulating layer 39b and to planarize it. Becomes In addition, there is a problem that the positional deviation between the layers deteriorates the throwing power of the plating 41 of the via hole 40 and lowers the connection reliability.

According to the method schematically shown in FIG. 9, the second via hole 45b is connected to the planarized first via hole 45a via the second plating 48, so that the above problem can be avoided. it can. However, when the circuit 49 is formed by an etching method, the thickness of the first plating 46 and the thickness of the second plating 48 must be etched, so that miniaturization of the circuit 49 becomes difficult, and high An obstacle to density wiring.

Further, as shown in FIG. 10, when an interlayer insulating layer 52 is formed on a base material 50, the surface undulates due to the influence of the circuit 51. If the surface undulates in this way, the next time a circuit is formed, poor resolution of the resist and uneven etching will occur.
Flatten by polishing or the like. Also, when the filler is filled by printing, polishing the extra printed filler,
It is necessary to planarize by polishing or the like. Therefore, conventionally, flattening is required twice for each layer of the circuit, so that there is a problem that the process is complicated, the yield is reduced, and the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has an excellent connection reliability of via holes, is low-cost, and is suitable for high-density wiring. The aim is to provide a method.

[0009]

In order to achieve the above object, a build-up multilayer printed wiring board having a non-penetrating via hole according to the present invention is formed in an interlayer insulating layer and the interlayer insulating layer, and is made conductive by plating. The non-through via hole is flattened by an insulating resin, and a via hole pad that covers the circuit and the conductive via hole is formed on the flattened surface.

That is, as shown in FIG. 1, a first via hole 4a and an interlayer insulating layer 3 are flattened by an insulating resin 6, and a circuit 7a and a via hole pad 7b are formed on the flattened surface. . The second via hole 4b is connected to the planarized first via hole 4a via a via hole pad 7b. Further, in the build-up multilayer printed wiring board having a non-through via hole of the present invention, the resin filled in the non-through via hole and the surface of the interlayer insulating layer in which the non-through via hole is formed are flattened, and the flattened surface is formed. A via hole pad for covering the circuit and the via hole.

That is, as shown in FIG. 2, the first via hole 12a is filled with an insulating or conductive resin 14,
The interlayer insulating layer 11 and the insulating or conductive resin 14 are flattened, and a circuit 15a and a via hole pad 15b are formed on the flattened surface. In the example of FIG. 2, the via holes 12 a and 12 b are made conductive by the plating film 13.

Here, as shown in FIGS. 3 and 4, the circuit and the via hole pad may be formed by a full additive method. The via hole pad covering the circuit and the conductive via hole is formed of a single layer of plating film. Further, a method of manufacturing a build-up multilayer printed wiring board having a non-through via hole of the present invention,
Forming a non-through via hole in the interlayer insulating layer, forming a plating film on the non-through via hole and the interlayer insulating layer, removing a plating film other than around the non-through via hole; A step of applying an insulating resin inside the through via hole and on the interlayer insulating layer, a step of polishing the insulating resin until the surface of the non-through via hole is exposed, and a step of flattening; Forming a plating film on the resin and the non-penetrating via hole.

That is, as shown in FIG. 5, a step of applying an insulating resin 6 to the interlayer insulating layer 3 in which the via hole 4a is formed (FIG. 5E), and flattening the insulating resin 6 by plating. Forming the film 7 (FIG. 5F). Non-through via hole 4a rendered conductive by plating with interlayer insulating layer 3
A photosensitive resin or a thermosetting resin can be used as the insulating resin 6 for flattening. Further, by using the same resin as the interlayer insulating layer 3 as the insulating resin 6, it is possible to reduce material costs and simplify management.

In the case where the interlayer insulating layer is made of a photosensitive resin such as a photo via hole, a resin having both good resolution and good plating adhesion is required in the prior art. In that case, the margin of selection of materials and control of conditions in the manufacturing process is reduced. However, according to the present invention, it is possible to selectively use a resin having good resolution for the interlayer insulating layer and a resin having high plating adhesion for the insulating resin for planarization, and the conditions for the material selection and the manufacturing process are different. This will increase the margin of control, which will result in lower costs and higher yields. In addition, the same use is possible even when a via hole is formed by a method such as laser or plasma ashing.

The method of manufacturing a build-up multilayer printed wiring board having a non-through via hole according to the present invention comprises the steps of: forming a non-through via hole in an interlayer insulating layer; filling the non-through via hole with a resin; The method further includes a step of simultaneously polishing and flattening the resin filled in the non-through via hole and the interlayer insulating layer, and a step of forming a plating film on the flattened surface.

That is, as shown in FIG. 6, a step of filling an insulating or conductive resin 14 into a via hole 12a formed in the interlayer insulating layer 11 (FIG. 6D), And a step of simultaneously flattening the interlayer insulating layer 11 to form the plating film 15 (FIG. 6E). When the resin 14 filling the non-penetrating via hole 12a is an insulating resin, a photosensitive or thermosetting resin can be used. If the same resin as the interlayer insulating layer 11 is used, the cost of the material is reduced and the management is simplified. Can be achieved. When the resin 14 filling the non-penetrating via holes 12a is a conductive resin, a conductive paste containing metal particles such as copper and silver can be used.

According to the present invention, when a circuit is formed by etching, a fine circuit can be easily formed because the plating thickness of the via hole is not added to the plating thickness of the circuit and the via hole pad. In addition, since the first via hole and the second via hole formed thereon are connected via the via hole pad, there is no reduction in the plating coverage due to the misalignment of the upper and lower via holes. In addition, since the planarization per circuit layer can be performed only once, the process can be simplified.

When a circuit or a via hole pad is formed by a full additive method, a circuit layer is flat with a plating resist, and an interlayer insulating layer can be formed thereon with good flatness. For this reason, the flattening process can be simplified. As described above, according to the present invention, it is possible to provide a build-up multilayer printed wiring board having excellent connection reliability, low cost, and suitable for high-density wiring.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] An example of a method of manufacturing a build-up multilayer wiring printed wiring board according to the present invention will be described with reference to the process sectional view of FIG. In this example, a build-up multilayer wiring printed wiring board whose cross-sectional structure is schematically shown in FIG. 1 was manufactured.

Single-sided copper-clad glass epoxy laminate 1 cut to a required size (manufactured by Hitachi Chemical Co., Ltd .; MCL-E6)
7) An etching resist (manufactured by Hitachi Chemical Co., Ltd .; S-4)
25) is laminated, and the circuit width and the gap are in a pattern of 40 μm to 100 μm in steps of 10 μm and the diameter is 150
An exposure machine (manufactured by Oak Manufacturing Co .; HMW-59) through a photomask having a pattern of via hole pads of μm.
0, exposure amount 40 mJ / cm ² ), and a developing solution (sodium carbonate; 10 g / l) at 40 ° C. is 1.8 kgf / c.
After spraying for 30 seconds at a pressure of m ² , it was washed with water.

Subsequently, an etching solution (40 ° C.
(45 bar of iron) is spray-treated at a pressure of 1.2 kgf / cm ² for 90 seconds, washed with water, immersed in a stripping solution (sodium hydroxide; 25 g / l) at 40 ° C. for 2 minutes to remove the etching resist, washed with water, and dried. Thus, a circuit 2a and a via hole pad 2b were formed (FIG. 5A). Next, a 30 ° C. roughening solution (sulfuric acid 5 ml / l, ammonium persulfate 200 g /
1) for 2 minutes to form fine irregularities on the surfaces of the circuit 2a and the via hole pad 2b. After washing with water,
Oxide film forming solution at 0 ° C. (trisodium phosphate 30 g / l,
Sodium perchlorate 100g / l, sodium hydroxide 1
(2 g / l) for 5 minutes to obtain an oxide film on the uneven surface. Then, after washing with water, 1% with a reducing solution (dimethylaminoborane 10 g / l, sodium hydroxide 10 g / l) at 45 ° C.
After treating for 2 minutes to reduce the oxide film, it was washed with water and dried to obtain a redox film.

Next, as shown in Table 1 below, photosensitive resin A containing each component was printed and coated on a stainless steel screen of 15 / cm and dried in a drying oven at 80 ° C. for 30 minutes. An interlayer insulating layer 3 having a thickness of about 50 μm was formed.
Thereafter, a film mask is brought into close contact with the surface of the interlayer insulating layer 3 and irradiated with ultraviolet rays at 700 mJ / cm ² using an ultra-high pressure mercury lamp, and exposed to a developing solution (sodium carbonate;
g / l) at a pressure of 1.8 kgf / cm ² for 2 minutes, washed with water and cured in a drying oven at 150 ° C. for 30 minutes.
A first via hole 4a having a diameter of about 100 μm was formed (FIG. 5B).

Next, a plating catalyst solution (manufactured by Hitachi Chemical Co., Ltd .;
HB101B) for 5 minutes, washed with water, and then treated with an activating solution (ADP601, manufactured by Hitachi Chemical Co., Ltd.) for 5 minutes. Next, after washing with water, the plate is treated with a 38 ° C. flash copper plating solution (manufactured by Hitachi Chemical Co., Ltd .; CUST2000) for 30 minutes to form a plating film having a thickness of about 0.5 μm on the entire surface.
Dried. Subsequently, an electrolytic copper plating solution (copper sulfate 200 g /
l, in a drying oven at sulfate 10 g / l) for 60 minutes copper plating at a current density of 1.5A / dm ^2, the water washing after 170 ° C. 4
The coating was cured for 0 minutes to obtain a plating film 5 having a thickness of about 20 μm (FIG. 5C).

Next, the plating film 5 having a diameter other than about 150 μm around the via hole was removed by predetermined etching (FIG. 5D). Subsequently, a thermosetting resin B containing components as shown in the following Table 1 was applied by printing on a 24 mesh / cm stainless steel mesh screen, defoamed in vacuum, and cured in a drying oven at 170 ° C. for 90 minutes. Thus, an insulating resin 6 having a thickness of about 20 μm was obtained on the interlayer insulating layer 3. In this step, the inside of the first via hole 4a is filled with the insulating resin 6 (FIG. 5E).

Next, a polishing belt (manufactured by Sankyo Rikagaku Co., Ltd .; CC)
-400), and after flattening with a belt sander, 8
The mixture was treated for 5 minutes with an aqueous solution of permanganic acid (potassium permanganate 60 g / l) at 0 ° C and a pH of 14, washed with water and treated with a neutralizing solution (hydroxylamine sulfate 30 g / l) at 40 ° C for 5 minutes. Further, after washing with water, the plate was treated with a plating catalyst solution (HB101B, manufactured by Hitachi Chemical Co., Ltd.) for 5 minutes. After washing with water, the plate was treated with an activating solution (ADP601, manufactured by Hitachi Chemical Co., Ltd.) for 5 minutes. Next, after washing with water, the plate is treated with a 38 ° C. flash copper plating solution (manufactured by Hitachi Chemical Co., Ltd .; CUST2000) for 30 minutes to form a plating film having a thickness of about 0.5 μm on the entire surface.
Dried. Subsequently, an electrolytic copper plating solution (copper sulfate 200 g /
l, in a drying oven at sulfate 10 g / l) for 60 minutes copper plating at a current density of 1.5A / dm ^2, the water washing after 170 ° C. 4
The coating was cured for 0 minutes to obtain a plating film 7 having a thickness of about 20 μm (FIG. 5F).

Next, after repeating the steps of FIGS. 5A to 5F in the same manner, the step of FIG. 5A is further performed, and as shown in FIG. 1, the circuits 2a, 7a, 8a, A build-up multilayer printed wiring board including via-hole pads 2b, 7b, 8b and via-holes 4a, 4b filled with an insulating resin was obtained. The first via hole 4a and the interlayer insulating layer 3 are flattened by an insulating resin 6, and a circuit 7a and a via hole pad 7b are formed on the flattened surface. Second
Via hole 4b is formed on first via hole 4a, and is connected to planarized first via hole 4a via via hole pad 7b.

[0027]

[Table 1]

[Embodiment 2] Another example of a method of manufacturing a build-up multilayer wiring printed wiring board according to the present invention will be described. This example is the same as Example 1 except that the method of forming the insulating resin film 6 was different from Example 1, and a build-up multilayer wiring printed wiring board whose sectional structure is schematically shown in FIG. 1 was manufactured.

That is, (e) of the first embodiment shown in FIG.
In the step (2), instead of the thermosetting resin B in Table 1, the photosensitive resin A in Table 1 was applied by printing on a 24 mesh / cm stainless steel mesh screen, followed by vacuum defoaming. After that, exposure was performed by irradiating an ultraviolet ray at 700 mJ / cm ² with an ultra-high pressure mercury lamp, followed by curing in a drying oven at 150 ° C. for 30 minutes.
Then, an insulating resin 6 having a thickness of about 20 μm was obtained. Other steps were performed in the same manner as in Example 1 to obtain a build-up multilayer printed wiring board as shown in FIG.

[Embodiment 3] Another example of the method of manufacturing a build-up multilayer wiring printed wiring board according to the present invention will be described. This embodiment is different from the first embodiment except that the method of forming the interlayer insulating layer 3 and the method of forming the via hole are different from the first embodiment.
A build-up multilayer wiring printed wiring board shown in FIG. 1 was manufactured.

That is, (b) of the first embodiment shown in FIG.
Up to the step of forming the redox film in the same manner as in Example 1,
Thereafter, the thermosetting resin B shown in Table 1 was applied by printing on a stainless steel screen of 15 pieces / cm at 170 ° C.
Was cured in a drying furnace for 90 minutes to obtain an interlayer insulating layer 3 having a thickness of about 50 μm. Next, a pulse of an excimer laser was adjusted and irradiated so that the via hole pad 2b was exposed through a metal mask to form a first via hole 4a having a diameter of about 100 μm. Other steps were performed in the same manner as in Example 1 to obtain a build-up multilayer printed wiring board as shown in FIG.

[Embodiment 4] Another example of a method for manufacturing a build-up multilayer wiring printed wiring board according to the present invention will be described. In this example, a build-up multilayer printed wiring board whose sectional structure is schematically shown in FIG. 3 was manufactured using a glass epoxy laminate.

That is, instead of the single-sided copper-clad glass-epoxy laminate 1 shown in FIG. 5A of Example 1, a glass-epoxy laminate 17 (manufactured by Hitachi Chemical Co., Ltd .; LE-67N) as shown in FIG. ), An additive adhesive film (Hitachi Kasei Kogyo; AP-1530) is laminated, and ultraviolet rays are irradiated at 1.5 J / cm by a metal halide lamp.
^{2 After} irradiation, cure in a drying oven at 150 ° C. for 40 minutes to form an adhesive layer 18, treat with an aqueous solution of permanganic acid (potassium permanganate 60 g / l) at 80 ° C. and pH 14 for 10 minutes, and wash with water The mixture was treated with a neutralizing solution (hydroxylamine sulfate 30 g / l) at 40 ° C. for 5 minutes. Further, after washing with water, the plate is treated with a plating catalyst solution (HB101B, manufactured by Hitachi Chemical Co., Ltd.) for 5 minutes.
P601) for 5 minutes, washed with water and dried.

Next, a plating resist 19 (manufactured by Hitachi Chemical Co., Ltd .; SR-3000) is laminated, and a photomask having a pattern of 40 μm to 100 μm in a circuit width and a gap of 10 μm and a pattern of a via hole pad having a diameter of 150 μm is provided. Through an exposure machine (manufactured by Oak Manufacturing Co., Ltd .; HMW-590, exposure amount 250 mJ / cm ² ), and a developing solution at 40 ° C. (diethylene glycol monobutyl ether; 200 ml / l, borax; 8 g / l)
Was sprayed at a pressure of 1.8 kgf / cm ² for 90 seconds, washed with water and dried.

Next, an electroless copper plating solution of 70 ° C. and pH 12.5 (copper sulfate pentahydrate 10 g / l, EDTA 40 g /
l, polyethylene glycol 20g / l, formalin 2
ml / l), copper-plated for 12 hours, rinsed with water for 17 hours
The composition was cured in a drying oven at 0 ° C. for 40 minutes to form a circuit 20 a and a via-hole pad 20 b having a thickness of about 20 μm. Thereafter, the interlayer insulating layer 21 is formed in the same manner as in FIG.
Was formed, and a first via hole 22a having a diameter of 100 μm was formed in the interlayer insulating layer (see FIG. 3). In Example 1, since the interlayer insulating layer 3 was formed on the substrate 1 on which the unevenness was formed by the circuit 2a, the surface of the interlayer insulating layer 3 undulated as shown in FIG. 5B. The surface of the layer where the circuit 20a and the via hole pad 20b are formed is flat because the full additive method is employed. Therefore,
The surface of the interlayer insulating layer 21 formed thereon also becomes flat.

Next, a plating film having a thickness of 20 μm is formed on the interlayer insulating layer 21 in the same manner as in FIG.
In the same manner as in (d), the plating film having a diameter other than about 150 μm around the via hole was removed by etching. Thus, the first via hole 22 a was made conductive by the plating film 23.
Next, an insulating resin 24 having a thickness of about 20 μm was obtained on the interlayer insulating layer 21 in the same manner as in FIG. 5E, and flattened using a polishing belt. On top of that, the circuit 2a is formed by the full additive method similarly to the formation of the circuit 20a and the via hole pad 20b.
5a and a via hole pad 25b were formed, and the same steps were repeated to form a second via hole 22b on the first via hole 22a. After that, as in the case of the first via hole, the second via hole is made conductive by a plating film, the second via hole 22b is filled with an insulating resin, and the insulating resin surface is flattened. Circuit 26a and second via hole 2 by additive method
A via hole pad 26b on 2b was formed.

[Embodiment 5] Referring to the process sectional view of FIG.
Another example of the method for manufacturing a build-up multilayer wiring printed wiring board according to the present invention will be described. In this embodiment, FIG.
In this example, a build-up multilayer wiring printed wiring board schematically showing a cross-sectional structure was manufactured.

The steps from FIG. 6A to FIG. 6C are the same as the steps from FIG. 5A to FIG. First, as shown in FIG. 6A, a circuit 10a and a via hole pad 10b are formed on a single-sided copper-clad glass epoxy laminate 9 cut into a required size. Next, FIG.
As shown in FIG. 6A, an interlayer insulating layer 11 having a thickness of about 50 μm and a first via hole 12a having a diameter of about 100 μm are formed. Subsequently, as shown in FIG. A plating film 13 of 20 μm was formed.

Next, the thermosetting resin B shown in Table 1 was added to 25
The first via hole 12a was printed and filled with a metal mask having a thickness of 0 μm, and cured in a drying oven at 170 ° C. for 90 minutes to obtain an insulating resin 14 (FIG. 6D). Next, using a polishing belt (manufactured by Sankyo Rikagaku Co., Ltd .; CC-400), the surface is polished and flattened with a belt sander until the plating film other than the first via hole 12a disappears, and then permanganic acid at 80 ° C. and pH 14 is used. The mixture was treated with an aqueous solution (potassium permanganate 60 g / l) for 5 minutes, washed with water, and then treated with a neutralization solution (hydroxylamine sulfate 30 g / l) at 40 ° C for 5 minutes. After washing with water, a plating catalyst solution (HB101B, manufactured by Hitachi Chemical Co., Ltd.)
For 5 minutes, washed with water, and then treated with an activating solution (ADP601, manufactured by Hitachi Chemical Co., Ltd.) for 5 minutes.

Next, after washing with water, the resultant was treated with a 38 ° C. flash copper plating solution (manufactured by Hitachi Chemical Co., Ltd .; CUST2000) for 30 minutes to form a plating film having a thickness of about 0.5 μm on the entire surface, washed with water and dried. Subsequently, an electric copper plating solution (copper sulfate 200 g / l, sulfuric acid 10 g / l) was used to produce a current density of 1.5 A /
dm ² , copper plating for 60 minutes, washing with water, curing in a drying oven at 170 ° C. for 40 minutes, and plating film 15 having a thickness of about 20 μm.
Was obtained (FIG. 6E).

Next, after the processes of FIGS. 6A to 6E were performed in the same manner, the process of FIG. 6A was further performed. Thus, as shown in FIG. 2, the circuits 10a, 15a, 16a,
Via-hole pads 10b, 15b, 16b, and via-holes 12a, 12b filled with insulating resin 14
Was obtained. The via holes 12a and 12b and the interlayer insulating layer 11 are flattened,
Circuits 15a and 16a and via hole pads 10b and 15b are formed on the flattened surface. The second via hole 12b is formed so as to overlap the first via hole 12a, and is connected to the planarized first via hole 12a via the via hole pad 15b.

[Embodiment 6] Another example of a method of manufacturing a build-up multilayer wiring printed wiring board according to the present invention will be described. This embodiment is the same as the fifth embodiment except that the inside of the via hole is filled with a conductive resin instead of the insulating resin. That is, in the step of FIG. 6D of Example 5, printing and filling were performed by using a conductive paste (ACP-052, manufactured by Asahi Chemical Laboratories) instead of the thermosetting resin B, and the mixture was dried in a 170 ° C. drying oven. After curing for 30 minutes, a conductive resin 14 was obtained. Other processes were performed in the same manner as in Example 5 to obtain a build-up multilayer printed wiring board as shown in FIG.

[Embodiment 7] Another example of a method of manufacturing a build-up multilayer wiring printed wiring board according to the present invention will be described. This embodiment corresponds to the fifth embodiment in which the circuit and the via hole pad are formed by the full additive method as in the fourth embodiment.

FIG. 4 is a schematic sectional view of a build-up multilayer printed wiring board manufactured according to this embodiment. An adhesive layer 28 is formed on a glass epoxy laminate 27, and a circuit 30a and a via hole pad 30 are formed on the adhesive layer 28 by a fully additive method using a patterned plating resist 29.
b was formed. After the first via hole 32a provided in the interlayer insulating layer 31 thereon is made conductive by the plating film 33 and the inside of the first via hole 32a is filled with the thermosetting resin B or the conductive resin shown in Table 1, Polishing and flattening were performed until the plating film other than the first via hole 32a disappeared, and a circuit 35a and a via hole pad 35b were formed on the flattened surface by a full additive method. Similarly, a second via hole 32b made conductive by a plating film is formed in an interlayer insulating layer provided thereon, and the inside of the second via hole 32b is filled with an insulating resin or a conductive resin. The substrate 36 was polished and flattened until there was no plating film other than the second via hole 32b, and a circuit 36a and a via hole pad 36b were formed on the flattened surface by using a patterned plating resist 29 by a full additive method.

Comparative Example A comparative example will be described with reference to a process sectional view shown in FIG. FIGS. 11A and 11B are the same as FIGS. 5A and 5B of the first embodiment. That is, in FIG. 11A, a circuit 43a and a via hole pad 43b are formed by etching on a single-sided copper-clad glass epoxy laminate 53 cut to a predetermined size, and in FIG. Is formed on the interlayer insulating layer 44, and a diameter of about 10
A first via hole 45a of 0 μm was formed.

Next, a polishing belt (manufactured by Sankyo Rikagaku Co., Ltd .; CC)
Using (−400), the interlayer insulating layer 44 is flattened by a belt sander (FIG. 11C), and a first plating 46 having a thickness of about 20 μm is obtained by the same processing as that of FIG. (FIG. 11D). Subsequently, the thermosetting resin B shown in Table 1 was printed and filled with a 250 μm-thick metal mask.
The resin was cured in a drying oven at 0 ° C. for 90 minutes to obtain an insulating resin 47 (FIG. 11E). After flattening again with a belt sander, the plate was treated with a roughening solution (sulfuric acid 5 ml / l, ammonium persulfate 200 g / l) for 2 minutes at 30 ° C., further washed with water, and then electroplated with copper (200 g / l copper sulfate, 10 g / l)
Copper plating was performed at a current density of 1.5 A / dm ^{2 for} 30 minutes, washed with water, and cured in a drying oven at 170 ° C. for 40 minutes to obtain a second plating 48 having a thickness of about 10 μm (FIG. 11F). ).
Next, after performing the processing of FIGS. 11A to 11F in the same manner, the processing of FIG. 11A is further performed, and a build-up multilayer printed wiring board as shown in a schematic sectional view of FIG. Obtained.

[Continuity Inspection] In the build-up multilayer printed wiring boards manufactured in the above Examples 1 to 7 and Comparative Example, 10 circuits each having a circuit width and a gap of 40 μm to 100 μm were formed in three layers at intervals of 10 μm. The circuits in each layer are connected by via holes. These circuits were tested for continuity with an electric tester. Table 2 below shows the test results.
Shown in The numbers in Table 2 represent the number of disconnected or short-circuited circuits out of the ten circuits.

[0048]

[Table 2]

As can be seen from Table 2, in Examples 1 to 3, 5 and 6, the circuit width and the gap were 60
There is no disconnection or short circuit in the circuit from μm to 100 μm, and the circuit width and gap can be reduced to 60 μm. Similarly, in Examples 4 and 7 in which circuits are formed by the full additive method, the circuit width and gap can be reduced to a minimum of 50 μm without disconnection and short circuit, and the circuit width and the gap can be reduced to 50 μm. On the other hand, in the comparative example, since there is no disconnection or short circuit at a minimum of 80 μm, the circuit width and the gap can be reduced to only 80 μm.

An analysis of the broken or short-circuited portion of the comparative example shows that, for one case having a circuit width and a gap of 70 μm,
The via hole is broken, and the second plating 48 has a thickness of about 10 μm.
m. Circuit width and gap is 40 μm to 6
In the case of the 0 μm circuit, the most defective portion was a short circuit between the circuits, the footing of the circuit was large, and the circuit was not sufficiently etched. This is because the circuit thickness was about 30 μm, which is the sum of the thickness of the first plating 46 and the thickness of the second plating 48.

In Examples 1 to 3, 5 and 6 in which the circuit was formed by the etching method in the same manner as in the comparative example, the circuit having a circuit width and gap of 60 μm to 100 μm also had a footing. No, the circuit was formed neatly. For circuits with circuit widths and gaps of 40 μm and 50 μm,
All defective parts were short-circuited, and there was a slight tailing. In Examples 4 and 7, circuits with a circuit width and gap of 50 μm to 100 μm were formed neatly, and defective portions of 40 μm were both broken, resulting from poor resolution of the plating resist (residual development). Was to do. In Examples 1 to 7, there was no connection failure of the via hole.

[0052]

As described above, according to the present invention, the interlayer insulating layer needs to be flattened only once per layer, and the plating thickness does not increase, so that the circuit can be miniaturized by etching. In addition, since the first via hole and the second via hole are connected via the via hole pad, there is no decrease in the plating-related turning property due to the displacement. Therefore,
It is possible to provide a build-up multilayer printed wiring board having excellent via hole connection reliability, low cost, and suitable for high-density wiring.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an example of a build-up multilayer printed wiring board according to the present invention.

FIG. 2 is a schematic sectional view showing another example of a build-up multilayer printed wiring board according to the present invention.

FIG. 3 is a schematic sectional view showing another example of a build-up multilayer printed wiring board according to the present invention.

FIG. 4 is a schematic sectional view showing another example of the build-up multilayer printed wiring board according to the present invention.

FIG. 5 is a schematic cross-sectional view illustrating an example of a manufacturing process of a build-up multilayer printed wiring board according to the present invention.

FIG. 6 is a schematic sectional view illustrating another example of the manufacturing process of the build-up multilayer printed wiring board according to the present invention.

FIG. 7 is a schematic cross-sectional view of a substrate on which circuits and via hole pads are formed by a photoadditive method.

FIG. 8 is a schematic sectional view showing an example of a conventional build-up multilayer printed wiring board.

FIG. 9 is a schematic sectional view showing another example of a conventional build-up multilayer printed wiring board.

FIG. 10 is a diagram illustrating a state where the surface of an interlayer insulating layer undulates under the influence of a circuit.

FIG. 11 is a schematic cross-sectional view illustrating a manufacturing process of a comparative example.

[Explanation of symbols]

1, 9, 53 ... single-sided copper-clad glass epoxy laminate 2a, 7a, 8a, 10a, 15a, 16a, 20a,
25a, 26a, 30a, 35a, 36a, 38a, 4
3a, 49, 51 ... circuits 2b, 7b, 8b, 10b, 15b, 16b, 20b,
25b, 26b, 30b, 35b, 36b, 38b, 4
3b: Via hole pad 3, 11, 21, 31, 39, 44, 52 ... Interlayer insulating layer 4a, 12a, 22a, 32a, 45a: First via hole 4b, 12b, 22b, 32b, 45b: Second via hole 5 , 13, 23, 33 ... plating film 6, 24 ... insulating resin 14, 34, 47 ... insulating or conductive resin 17, 27 ... glass epoxy laminate 18, 28 ... adhesive layer 19, 29 ... plating resist 37 , 42, 50 Base material 40 Via hole 41 Plating 46 First plating 48 Second plating

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masashi Miyazaki 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture General-purpose Computer Division, Hitachi Ltd.

Claims (7)

[Claims] In a build-up multilayer printed wiring board having a non-penetrating via hole, an interlayer insulating layer and a non-penetrating via hole formed in the interlayer insulating layer and made conductive by plating are flattened by an insulating resin, and the flatness is obtained. A build-up multilayer printed wiring board, wherein a via hole pad for covering a circuit and the conductive via hole is formed on the surface that has been made conductive. 2. In a build-up multilayer printed wiring board having a non-penetrating via hole, a resin filled in the non-penetrating via hole and a surface of an interlayer insulating layer in which the non-penetrating via hole is formed are flattened. A via hole pad for covering a circuit and the via hole on a surface of the multi-layer printed wiring board. 3. The build-up multilayer printed wiring board according to claim 1, wherein at least one layer of the circuit and the via hole pad are formed by a full additive method. 4. The build-up multilayer printed wiring board according to claim 1, wherein the circuit and the via hole pad that covers the conductive via hole are formed of a single-layer plating film. 5. A method of manufacturing a build-up multilayer printed wiring board having a non-penetrating via hole, wherein a non-penetrating via hole is formed in the interlayer insulating layer, and a plating film is formed on the non-penetrating via hole and the interlayer insulating layer. A step of removing a plating film other than around the non-through via hole, a step of applying an insulating resin inside the non-through via hole and on the interlayer insulating layer, and applying the insulating resin to the non-through via hole. Manufacturing a build-up multilayer printed wiring board, comprising: a step of polishing and flattening until a surface is exposed; and a step of forming a plating film on the flattened insulating resin and the non-penetrating via hole. Method. 6. A method of manufacturing a build-up multilayer printed wiring board having a non-penetrating via hole, a step of forming a non-penetrating via hole in an interlayer insulating layer, a step of filling the non-penetrating via hole with a resin, Manufacturing a build-up multilayer printed wiring board, comprising: simultaneously polishing and flattening the resin and the interlayer insulating layer filled into the substrate; and forming a plating film on the flattened surface. Method. 7. The method for manufacturing a build-up multilayer printed wiring board according to claim 5, wherein at least one circuit is formed by a full additive method.