JPH10322178A - Semiconductor device - Google Patents

Abstract

An ASIC including a variable delay circuit which realizes a variable delay circuit which has a small minimum delay time and a small layout required area, is easy in design and delay time management, and is excellent in test and diagnostic performance. , Etc., to increase the test diagnosis accuracy. A variable delay circuit mounted on an ASIC or the like is provided, for example, by selectively outputting a substantial input signal i input via an input terminal i when a corresponding delay control signal c0 is at a low level. NAND gate N transmitting to x
A1, a NAND gate NA2 for selectively transmitting a substantial input signal j input via the input terminal j to the output terminal y, and a corresponding delay control signal c0 are alternatively set to a high level. A plurality of unit delays each including a NAND gate NA3 for selectively transmitting a substantial input signal i to an output terminal y, wherein the output terminal x and the input terminal i and the output terminal y and the input terminal j are respectively sequentially coupled in series. It is configured based on the circuit D0 and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to, for example, an ASIC (Application Specific Integrated Circuit) including a variable delay circuit, which is used for improving the delay characteristics of the variable delay circuit and increasing the efficiency of diagnostic processing. It is about effective technology.

[0002]

2. Description of the Related Art P-channel and N-channel MOSFs
CM formed by combining ET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is a general term for an insulated gate type field effect transistor)
There is an ASIC including an OS (complementary MOS) circuit as a basic element and including a variable delay circuit. The variable delay circuit is provided for setting / adjustment of a rising or falling timing or a pulse width of a predetermined internal control signal, and a delay characteristic thereof is as follows.
This has a relatively large influence on the cycle time and timing specifications of the ASIC and thus the digital system including it.

[0003]

In a conventional ASIC or the like, a variable delay circuit is, for example, shown in FIG. 5, FIG. 7 or FIG.
And each has its own problems. That is, in the variable delay circuit of FIG.
, Four or six inverters V3 to V4, V5 to V5
V8 or V9 to VE are connected in series, and three sets of delay circuits are provided in parallel, and output signals thereof, that is, internal signals Sa, Sb or Sc are converted to delay control signals c1 to c3.
Transfer gate G for selectively transmitting according to
1 to G3 are provided. As shown in FIG. 6, the input signal Si input from the preceding stage circuit of the ASIC includes the delay time tb1 of the buffer B1 and the two inverters V3 and V3.
4 delay time 2to (where to is the inverter V3
Represents the delay time per VE. The same applies hereinafter), that is, the signal is delayed by tb1 + 2to to become the internal signal Sa. Also, a buffer B1 and four inverters V5 to V8
Is delayed by the delay time tb1 + 4 to
And the internal signal Sc is delayed by the delay time tb1 + 6to of the buffer B1 and the six inverters V9 to VE.

For example, when the delay control signal c2 is alternatively set to a high level, only the corresponding internal signal Sb is transmitted to the buffer B2 via the transfer gate G2. The output signal So of the variable delay circuit is delayed by the gate and buffer delay time tb2.

In other words, in the method of FIG. 5, delay circuits are connected in parallel in accordance with the number of options of a desired delay time, and output signals, that is, internal signals Sa to Sc and the like are alternatively selected by transfer gates G1 to G3. The desired delay time is obtained by selection. However, as the performance of the ASIC increases and the number of delay time options increases, the transfer of the input side buffer B1 having a large number of fan-outs and its output terminal is logically coupled. The output load capacity of the gates G1 to G3 increases,
The minimum delay time increases. In addition, the arrangement positions of the plurality of delay circuits having different numbers of inverter stages and the relative positions of the branch points and the logical connection points are dispersed, and the wiring capacitances are different, so that it becomes difficult to manage the delay time of each delay circuit. It is difficult to obtain the delay characteristic of

On the other hand, in the variable delay circuit shown in FIG. 7, variable capacitors C1 to C4 are provided between output terminals of, for example, four inverters VF to VI connected in series and the ground potential of the circuit. Each of the variable capacitors includes three capacitors Ca to Ca whose lower electrodes are commonly coupled, as represented by the variable capacitor C1 at the bottom of FIG.
Cc. The upper electrodes of these capacitors are commonly coupled via switches Q1 to Q3 which are selectively turned on in response to the high level of the corresponding delay control signals c1 to c3. Needless to say, the delay times of the inverters VF to VI increase as the capacitance values of the corresponding variable capacitors C1 to C4 increase.

For these reasons, in the method of FIG. 7, the required number of elements of the variable capacitors C1 to C4 increases as the number of options of the desired delay time increases, and the required area of the layout increases, and the signal is fixed. Since the number of inverter stages to be passed is large, the minimum delay time of the variable delay circuit increases. Also, in consideration of the ASIC test / diagnosis processing, the conventional test method uses the variable capacitors C1 to C1.
The disconnection of the portion C4 cannot be detected, and the test diagnostic accuracy of the ASIC decreases.

Next, in the case of FIG. 8, the variable delay circuit includes four inverters VJ to VM connected in series, each of which is a P-channel type current control provided on its power supply voltage side. MOSFETs P1 to P4
And N-channel type current control MOSFETs N1 to N4 provided on the ground potential side. Of these, MOS
A predetermined current control signal icp is commonly supplied to the gates of the FETs P1 to P4 from a control circuit (not shown) of the ASIC, and the current control signal icn is commonly supplied to the gates of the MOSFETs N1 to N4. Thereby, the inverters VJ to VJ are controlled according to the potentials of the current control signals icp and icn.
The operating current of the VM is controlled, and the delay time of the delay circuit including these inverters is controlled.

However, in this method, the current control MOS
Since the current control signals icp and icn supplied to the gates of the FETs P1 to P4 and N1 to N4 are so-called analog quantities, they can be applied to macro cells and the like.
The SIC designer cannot combine existing standard gates to configure the ASIC, and the design man-hour of the ASIC increases. Further, a current control MOS is provided in the power supply path of the inverters VJ to VM.
By adding the FETs P1 to P4 and N1 to N4, the so-called power supply impedance of each inverter increases, and the minimum delay time as a variable delay circuit increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a variable delay circuit which has a small minimum delay time and a small required layout area, is easy to design and manage the delay time, and is excellent in test diagnostics. It is another object of the present invention to increase the speed of an ASIC or the like including a variable delay circuit and improve the test and diagnosis accuracy.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a variable delay circuit mounted on an ASIC or the like transmits a first input signal input via a first input terminal to a first output terminal when a corresponding delay control signal is set to a low level, for example. A first logic gate, a second logic gate for transmitting a substantial second input signal input via the second input terminal to a second output terminal, and a corresponding delay control signal. And a third logic gate for transmitting a substantial first input signal to the second output terminal when the signal is alternatively set to a high level, and the first output terminal and the first input terminal; A plurality of unit delay circuits in which a second output terminal and a second input terminal are respectively sequentially coupled in series; and a delay amount control signal of a predetermined bit is decoded and the corresponding delay control signal is selectively set to a high level, for example. And delay control times The door to configure to the original.

According to the above-described means, a variable delay circuit having substantially the same reciprocating signal path can be constituted only by stacking an arbitrary number of unit delay circuits having the same pattern. Thereby, the minimum delay time is small corresponding to the delay time of one or two logic gates of the unit delay circuit provided at the top, the layout required area is small, and the design and the management of the delay time are easy. In addition, it is possible to realize a variable delay circuit excellent in test diagnostics. As a result, the timing design of an ASIC or the like including a variable delay circuit can be facilitated, the speed thereof can be increased, and the test diagnosis accuracy can be increased.

[0014]

FIG. 1 is a block diagram showing one embodiment of a variable delay circuit to which the present invention is applied.
FIG. 2 is a circuit diagram of the first embodiment of the unit delay circuit D0 constituting the variable delay circuit of FIG. 1, and FIG. 3 is a circuit diagram of the delay circuit of one embodiment of the variable delay circuit of FIG. A characteristic diagram is shown. The configuration and operation of the variable delay circuit of this embodiment and the features thereof will be described with reference to these drawings. Although not particularly limited, the variable delay circuit of this embodiment is mounted on an ASIC, and is used for setting / adjusting a rising or falling timing or a pulse width of a predetermined internal control signal. The circuit elements constituting each block in FIG. 1 are formed on one semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique. In the following circuit diagrams, MOSFETs with an arrow at the channel (back gate) portion are P
It is of a channel type and is distinguished from an N-channel MOSFET without an arrow. Further, in the following description, with reference to the unit delay circuit D0 in FIG.
The specific configuration of the unit delay circuits D0 to Dn will be described.

In FIG. 1, the variable delay circuit of this embodiment includes n + 1 unit delay circuits D0 to Dn, each of which has two input terminals i (first
Input terminals) and j (second input terminal) and two output terminals x (first output terminal) and y (second output terminal)
And one delay control terminal c. A predetermined internal control signal, that is, an input signal Si is supplied to an input terminal i of the first-stage unit delay circuit D0 from a previous-stage circuit (not shown) of the ASIC, and an output terminal x thereof is connected to the next-stage unit delay circuit D1.
To the input terminal i. The input terminal j is
The output signal at the output terminal y is coupled to the output terminal y of the unit delay circuit D1 at the next stage, and is supplied to the subsequent circuit of the ASIC as the output signal So of the variable delay circuit.

The output terminal x of the second-stage unit delay circuit D1
Is coupled to the input terminal i of the third-stage unit delay circuit D2, and its input terminal j is coupled to the output terminal y of the third-stage unit delay circuit D2. Hereinafter, each unit delay circuit has its output terminal x coupled to the input terminal i of the next unit delay circuit, and its output terminal y connected to the input terminal j of the preceding unit delay circuit.
Are sequentially connected in series. The output terminal x of the last-stage unit delay circuit Dn is coupled to its input terminal j. The delay control terminals c of the unit delay circuits D0 to Dn are supplied with corresponding delay control signals c0 to cn from the delay control circuit DCTL, respectively.
TL includes m + 1 from a control circuit (not shown) of the ASIC.
Bit delay amount control signals dc0 to dcm are supplied.

The delay control circuit DCTL decodes the delay amount control signals dc0 to dcm and outputs the delay control signals c0 to ccm.
The bit corresponding to n is alternatively set to the high level. As a result, the delay control signals c0 to cn are normally all at the low level (first logic level), and the delay amount control signals dc
When 0 to dcm are the corresponding combinations, they are selectively and alternatively set to the high level (second logic level).

Here, each of the unit delay circuits D0 to Dn has a first logic gate, that is, a NAND (NAND) gate NA1 as represented by the unit delay circuit D0 in FIG.
(A first NAND gate), a second logic gate, that is, a NAND gate NA2 (a second NAND gate), and a third logic gate, that is, a NAND gate NA3 (a third NAND gate). The input signal i (first input signal), that is, for example, Si is supplied to one input terminal of the NAND gate NA1 through the input terminal i. The other input terminal is supplied with a delay control signal c, that is, for example, c0 from the delay control circuit DCTL via the delay control terminal c, and outputs an output signal of the unit delay circuit D0 via the output terminal x. x (first output signal). In addition,
The NAND gates NA1 to NA3 are designed to have the same delay time td.

Next, an input signal j (a second input signal), that is, an output signal y of, for example, a second-stage unit delay circuit D1 is supplied to one input terminal of the NAND gate NA2 via an input terminal j. . An output signal of the NAND gate NA3 is supplied to the other input terminal, and the output signal becomes an output signal y (second output signal) via the output terminal y, for example, an output signal So of a variable delay circuit. . In addition,
As will be apparent from the following description, the output signal of the NAND gate NA3 substantially corresponds to an inverted signal of the input signal i,
The input signal j corresponds to a substantially inverted signal of the input signal i by the NAND gate NA1. Therefore, the NAND gate NA2 is substantially a so-called negative logic OR (OR).
It will function as a gate.

An input signal i, for example, Si is supplied to one input terminal of the NAND gate NA3 via the input terminal i. The other input terminal is supplied with a corresponding delay control signal c, that is, an inverted signal of, for example, c0 by the inverter V1, and the output signal is supplied to the other input terminal of the NAND gate NA2.

The corresponding delay control signal c, for example, c0
Is at a low level, in the unit delay circuit D0, the NAND gates NA1 and NA2 are in the transmission state, and the NAND gate NA3 is in the non-transmission state. Therefore, the input signal i, for example, Si is delayed and inverted by the delay time td by the NAND gate NA1 and transmitted to the output terminal x. Further, the input signal j, that is, the output signal y of the second-stage unit delay circuit D1 is delayed and inverted by the delay time td by the NAND gate NA2 and transmitted to the output terminal y, and the output signal y, that is, the output signal of the variable delay circuit is output. So.

On the other hand, when the corresponding delay control signal c, that is, for example, c0 is alternatively set to a high level, in the unit delay circuit D0, the NAND gates NA1 and NA2 are set to the non-transmission state, and the NAND gate NA3 is set to the transmission state instead. It is said. Therefore, the input signal i, for example, Si is delayed / inverted by the NAND gate NA3 for the delay time td and transmitted to the other input terminal of the NAND gate NA2, and further delayed / inverted by the delay time td and outputted to the output terminal. transmitted to y.

As described above, the input signal Si input to the head of the variable delay circuit, that is, the input terminal i of the first-stage unit delay circuit D0 is input from the output terminals x of the series-coupled unit delay circuits D0 to Dn. The signals are sequentially delayed and transmitted through the terminal i in the normal order. Then, after the corresponding bits of the delay control signals c0 to cn are turned back by the unit delay circuit which is alternatively set to the high level, the output terminals y of the unit delay circuits D0 to Dn are connected via the input terminal j. The signals are sequentially delayed and transmitted in reverse order, and finally output from the output terminal y of the first-stage unit delay circuit D0 as the output signal So of the variable delay circuit. In addition, in each unit delay circuit, the signal to be transmitted including the time of folding is inverted twice each, so that signal transmission and reception are always performed at the same logic level as the input signal Si.

Therefore, the input signal Si and the output signal S
The phase difference between o, that is, the delay time Td of the variable delay circuit as a whole is represented by the following equation, where k is the number of stages of the unit delay circuit to be folded, and td is the delay time of the NAND gates NA1 to NA3 of each unit delay circuit. k × td + k × td = 2 × k × td, and when the unit delay time δ of the unit delay circuits D0 to Dn is δ = 2 × td, Td = k × δ.

As a result, the delay characteristic of the variable delay circuit is
As shown in FIG. 3, the minimum delay time, that is, the delay time Td when the delay control amount by the delay amount control signals dc0 to dcm is zero is δ, and the unit change of the delay time with respect to the unit change amount Δ of the delay control amount It becomes a step-shaped straight line with the amount δ, and the maximum delay time Tdmax is Tdmax = (n + 1) × δ.

In this embodiment, the unit delay circuits D0 to Dn constituting the variable delay circuit are all of the same circuit configuration, each of which shares the outward and return paths of the signal transmission path for the same period. In addition, by sharing and standardizing the layout pattern of these unit delay circuits, an arbitrary number of them can be stacked and a variable delay circuit having an arbitrary maximum delay time Tdmax can be easily realized. At this time, the minimum delay time as the variable delay circuit is, as described above, the unit delay circuits D0 to D
n unit delay time δ, for example, 100 to several hundred ps
(Picoseconds), and the unit change amount of the delay time with respect to the unit control amount Δ of the delay amount control signal can also be the unit delay time δ. Further, even when a variable delay circuit is configured by stacking a large number of unit delay circuits, a loopback test can be performed by designating an arbitrary unit delay circuit by designating the delay amount control signals dc0 to dcm. , Its normality can also be confirmed.

As a result, the minimum delay time is small corresponding to the delay time of one or two logic gates of the unit delay circuit provided at the top, and the layout required area is small.
It is possible to realize a variable delay circuit that is easy to design and manage delay time and has excellent test diagnosis performance, thereby facilitating the timing design of an ASIC including a delay circuit, speeding up the test, and improving the test diagnosis. Accuracy can be increased.

FIG. 4 is a circuit diagram of a second embodiment of the unit delay circuit D0 constituting the variable delay circuit of FIG. Since this embodiment basically follows the embodiment of FIG. 2, the description will be added only to the portions different from this.

In FIG. 4, the unit delay circuit D0 of this embodiment includes three clocked inverters CV1 (first logic gate), CV2 (second logic gate) and CV2.
3 (third logic gate). The input terminal of the clocked inverter CV1 is coupled to the input terminal i (first input terminal) of the unit delay circuit D0, and the output terminal is coupled to the output terminal x (first output terminal). Also,
The input terminal of clocked inverter CV2 is coupled to input terminal j (second input terminal) of unit delay circuit D0, and its output terminal is coupled to output terminal y (second output terminal). The input terminal of clocked inverter CV3 is coupled to input terminal i, and its output terminal is coupled to output terminal y. The inversion control terminals of the clocked inverters CV1 and CV2 are supplied with the delay control signal c, that is, for example, c0.
An inverted signal from the inverter V2 is supplied.

Thus, the clocked inverter CV1
Is set to the transmission state by setting the corresponding delay control signal c, that is, for example, c0 to a low level (first logical level), and the input signal i (first input signal) at the input terminal i, that is, for example, Si The signal is transmitted to the output terminal x as an output signal x (first output signal). Similarly, the clocked inverter CV2 is selectively brought into the transmission state by setting the corresponding delay control signal c, that is, for example, c0 to a low level, and the input signal j (second input signal) at the input terminal j, that is, for example, the second The output signal y of the stage unit delay circuit D1 is used as an output signal y (second output signal) at the output terminal y.
To communicate.

On the other hand, the clocked inverter CV3 is selectively brought into a transmission state by setting the corresponding delay control signal c, that is, for example, c0 to a high level (second logic level), and the input signal i at the input terminal i, that is, For example, Si is returned to the output terminal y as it is as the output signal y and transmitted.

As a result, in this embodiment, the same operation and effect as in the embodiment shown in FIG. 2 can be obtained, whereby the speed of an ASIC or the like including a delay circuit can be further increased, and the test and diagnosis accuracy can be improved. Can be increased. In the case of this embodiment, since the logic level of the delayed / transmitted signal remains inverted at the time of folding, the output signal y of the first-stage unit delay circuit D0, that is, the output signal So is converted by an inverter or the like. I need to flip it again. Therefore, the minimum delay time Tdmin of the variable delay circuit including the unit delay circuit D0 is equal to the delay time of the inverter t.
When the delay time of the clocked inverters CV1 to CV3 is td, Tdmin = td + tdo, and the unit delay amount Tdδ of the delay time of the variable delay circuit with respect to the unit control amount Δ of the delay amount control signal is Tdδ = 2. × td. The minimum delay time and the unit delay amount are reduced to about one half as compared with the case where the unit delay circuit D0 of FIG. 2 is used.

In the unit delay circuit of this embodiment, when the clocked inverter CV1 is in a non-transmitting state, its output terminal x is in a high impedance state, and the clocked inverters CV1 and CV2 of the subsequent unit delay circuit are provided.
May flow through current. To cope with this, each unit delay circuit is provided with a means (not shown) for preventing the input terminal i from being in a floating state.

The operation and effect obtained from the above embodiment are as follows. (1) A variable delay circuit mounted on an ASIC or the like is connected to a first input terminal through a first input terminal when a corresponding delay control signal is set to a low level, for example. A first logic gate for transmitting to a second output terminal of the first logic gate, and a second logic gate for transmitting a substantial second input signal inputted through the second input terminal to a second output terminal at this time. And a third logic gate for transmitting a substantially first input signal to a second output terminal when the corresponding delay control signal is, for example, alternatively set to a high level. A plurality of unit delay circuits in which the first input terminal, the second output terminal, and the second input terminal are sequentially coupled in series, respectively, and a delay amount control signal of a predetermined bit is decoded and the corresponding delay control signal is converted into, for example, Alternatively high level By configuring the delay control circuit based on
By stacking an arbitrary number of unit delay circuits having the same pattern, it is possible to easily form a variable delay circuit having substantially the same reciprocating signal path.

(2) According to the above item (1), the minimum delay time is small corresponding to the delay time of one or two logic gates of the unit delay circuit provided at the top, the layout required area is small, and In addition, it is possible to obtain a variable delay circuit that can easily manage the delay time and can realize a test diagnostic performance. (3) According to the above items (1) and (2), the speed of an ASIC or the like including a variable delay circuit can be increased, and the effect of improving the test diagnosis accuracy can be obtained.

(4) In the above items (1) to (3),
By configuring the first to third logic gates with clocked inverters, the minimum delay time and the unit delay amount of the variable delay circuit can be further reduced, and A including the variable delay circuit
The effect is obtained that the speed and performance of SIC and the like can be further improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the delay control signal c0 and the like can be input to the unit delay circuits D0 to Dn, for example, every other signal or every predetermined number. In this case, in the unit delay circuit to which the delay control signal is not input, it is necessary to fix the delay control terminal c to a low level. Delay control signals c0 to cn
Can be inverted by exchanging the transmission condition of each logic gate of the unit delay circuits D0 to Dn.

2 and 4, the unit delay circuit D0
To Dn can be configured by combining, for example, a NOR gate, or can be configured by, for example, combining a transfer gate and an inverter.
Further, in the embodiment of FIG. 4, the first-stage unit delay circuit D0
May be provided, for example, between the output terminal of the clocked inverter CV3 and the output terminal y of the unit delay circuit. In FIG. 3, the specific delay characteristics of the variable delay circuit are just examples, and do not limit the gist of the present invention.

In the above description, the invention made mainly by the present inventor is referred to as the application field AS
The case where the present invention is applied to an IC and its variable delay circuit has been described. However, the present invention is not limited to this.
The present invention can be applied to various memory integrated circuits including various variable delay circuits, various logic integrated circuit devices, microcomputers, and the like. The present invention can be widely applied to a semiconductor device including at least a variable delay circuit and a device or a system including such a semiconductor device.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a variable delay circuit mounted on an ASIC or the like is connected to a first output terminal via a first input terminal when a corresponding delay control signal is set to a low level, for example. A first logic gate for transmitting a substantially second input signal, which is then input via a second input terminal, to a second output terminal, and a corresponding delay. A third logic gate for transmitting a substantially first input signal to a second output terminal when the control signal is alternatively set to a high level, for example, and the first output terminal and the first logic gate. A plurality of unit delay circuits in which an input terminal, a second output terminal, and a second input terminal are sequentially connected in series, respectively, and a delay amount control signal of a predetermined bit is decoded and the corresponding delay control signal is selected, for example, as an alternative. To a high level And a control circuit that constitutes the basis stacked to any number of unit delay circuit that is the same pattern can be reciprocally signal path is easily configured substantially the same variable delay circuit. Thereby, the minimum delay time is small corresponding to the delay time of one or two logic gates of the unit delay circuit provided at the top, the layout required area is small, and the design and the management of the delay time are easy. In addition, a variable delay circuit excellent in test diagnostics can be easily realized. As a result, the timing design of an ASIC or the like including a variable delay circuit can be facilitated, the speed thereof can be increased, and the test diagnosis accuracy can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a variable delay circuit to which the present invention is applied.

FIG. 2 is a circuit diagram showing a first embodiment of a unit delay circuit included in the variable delay circuit of FIG.

FIG. 3 is a delay characteristic diagram showing one embodiment of the variable delay circuit of FIG. 1;

FIG. 4 is a circuit diagram showing a second embodiment of the unit delay circuit included in the variable delay circuit of FIG. 1;

FIG. 5 is a circuit diagram showing an example of a conventional variable delay circuit.

FIG. 6 is a signal waveform diagram illustrating an example of the variable delay circuit of FIG. 5;

FIG. 7 is a circuit diagram showing another example of the conventional variable delay circuit.

FIG. 8 is a circuit diagram showing still another example of the conventional variable delay circuit.

[Explanation of symbols]

Si: input signal, So: output signal, D0 to Dn
Unit delay circuit, i, j ... input terminal, x, y ... output terminal, c ... delay control terminal, c0 to cn ... delay control signal, DCTL ... delay control circuit, dc0 to dcm ... delay amount Control signal. Δ: unit delay control amount, δ: unit delay amount tb1 to tb2: buffer delay time, to: unit delay time. icp, icn... current control signals. NA1
~ NA3 ... NAND gate, V1 ~ VM ...
... Inverters, B1-B4 ... Buffers, G1-G3 ...
... Transfer gate, C1-C4, Ca-Cc ... Capacitor, Q1-Q3 ... Switch MOSFET, CV
1 to CV3 clocked inverters, P1 to P8
P-channel MOSFETs, N1 to N8... N-channel MOSFETs.

Claims (4)

[Claims] 1. A first input terminal to which a first input signal is input, a second input terminal to which a second input signal is input, and a first output to which a first output signal is output. A second output terminal from which a second output signal is output, a delay control terminal to which a delay control signal is input, and substantially when the corresponding delay control signal is at a first logic level. A first logic gate for selectively transmitting the first input signal as the first output signal to the first output terminal, substantially when the corresponding delay control signal is at a first logic level A second logic gate for selectively transmitting the typical second input signal as the second output signal to the second output terminal, and the corresponding delay control signal at a second logic level. When the substantial first input signal is selectively used as the second output signal The first output terminal and the first input terminal, and the second output terminal and the second input terminal of the plurality of unit delay circuits each including a third logic gate transmitting to the second output terminal; A semiconductor device comprising a variable delay circuit sequentially connected in series. 2. The first logic gate according to claim 1, wherein one input terminal of the first logic gate is coupled to the first input terminal, and the first logic gate receives the delay control signal corresponding to the other input terminal; An output terminal comprising a first NAND gate coupled to the first output terminal; the second logic gate having one input terminal coupled to the second input terminal; A second NAND gate having a terminal coupled to the second output terminal, wherein the third logic gate has one input terminal coupled to the first input terminal and the other input gate coupled to the other input terminal. A semiconductor device receiving an inverted signal of the delay control signal corresponding to the terminal, and having an output terminal formed of a third NAND gate coupled to the other input terminal of the second NAND gate. . 3. The first logic gate of claim 1, wherein an input terminal of the first logic gate is coupled to the first input terminal, an output terminal of the first logic gate is coupled to the first output terminal, and A first clocked inverter selectively transmitted when the delay control signal is set to a first logic level, wherein the second logic gate has an input terminal connected to the second input. A second clocked inverter coupled to the terminal, the output terminal of which is coupled to the second output terminal, and selectively activated when the corresponding delay control signal is at a first logic level. Wherein the third logic gate has an input terminal coupled to the first input terminal, an output terminal coupled to the second output terminal, and a corresponding delay control signal. Second logical level A semiconductor device comprising a third clocked inverter which is selectively set to a transmission state when set to a bell. 4. The delay control according to claim 1, wherein the variable delay circuit decodes a predetermined delay amount control signal and selectively sets the corresponding delay control signal to an effective level. A semiconductor device including a circuit, wherein the semiconductor device is an ASIC having a CMOS logic circuit as a basic element.