JPH10322194A - Frequency divider circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the basic clock frequency and to reduce the power consumption by using a means which generates two 1/N divided clocks having their phases shifted from each other by an N/2 basic clock period, based on two output timings of an N-notation counter operating by a basic clock and a means which synthesizes those two divided clocks to produce a 2/N divided clock frequency of the basic clock. SOLUTION: An AND-A decodes the count value 4 of a quinary counter 1 and changes the output of the counter 1 into H from L. An FF-A latches the output of the AND-A at the leading edge of a basic clock CLK (f). Thus, the output of the AND-A is delayed by one clock period and a 1/5 divided clock CLKa (f/5) is outputted. Then the output of an AND-B is delayed by a 1/2 clock period, and a 1/5 divided clock CLKb (f/5) is outputted. The phase difference between clocks CLKa and CLKb becomes 5/2, and a 2/5-divided clock is obtained by a synthesizing circuit OR-A against the clock CLK (f).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency dividing circuit for dividing the frequency of an input basic clock by 2 / N (N is an odd number of 3 or more).

[0002]

2. Description of the Related Art Conventionally, as such a 2 / N frequency dividing circuit, a PLO (Phase Locked Oscillator) circuit and a 1 / N
A frequency divider (which can be easily obtained) is used. When a basic clock having a frequency f [Hz] is CLK (f), a basic circuit is provided by a PLO circuit having an oscillation frequency 2f. Double frequency clock C of clock CKL (f)
LK (2f) is generated, and this CLK (2f) is frequency-divided by 1 / N by a 1 / N frequency divider, thereby obtaining 2 / CLK (f).
The N-divided clock CLK (2f / N) was generated.

[0003] Such a 2 / N dividing circuit is used in an optical transmission system when data received at a transmission rate f [bps] is transmitted at a transmission rate 2 f / N [bps].

[0004]

However, in the above-mentioned conventional 2 / N frequency dividing circuit, since a PLO circuit and a 1 / N frequency divider operating at a frequency 2f twice the basic clock are used, the basic clock frequency f increases (Equation 1)
00 [MHz] or more), there is a problem that the frequency dividing circuit cannot be easily realized and the power consumption is large.

The present invention has been made to solve such a conventional problem, and has as its object to expand the applicable basic clock frequency range and reduce power consumption.

[0006]

In order to achieve the above object, a frequency dividing circuit according to the present invention operates at either a rising edge or a falling edge of a basic clock.
(N is an odd number of 3 or more) base counter and two (1 / N) clocks whose phases are shifted from each other by (N / 2) clock periods of the basic clock based on the output timing of the two count values of the N-base counter. A) frequency dividing means for generating a frequency-divided clock; and synthesizing means for generating a (2 / N) frequency-divided clock of the basic clock by synthesizing the two (1 / N) frequency-divided clocks. It is characterized by.

In a frequency dividing circuit according to a second aspect of the present invention, the frequency dividing means is arranged such that the frequency dividing means counts i (i is 0 to 0) of the N-ary counter.
A first decoding circuit for decoding an integer of any of N−1, and a count value j (j is 0 to 0) of the N-ary counter.
N-1), a first latch circuit for latching a decode output of the first decode circuit at a rising edge of the basic clock, and a second decode circuit. A second latch circuit for latching a decode output of the circuit at a falling edge of the basic clock, wherein the synthesizing means includes a latch output of the first latch circuit and a latch output of the second latch circuit. , And a logical OR gate having the input as an input.

According to a third aspect of the present invention, in the frequency dividing circuit according to the second aspect, when the N-ary counter operates at a rising edge of a basic clock, the count values i and j are j = i− (N -1) / 2 or j = i + (N + 1) / 2
And if the N-ary counter operates on the falling edge of the basic clock, j = i−
(N + 1) / 2 or j = i + (N-1) / 2, and the first and second decoding circuits each comprise an AND gate that receives the count output of the N-ary counter as an input. The first and second latch circuits are each formed of a D flip-flop.

According to a fourth aspect of the present invention, in the frequency dividing circuit, the N is 5
The above-mentioned odd number, wherein the frequency dividing means determines that the count value of the N-ary counter is p (p is any integer from 0 to N-1)
And a first gate circuit that gates the basic clock during a period that is the next count value, and the count value of the N-ary counter is q (q is any integer from 0 to N−1).
And a second gate circuit that gates the inverted clock of the basic clock for a period that is the next count value, wherein the synthesizing means outputs the output of the first gate circuit and the output of the second gate circuit. An OR gate having an output as an input, operating at a rising edge or a falling edge of an output clock of the OR gate, connecting an input terminal to a negative-phase latch output terminal, and connecting a positive-phase latch output terminal to the ( 2 / N) a latch circuit serving as an output terminal of the frequency-divided clock, wherein the count values p and q are q = p− (N + 1) when the N-ary counter operates at the rising edge of the basic clock. ) / 2 or q = p + (N-1) / 2
Is satisfied, and when the N-ary counter operates on the falling edge of the basic clock, q = p−
(N-1) / 2 or q = p + (N + 1) / 2.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment FIG. 1 is a circuit diagram showing a frequency dividing circuit according to a first embodiment of the present invention. The frequency dividing circuit where N = 5, that is, the basic clock CLK (f) having a frequency f is 2/5. This is a frequency dividing circuit for dividing the frequency.

The frequency dividing circuit shown in FIG.
TA, AND gates AND-A, AND-B and AND-C, and D flip-flops FF-A and FF
-B and two-input OR gates OR-A, OR-B and O
It has an RC and a two-input NOR gate NOR-A.

CNT-A has three count output terminals Q
A, QB, QC, a clock input terminal to which the basic clock CLK (f) is input, and a reset input terminal RESET
And operates at the rising edge of the basic clock CLK (f). Output terminal QA is LSB terminal, output terminal Q
C is an MSB terminal.

The AND-C has three input terminals, a first (inverted) input terminal is connected to the output terminal QA of the CNT-A, and a second (inverted) input terminal is connected to the output terminal QB. The third (non-inverting) input terminal is connected to the output terminal QC. OR-B has a first input terminal AND
-C, the second input terminal is connected to the external reset input terminal E-RST, and the output terminal is CNT.
-A is connected to the reset terminal RESET.

NOR-A has a first input terminal CNT-A.
A is connected to the output terminal QA, and the second input terminal is connected to the output terminal QB. The FF-A has the data input terminal D connected to the output terminal of the NOR-A, and operates at the falling edge of the basic clock CLK (f). A
The ND-A has a first input terminal connected to the (positive-phase) data output terminal Q of the FF-A and a second input terminal to which the basic clock CLK (f) is input. AND-B has a first (non-inverted) input terminal connected to the output terminal QB of the CNT-A, and a second (inverted) input terminal connected to the base clock C.
LK (f) is input. In addition, instead of AND-B,
A NOR gate whose (inverted) input terminal is connected to the output terminal QB of the CNT-A and whose (non-inverted) input terminal is connected to the basic clock CLK (f) may be used.

OR-A has a first input terminal AND-A
And the second input terminal is connected to the output terminal of AND-B. The FF-B has a data input terminal connected to the output terminal of the OR-C, a (negative phase) data output terminal rQ connected to the first input terminal of the OR-C, and a clock input terminal connected to the OR-A. It is connected to the output terminal and operates at the rising edge of the output clock of OR-A. The second input terminal of OR-C is connected to the external reset input terminal E-RST.

The above CNT-A, AND-C and OR-B
Means that it operates on the rising edge of the basic clock.
A quinary counter 1 that counts from 0 "to" 4 "is configured, and the count output of CNT-A is" 4 "(QC =" QC ").
H ", QB = QA =" L "), the output of AND-A becomes" H ", and the output of AND-A is a reset input terminal RESET of CNT-A via OR-B as an internal reset signal. To reset CNT-A.

The above NOR-A, FF-A and AND-A
And NOR-A decode the count values "4" and "0" of the quinary counter 1 and change the output from "L" to "H". -A is N
By latching the decoded output of OR-A at the falling edge of the basic clock CLK (f), it is delayed by a half clock period of the basic clock CLK (f), and AND
In -A, the output of the FF-A is "H", and the basic clock CLK (f) is gated to generate a 1/5 frequency-divided clock CLKa (f / 5). At this time, the basic clock CLK (f) is gated substantially during the period when the count value of the quinary counter 1 is “0” (p = 0) and the next “1”.

The above AND-B corresponds to the second gate circuit, and the count value of the quinary counter 1 is "2" (q =
2) and the next “3” period, the basic clock CLK
By gating the inverted clock of (f), 1/5
A divided clock CLKb (f / 5) is generated. To gate the inverted clock means that the basic clock CLK during the period when the count value of the quinary counter 1 is "2" and "3"
(F), and the gate output is supplied to the basic clock CL.
This is equivalent to delaying by a half clock period of K (f). The above p and q satisfy the following equation: q = p + (N-1) / 2 (N = 5).

These NOR-A, FF-A and AND-
A and AND-B constitute the frequency dividing means 2, and two 1/5 frequency-divided clocks CLKa (f / 5) whose phases are shifted from each other by 5/2 clock periods of the basic clock CLK (f).
And CLKb (f / 5).

The above-mentioned OR-A, FF-B and OR-C constitute a synthesizing means 3 for generating two 1/5 frequency-divided clocks CLKa (f / 5) and CLKb (f / 5). By synthesizing, 2/5 of the basic clock CLK (f)
A divided clock CLK (2f / 5) is generated. OR-A
Are 1/5 frequency-divided clocks CLKa (f / 5) and CLK
b (f / 5) corresponds to an OR gate, and FF-B and OR-C constitute a latch circuit.
FF-B at the rising edge of the output clock of OR-A
Is operated to obtain a 2/5 frequency-divided clock CLK (2f / 5) based on the positive-phase latch data.

FIG. 2 is an operation timing chart of the frequency dividing circuit shown in FIG. The quinary counter 1 is the basic clock CL
It operates at the rising edge of K (f) and outputs count values “0” to “4” at the timing shown in FIG.

NOR-A changes its output from "L" to "H" when the count value of the quinary counter 1 is "4" and "0".
(FIG. 2D). The FF-A latches the output of the NOR-A at the falling edge of the basic clock CLK (f) and delays the output of the NOR-A for a half clock period (FIG. 2E). The AND-A gates the basic clock CLK (f) while the output of the FF-A is at “H”, so that the 1/5 frequency-divided clock CLKa (f /
5) is output. This CLKa (f / 5) is shown in FIG.
As shown in (F), it is a waveform obtained by gating the basic clock CLK (f) during the count values “0” and “1”.

On the other hand, since the output terminal QB of CNT-A becomes "H" when the count value is "2" and "3" (FIG. 2 (G)), AND-B gates this QB output. The signal is used as a signal, and while the QB output is "H", the basic clock CLK (f) is gated to output a 1/5 frequency-divided clock CLKb (f / 5). This CLKb
(F / 5) is the count value, as shown in FIG.
The waveform is obtained by gating the inverted clock of the basic clock CLK (f) during the periods 2 ”and“ 3 ”.

A signal obtained by gating the inverted clock of the basic clock CLK (f) for a certain count value is 1 with respect to the basic clock CLK (f) gated in the same period.
Therefore, the phase difference between the 1/5 frequency-divided clocks CLKa (f / 5) and CLKb (f / 5) is 5/2 clock periods.

OR-A is the output of NAND-A and AND
−B, the output of CLKa (f /
5) and CLKb (f / 5) are combined and output (FIG. 4).
(I)). 1/5 frequency-divided clock CLKa (f / 5) and C
Since the phase difference of LKb (f / 5) is 2.5 clock periods, the frequency of this synthesized clock is 1 / 2.5 = 2/5 of the basic clock frequency f.

The FF-B operates at the rising edge of the output clock of the OR-A.
H "is alternately repeated, whereby a 2/5 frequency-divided clock CLK (2f / 5) of the basic clock frequency f is output from the output terminal Q of the FF-B as shown in FIG. .

As described above, according to the first embodiment,
By the frequency dividing means 2, the count value of the quinary counter 1 becomes "
0 ”(= p) and“ 1 ”, the basic clock CLK
(F), and the inverted clock of the basic clock CLK (f) is gated while the count value is “2” (= q) and “3”, so that the phases of the clocks are mutually different.
(F) Generates 1/5 frequency-divided clocks CLKa (f / 5) and CLKb (f / 5) that differ by 5/2 clock periods, and the synthesizing means 3 generates the 1/5 frequency-divided clock CLKa.
By synthesizing (f / 5) and CLKb (f / 5) and operating the FF-B with the synthesized clock, the basic clock CLK (f / 5) can be used without using a circuit operating at twice the basic clock frequency. f), a 2/5 frequency-divided clock CLK (2f / 5) can be generated.
It is possible to easily cope with the case where the basic clock frequency is high, and it is possible to reduce the power consumption as compared with the conventional frequency dividing circuit.

The above-mentioned p and q are not limited to the above-mentioned count values, but may be any values satisfying either q = p− (N + 1) / 2 or q = p + (N−1) / 2. . When the quinary counter 1 operates at the falling edge of the basic clock CLK (f), a value satisfying either q = p− (N−1) / 2 or q = p + (N + 1) / 2 I just want it.

In the first embodiment, N = 5
However, even when N is an odd number of 7 or more, the present invention can be applied by using a counter in the same base as N and determining p and q in accordance with the above equation.

Second Embodiment Since the frequency dividing circuit of the first embodiment cannot be applied when N = 3, the present embodiment will describe a frequency dividing circuit which can be applied even when N = 3. I do.

FIG. 3 is a circuit diagram showing a frequency dividing circuit according to a second embodiment of the present invention. The frequency dividing circuit in which N = 5, that is, the basic clock CLK (f) having a frequency f is divided by 2/5. Frequency dividing circuit.

The frequency dividing circuit shown in FIG.
T-A and three-input AND gates AND-A and AND
-B and D flip-flops FF-A and FF-B
And two-input OR gates OR-A and OR-B.

CNT-A has three count output terminals Q
A, QB, QC, a clock input terminal to which the basic clock CLK (f) is input, and a reset input terminal RESET
And operates at the rising edge of the basic clock CLK (f). Output terminal QA is LSB terminal, output terminal Q
C is an MSB terminal.

The AND-A has a first (inverted) input terminal connected to the output terminal QA of the CNT-A, and a second (inverted) input terminal.
The input terminal is connected to the output terminal QB and the third (non-inverting)
The input terminal is connected to the output terminal QC. Also AND
-B, the first (inverted) input terminal is connected to the output terminal QA of the CNT-A, the second (non-inverted) input terminal is connected to the output terminal QB, and the third (inverted) input terminal is It is connected to the output terminal QC.

OR-B has a first input terminal AND-A.
, The second input terminal is an external reset input terminal, and the output terminal is connected to the reset terminal RESET of the CNT-A.

In the FF-A, the data input terminal D is AND-
A is connected to the output terminal of A and operates at the rising edge of the basic clock CLK (f). The FF-B has the data input terminal D connected to the output terminal of the AND-B, and operates at the falling edge of the basic clock CLK (f).

The OR-A has a first input terminal connected to the (positive phase) data output terminal Q of the FF-A, and a second input terminal connected to the (positive phase) data output terminal Q of the FF-B. Have been.

The above CNT-A, AND-A and OR-B
Means that it operates on the rising edge of the basic clock.
A quinary counter 1 that counts from 0 "to" 4 "is configured, and the count output of CNT-A is" 4 "(QC =" QC ").
H ", QB = QA =" L "), the output of AND-A becomes" H ", and the output of AND-A is a reset input terminal RESET of CNT-A via OR-B as an internal reset signal. To reset CNT-A.

At the same time, the AND-A corresponds to the first decoding circuit, and the count value of the quinary counter 1 is "4" (i
= 4) to change the output from "L" to "H". The above AND-B corresponds to the second decoding circuit, and the count value “2” (j = 2) of the quinary counter 1
To change the output from "L" to "H".
The above FF-A corresponds to the first latch circuit, and AND
Latch the decoded output of -A at the rising edge of the basic clock CLK (f). The FF-B corresponds to a second latch circuit, and latches the decoded output of AND-B at the falling edge of the basic clock CLK (f). Note that the above i and j satisfy the following equation: j = i− (N−1) / 2 (N = 5).

These AND-A, AND-B and FF-
A and FF-B constitute the frequency dividing means 4 and have two 1/5 frequency-divided clocks CLKa (f / 5) whose phases are shifted from each other by 5/2 clock periods of the basic clock CLK (f) and CLKb (f / 5) is generated. That is, AND-
A decode output is supplied to the basic clock CLK by FF-A.
By delaying one clock period of (f), 1/5
A divided clock CLKa (f / 5) is generated, and AND
-A decode output is supplied to the base clock CL by FF-B.
By delaying by 1/2 clock period of K (f), 1
/ 5 divided clock CLKb (f / 5) is generated.

The above OR-A corresponds to the synthesis means 5, and
One-fifth frequency-divided clocks CLKa (f / 5) and CL
By synthesizing Kb (f / 5), the basic clock C
A Ｌ frequency-divided clock CLK (2f / 5) of LK (f) is generated.

FIG. 4 is an operation timing chart of the frequency dividing circuit shown in FIG. The quinary counter 1 is the basic clock CL
It operates at the rising edge of K (f), and outputs count values “0” to “4” at the timing shown in FIG.

The AND-A decodes the count value "4" of the quinary counter 1 and changes its output from "L" to "H" (FIG. 4 (D)). The FF-A delays the output of the AND-A by one clock period by latching the output of the AND-A at the rising edge of the basic clock CLK (f), and the 1/5 frequency-divided clock CLKa (f / 5)
Is output (FIG. 4E).

On the other hand, AND-B decodes the count value "2" of the quinary counter 1 and changes its output from "L" to "L".
H ”(FIG. 4 (F)).
By latching the output of -B at the falling edge of the basic clock CLK (f), the output of AND-B is reduced to 1 /
Delayed by two clock periods and divided by 1/5 frequency clock CLKb
(F / 5) is output (FIG. 4 (G)). At this time, 1/5
Divided clocks CLKa (f / 5) and CLKb (f / 5)
Is a 5/2 clock period.

OR-A is a 1/5 frequency-divided clock CLKa
(F / 5) and CLKb (f / 5) are combined by ORing. CLKa (f / 5) and CLKb (f /
Since the phase difference of 5) is 2.5 clock periods, the frequency of this synthesized clock is 1/2.
5 = 2/5. Therefore, the output of OR-A is
As shown in (H), 2 / (2) of the basic clock CLK (f)
It becomes the frequency-divided clock CLK (2f / 5).

As described above, according to the second embodiment,
The count value of the quinary counter 1 by the frequency dividing means 4 "
4 "(= i) is decoded by AND-A, the decoded output is delayed by one basic clock period by FF-A, and the count value" 2 "(= j) is decoded by AND-B. The output is delayed by ＦＦ basic clock period by FF-B, and the 1/5 frequency-divided clock CLKa (f / 5) whose phases are different from each other by 5/2 basic clock period
And CLKb (f / 5), and the synthesizing means 5
The 1/5 frequency-divided clocks CLKa (f / 5) and CLKb (f
/ 5) are combined to obtain the basic clock frequency of 2
Without using a circuit that operates at twice the frequency, a 2/5 frequency-divided clock CLK (2f /
Since 5) can be generated, it is possible to easily cope with a case where the basic clock frequency is high, and it is possible to reduce the power consumption as compared with the conventional frequency dividing circuit. As will be described later, by using a ternary counter, N
= 3.

The above-mentioned i and j are not limited to the above-mentioned count values, but may be any value satisfying either j = i- (N-1) / 2 or j = i + (N + 1) / 2. . When the quinary counter 1 operates at the falling edge of the basic clock CLK (f), a value satisfying either j = i− (N + 1) / 2 or j = i + (N−1) / 2 I just want it.

In the second embodiment, N = 5
However, when N is an odd number of 3 or more other than 5,
The present invention can be applied by using a counter having the same radix as N and determining the decode values i and j according to the above equation.

[0049]

As described above, according to the frequency dividing circuit of the present invention, the frequency dividing means makes the phases N and N of the basic clock mutually.
By generating two 1 / N frequency-divided clocks that are different from each other by 1/2 clock period, and synthesizing the two 1/5 frequency-divided clocks by the synthesizing means, the basic clock frequency of 2
Since a 2 / N frequency-divided clock of the basic clock can be generated without using a circuit operating at twice the frequency, it is possible to easily cope with a case where the basic clock frequency is high. There is an effect that power consumption can be reduced as compared with a circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a frequency dividing circuit according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the frequency dividing circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a frequency dividing circuit according to a second embodiment of the present invention.

FIG. 4 is an operation timing chart of a frequency dividing circuit according to a second embodiment of the present invention.

[Explanation of symbols]

1 quinary counter, 2,4 dividing means, 3,5 combining means, CNT-A 3-bit counter, FF-A,
FF-BD flip-flop, AND-A, AND
-B, AND-C AND gate, OR-A, OR-
B, OR-COR gate, NOR-A NOR gate.

Claims (4)

[Claims] An N-ary (N is an odd number of 3 or more) counter operating at either a rising edge or a falling edge of a basic clock, and a phase based on output timings of two count values of the N-ary counter. Are (N /
2) frequency dividing means for generating two (1 / N) frequency-divided clocks shifted by a clock period; and synthesizing the two (1 / N) frequency-divided clocks to thereby produce (2 / N) of the basic clock. A frequency dividing circuit having a synthesizing means for generating a frequency-divided clock. 2. The frequency dividing means: a first decoding circuit for decoding a count value i (i is an integer from 0 to N-1) of the N-ary counter, and a count value of the N-ary counter a second decode circuit for decoding j (j is any integer from 0 to N-1); a first latch circuit for latching a decode output of the first decode circuit at a rising edge of the basic clock; A second latch circuit for latching a decode output of the second decode circuit at a falling edge of the basic clock, wherein the synthesizing means includes a latch output of the first latch circuit and a second latch circuit. 2. The frequency dividing circuit according to claim 1, further comprising a logical sum gate having a latch output of the latch circuit as an input. 3. The count values i and j are j = i− (N−1) / 2 or j = i + (N +) when the N-ary counter operates at the rising edge of a basic clock.
1) if any of (1) / 2 is satisfied and the N-ary counter operates on the falling edge of the basic clock, j
= I- (N + 1) / 2 or j = i + (N-1) / 2, and the first and second decoding circuits respectively
3. The frequency dividing circuit according to claim 2, comprising a logical product gate having a count output of a binary counter as an input, wherein each of said first and second latch circuits comprises a D flip-flop. 4. The frequency dividing means according to claim 1, wherein the N is an odd number of 5 or more, and wherein the frequency dividing means sets the count value of the N-ary counter to p (p is any integer from 0 to N-1) and the next count value A first gate circuit that gates the basic clock for a period of time, a period in which the count value of the N-ary counter is q (q is any integer from 0 to N−1) and the next count value, A second gate for inverting the basic clock
A combinational circuit comprising: a logical sum gate receiving an output of the first gate circuit and an output of the second gate circuit; a rising edge of an output clock of the logical sum gate; Alternatively, it operates at the falling edge, connects the input terminal to the negative-phase latch output terminal, and connects the positive-phase latch output terminal to the (2 /
N) a latch circuit as an output terminal of a divided clock, wherein the count values p and q are q = p− when the N-ary counter operates at the rising edge of the basic clock.
(N + 1) / 2 or q = p + (N-1) / 2, and q = p- (N-1) if the N-ary counter operates on the falling edge of the basic clock.
2. The frequency dividing circuit according to claim 1, wherein any one of / 2 and q = p + (N + 1) / 2 is satisfied.