JPH10322202A - PLL circuit - Google Patents

Abstract

(57) [Problem] To provide a PLL circuit having a wide lock frequency range. A voltage controlled oscillator of a PLL circuit has a first terminal with relatively high sensitivity and a second terminal with relatively low sensitivity. A constant voltage is supplied to the first terminal, and a voltage proportional to the output voltage of the low-pass filter is supplied to the second terminal. The first terminal is a terminal connected to the output of the low-pass filter in a standard use state, and the second terminal is connected to a resistor for adjusting the oscillation frequency range of the voltage controlled oscillator in a standard use state. Terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit, and more particularly to a PLL circuit having a wide lock frequency range.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a configuration of a conventional PLL circuit. This PLL circuit includes a phase frequency detector (PFD) 10, a low-pass filter (LF; also called a loop filter) 12, and a voltage-controlled oscillator (VC
O) 14 and a frequency divider 16. The reference input signal Sref is input to a reference input terminal of the phase frequency detector 10, and the feedback signal Sret is input to a feedback input terminal.

[0003] The phase frequency detector 10 receives a reference input signal S
A signal having a voltage level corresponding to the edge difference between ref and the feedback signal Sret is output. The output of the phase frequency detector 10 is passed through a low-pass filter 12 to a voltage-controlled oscillator 14
To the first terminal T1. A bias resistor Rbias is connected to the second terminal T2 of the voltage controlled oscillator 14. The output of the voltage controlled oscillator 14 is the clock signal CL
It is output to the outside as K and is input to the frequency divider 16. The frequency divider 16 is a counter that counts the number of pulses up to the set multiple N, and divides the clock signal CLK by the multiple N. The signal Sret divided by the frequency divider 16 is used as the feedback signal 10 by the phase frequency detector 10.
Is input to the feedback input terminal.

In a state where the phases and frequencies of the reference input signal Sref and the feedback signal Sref are locked, the clock signal CLK has a frequency N times the reference input signal Sref.
The signal has the same phase as the reference input signal Sref. The frequency range of the clock signal CLK that can achieve the lock state (hereinafter, simply referred to as “lock frequency range”) is adjusted by the bias resistor Rbias connected to the second terminal T2 of the voltage controlled oscillator 14. FIG. 4 is a graph showing an example of the relationship between the resistance value of the bias resistor Rbias and the lock frequency range.

[0005]

As can be seen from FIG. 4, in the conventional PLL circuit, the bias resistance Rbias
The lock frequency range for one resistance value is relatively narrow. For this reason, it has been difficult to generate a clock signal CLK having a wide range of frequencies using such a PLL circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the prior art, and has as its object to provide a PLL circuit having a wide lock frequency range.

[0007]

Means for Solving the Problems and Their Functions and Effects To solve at least a part of the above-mentioned problems, the present invention
The PLL circuit includes a phase frequency detector, a low-pass filter, and a voltage-controlled oscillator, wherein the voltage-controlled oscillator has a first terminal having a relatively high sensitivity and a second terminal having a relatively low sensitivity. And a constant voltage is supplied to the first terminal, and the second terminal
Is supplied with a voltage proportional to the output voltage of the low-pass filter.

With this configuration, the oscillation frequency range of the PLL circuit changes according to the output level of the low-pass filter, so that a PLL circuit having a wide lock frequency range can be realized.

The first terminal is a terminal connected to the output of the low-pass filter in a standard use state, and the second terminal is an adjustment of an oscillation frequency range of the voltage controlled oscillator in a standard use state. May be a terminal to which a resistor is connected.

Some commercially available PLL circuit elements (eg, IC circuits including a phase frequency detector and a voltage controlled oscillator) include a terminal connected to the output of the low-pass filter in a standard use state, In some cases, a terminal to which a resistor for adjusting the oscillation frequency range of the control oscillator is connected is provided. When such a circuit element is used, a constant voltage is supplied to the first terminal connected to the output of the low-pass filter in a standard use state, and the oscillation frequency range of the voltage-controlled oscillator in a standard use state. By supplying the output of the low-pass filter to the second terminal to which the resistor for adjusting
An L circuit can be configured.

The PLL circuit includes an amplifier to which an output voltage of the low-pass filter, which is a passive filter, is input, and two resistors for dividing the output voltage of the amplifier and a predetermined power supply voltage. The voltage-controlled oscillator may be configured so that a voltage divided by the two resistors is supplied to the second terminal of the voltage-controlled oscillator.

By providing the amplifier, the input impedance to the voltage controlled oscillator can be reduced.
Further, since the output voltage of the amplifier and the predetermined power supply voltage are divided by two resistors and supplied to the second terminal of the voltage controlled oscillator, the input voltage level of the second terminal (ie, the lock of the voltage controlled oscillator) The voltage level for adjusting the frequency range is adjusted to a value proportional to the output voltage of the low-pass filter. As a result, a PLL circuit having a wide lock frequency range according to the output voltage level of the low-pass filter can be realized.

[0013]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention. This PL
The L circuit includes a phase frequency detector 10, a low-pass filter 12, an amplifier (op-amp) 18, and four resistors R1
To R4, a voltage controlled oscillator (VCO) 14, and a frequency divider 1
6 is provided.

An output of the phase frequency detector 10 is supplied to a non-inverting input terminal of an amplifier 18 through a low-pass filter 12. The output of the amplifier 18 is fed back to the inverting input terminal of the amplifier 18. The low-pass filter 12 is, for example, a passive filter including a capacitor and a resistor. The low-pass filter 12 and the amplifier 18 constitute an active filter.

The output terminal of the amplifier 18 has two resistors R
1, and the power supply voltage Vdd via R2. A node P1 between the two resistors R1 and R2 is connected to the voltage-controlled oscillator 1
4 is connected to the second terminal. Therefore, a voltage obtained by dividing the voltage between the power supply voltage Vdd and the output voltage of the amplifier 18 by the two resistors R1 and R2 is supplied to the second terminal T2 of the voltage controlled oscillator 14. Therefore, a voltage proportional to the output voltage of the low-pass filter 12 is input to the second terminal T2. On the other hand, the first terminal T of the voltage controlled oscillator 14
1 is supplied with a voltage obtained by dividing the power supply voltage Vdd by the other two resistors R3 and R4.

In the conventional PLL circuit shown in FIG. 3 (that is, in a standard use state), while the output voltage from the low-pass filter 12 is supplied to the first terminal T1 of the voltage controlled oscillator 14, In the PLL circuit of the embodiment shown in FIG. 1, a constant voltage is supplied to the first terminal T1.
On the other hand, in FIG. 3, the second terminal T1 of the voltage controlled oscillator 14 is
In FIG. 1, a voltage proportional to the output voltage of the low-pass filter 12 is input to the second terminal T1. Thus, in the PLL circuit of the embodiment shown in FIG. 1, it can be considered that the two terminals T1 and T2 of the voltage controlled oscillator 14 in the conventional PLL circuit are used in reverse.

The voltage controlled oscillator 14 in this embodiment
Has a built-in ring oscillator circuit composed of CMOS. The two terminals T1 and T2 are the two input terminals to the ring oscillator circuit, the first terminal T1 is relatively sensitive and the second terminal T2 is relatively insensitive. Here, “high sensitivity” means that the slope of the change in the oscillation frequency of the voltage controlled oscillator 14 with respect to the change in the input voltage is large. Since the two terminals T1 and T2 have characteristics similar to each other except for different sensitivities, they can be used in a connection state opposite to a standard use state as in this embodiment. .

FIG. 2 is a graph showing a lock frequency range in the PLL circuit of the embodiment. The horizontal axis in FIG. 2 is the input voltage of the amplifier 18 (that is, the output voltage of the low-pass filter 12), and the vertical axis is the lock frequency. In addition,
The horizontal axis is a normal linear scale, while the vertical axis is a logarithmic scale. The range indicated by hatching is the lock frequency range. As can be seen from FIG. 2, the lock frequency range is about 0.01 MHz (10 k) depending on the input voltage to the amplifier 18.
Hz) to about 100 MHz. Therefore, the clock signal CLK having a wide range of frequencies can be generated by the same PLL circuit without having to adjust the bias resistance as in the related art. The frequency of the clock signal CLK is a value obtained by multiplying the frequency of the reference input signal Sref by a frequency division ratio (multiplication number) N in the frequency divider 16. Therefore, in the PLL circuit of the embodiment, the reference input signal Sr
By changing the frequency of ef and the dividing ratio N, a clock signal CLK having a wide range of frequencies from about 0.01 MHz (10 kHz) to about 100 MHz can be easily generated.

It should be noted that the present invention is not limited to the above examples and embodiments, but can be implemented in various modes without departing from the gist thereof.
For example, the following modifications are possible.

(1) The amplifier 18 is not always necessary, and a low-pass filter may be constituted only by a passive filter. Further, the frequency divider 16 can be omitted.

(2) First terminal T of voltage controlled oscillator 14
1 only needs to be supplied with a constant voltage.
3, a constant voltage can be supplied to the first terminal T1 by various circuit configurations other than the circuit using R4. On the other hand, the second terminal T2 of the voltage-controlled oscillator 14
What is necessary is just to supply the voltage proportional to the output voltage of the low-pass filter 12. Such a circuit can also be realized by various circuit configurations other than the circuit in the embodiment using the amplifier 18 and the two resistors R1 and R2.

[0022]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit as one embodiment of the present invention.

FIG. 2 is a graph showing a lock frequency range in the PLL circuit according to the embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional PLL circuit.

FIG. 4 is a graph showing an example of a relationship between a resistance value of a bias resistor Rbias and a lock frequency range.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Phase frequency detector 12 ... Low pass filter 14 ... Voltage controlled oscillator 16 ... Divider 18 ... Amplifier

Claims (3)

[Claims] 1. A PLL circuit comprising a phase frequency detector, a low-pass filter, and a voltage controlled oscillator, wherein the voltage controlled oscillator has a first terminal having a relatively high sensitivity and a second terminal having a relatively low sensitivity. A constant voltage is supplied to the first terminal, and a voltage proportional to the output voltage of the low-pass filter is supplied to the second terminal. PL
L circuit. 2. The PLL circuit according to claim 1, wherein the first terminal is a terminal connected to an output of the low-pass filter in a standard use state, and the second terminal is a standard terminal. A PLL circuit which is a terminal to which a resistor for adjusting an oscillation frequency range of the voltage controlled oscillator is connected in a use state. 3. The PLL circuit according to claim 1, further comprising: an amplifier to which an output voltage of said low-pass filter, which is a passive filter, is input, and an output voltage between said amplifier and a predetermined power supply voltage. A PLL circuit comprising: two resistors that divide a voltage of the voltage-controlled oscillator. The voltage divided by the two resistors is supplied to the second terminal of the voltage-controlled oscillator.