JPH1032247A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable formation of ohmic multilayer wirings at a high yield without enlarging the circuit area, by opening a connection hole having a greater area at its aperture portion than at its bottom, and forming an insulating sidewall on the peripheral wall of the connection hole. SOLUTION: An element isolation insulating film 21 is formed on a semiconductor substrate 10, and a diffusion layer 11 is formed in a region isolated by the element isolation insulating film 21. After the surface of the semiconductor substrate 10 is covered with an interlayer insulating film 22, a tapered connection hole 40 which has a greater area at its aperture portion than at its bottom and which has its diameter gradually increased toward the aperture portion is formed on the interlayer insulating film 22. Then, a silicide layer 31 made of an alloy of the semiconductor substrate 10 and a refractory metal is formed on the bottom of the connection hole 40. Subsequently, the peripheral wall of the connection hole 40 is covered with an insulating sidewall 24, and a contact layer metal 32 is formed on the inner peripheral wall of the sidewall 24. Then, a buried conductor 34 is buried inside of the connection hole surrounded by the contact layer 32, and a wiring layer 36 is formed on the buried conductor 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a low contact resistance and a method of manufacturing the same.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated and miniaturized,
An increase in the contact resistance between the substrate and the conductor wiring has become a problem. That is, conventionally, a connection hole (contact hole) reaching the substrate is opened in the interlayer insulating film, a titanium film or the like is formed on the substrate at the bottom of the connection hole by sputtering, and the substrate and the titanium film are reacted to form a silicide, thereby reducing the contact hole. The technology of resistance is used. However, as the miniaturization progresses, the opening area of the connection hole also decreases and the aspect ratio increases,
It has become difficult to form a titanium film having a sufficient thickness at the bottom of the connection hole. It is known that the resistance at the contact suddenly increases unless the thickness of the titanium film is not less than a certain thickness.

FIG. 6 and FIG. 7 show a conventional contact technique.
I will explain. First, as shown in FIG.
An element isolation insulating film 200 is formed on an N-type substrate 100 and diffused.
The layer 101 is formed. Atmospheric pressure CVD of interlayer insulating film 201
Film formation, heat treatment, resist patterning of connection holes
Perform R11. At this time, the diffusion layer, insulating film formation, and heat
The processing conditions are shown below.Diffusion layer formation : BF_Two ⁺Ion implantation (35 keV, 3 × 10^Fifteenions
/ Cm^Two) Heat treatment (vertical diffusion furnace annealing, 900 ° C, N_Two, 10
Minutes)Insulation film formation : Normal pressure CVD TEOS: 60 sccm, TMPO: 15 sccm, T
EB: 520 ° C. at 15 sccm, 2% by weight of boron (B), 5% by weight of phosphorus (P)
%, Thickness 1200nmInsulating film heat treatment method : Vertical diffusion furnace annealing N_Two: 100%, 750 ° C., 10 minutes After that, as shown in FIG.
The connection hole 400 is opened by ringing. Connection hole processing conditions
It is shown below.Connection hole processing conditions : Reactive ion etching (−30 ° C., 5.3 Pa, 12
00W) CO: 100 sccm, C_FourF₈: 7sccm, Ar:
Next, as shown in FIG. 6C, the resist was removed.
After that, contact ion implantation and heat treatment are performed to remove the oxide film.
After performing the pre-treatment, the adhesion layer metal 300 is
The entire surface is formed by the guntron sputtering method.
Metal silicide 301 at the bottom of the connection hole
After that, the tungsten film 310 is entirely covered with the thermal CVD method.
Form a film. Examples of the respective film forming conditions are shown below.Activation of contact impurities : BF_Two, 20 keV, 3 × 10^Fifteenions / cm^Two Oxide removal : H_TwoO: buffered hydrofluoric acid = 400: 1, 60 secondsAdhesion layer metal sputter : Collimated Ti 30 nm (0.52 Pa, 8 kW, Ar
35 sccm, 300 ° C.) TiN 70 nm (0.78 Pa, 6 kW, N_2;42sc
cm, Ar; 21 sccm, 300 ° C.) Lamp annealing : 650 ° C, 1 atm, N_Two100%, 30 secondsBlanket W : 600 nm (10.7 kPa, W
F₆: H_Two: Ar = 40: 400: 2250 sccm,
(450 ° C.) Next, contact holes are filled by anisotropic ion etching over the entire surface.
After forming the embedded plug (embedded conductor) 311,
Body wiring material is entirely deposited by magnetron sputtering
Photoresist patterning and anisotropic ion etching
To form a conductor wiring 320, as shown in FIG.
A simple contact structure can be obtained. Each professional
Examples of access conditions are shown below.Embedded plug processing : 1st STEP (W etching): 45.5 Pa, 275 W, SF6: Ar: He = 110: 90: 5 sccm 2nd STEP (TiN etching): 6.5 Pa, 250 W, Ar: Cl_Two= 75: 5scc
m 3rdSTEP (W overetch): 32.5 Pa, 70 W, SF₆: Ar: He = 20: 1
0: 10sccmConductor wiring formation : Barrier metal: Ti: 20 nm (0.52 Pa, 2 kW, Ar35sc)
cm, 300 ° C.) TiN: 20 nm (0.78 Pa, 6 kW, N_Two; 42
sccm, Ar65sccm, 300 ° C) Aluminum alloy: Al-0.5% Cu500nm (0.52Pa, 15k)
W, Ar; 65 sccm, 300 ° C. Cap metal: Ti 10 nm (0.52 Pa, 2 kW, Ar; 35 sc)
cm, 300 ° C.) TiN 100 nm (0.78 Pa, 6 kW, N_Two; 42
sccm, Ar: 21 sccm, 300 ° C)Conductive wiring reactive ion etching : BCl_Three/ Cl_Two= 100 / 150sccm, 1Pa,
Microwave 400mA, RF110W Just + 40% overetching P formed by the above process⁺Si contact resistance
Is 8 with a diameter of φ0.4 μm (hole aspect ratio 3.0).
It has an ohmic characteristic of 0Ω and a diameter of φ0.3μm (hole
360 Ω non-ohmic characteristics with an aspect ratio of 4.0)
there were. The deterioration of the contact characteristics
This is attributable to the thickness of the contact hole bottom of the deposited metal. Toes
Φ0.4μm diameter (Hole aspect ratio 3.0)
In this method, a Ti film with a bottom is formed to 5 nm or more,
Ohmic contact is formed by residing
On the other hand, the diameter of φ0.3 μm (hole aspect ratio of 4.
In the case of 0), the Ti film is formed only about 2 nm,
First, silicidation results in high resistance. Metal contour
When the ohmic resistance rises and becomes non-ohmic,
Such as operation delays, performance variations,
There is concern about characteristic deterioration.

[0004] In order to solve such a problem, it is necessary to improve the coverage with the bottom of the adhesion layer metal, and there is a means for introducing a new technology such as a high directivity sputtering method or a CVD method. , The former is expensive
The latter has a problem of impurity concentration.

[0005] In addition, a conventional hoe can be used without reducing the hole diameter.
The bottom diameter of the adhesion layer metal.
It is thought that there is a way to secure and reduce the circuit area.
However, the problem in that case will be described with reference to FIGS.
I do. For example, the element isolation insulating film 200
Is formed, a diffusion layer 101 is formed. Interlayer insulating film 2
02 by normal pressure CVD and heat treatment (in this case,
Isolation between layers to provide ohmic contact even for small diameters
Edge pattern thickness is reduced), resist patterning of connection holes
Perform R12.Diffusion layer formation : BF_Two ⁺Ion implantation (35 keV, 3 × 10^Fifteenions
/ Cm^Two) Heat treatment (vertical diffusion furnace annealing, 900 ° C, N_Two, 10
Minutes)Insulation film formation : Normal pressure CVD TEOS: 60 sccm, TMPO: 15 sccm, T
EB: 520 ° C. at 15 sccm, 2% by weight of boron (B), 5% by weight of phosphorus (P)
%, Thickness 600 nmInsulating film heat treatment method : Vertical diffusion furnace annealing N_Two: 100%, 750 ° C., 10 minutes After that, as shown in FIG.
The connection hole 401 is opened by ringing. The connection processing conditions
Shown below.Reactive ion etching : (−30 ° C., 5.3 Pa, 1
200W) CO: 100sccm, C_FourF₈: 7sccm, Ar:
Next, as shown in FIG. 8C, the resist R12 is removed.
After that, contact ion implantation, heat treatment and oxidation
After performing the pre-treatment of film removal, the adhesion layer metal 300 is used as an example.
For example, a film is entirely formed by magnetron sputtering, and run
Annealing is performed, and metal silicide 301 is placed at the bottom of the connection hole.
After that, the tungsten film 310 is formed by thermal CVD.
The entire surface is formed. Examples of each film formation condition are shown below.
You.Activation of contact impurities : BF_Two, 20 keV, 3 × 10^Fifteenions / cm^Two Oxide film removal : H_TwoO: buffered hydrofluoric acid = 400: 1, 60 secondsAdhesion layer metal sputter : Collimated Ti: 30 nm (0.52 Pa, 8 kW, A
r: 35 sccm, 300 ° C.) TiN: 70 nm (0.78 Pa, 6 kW, N_Two: 42
sccm, Ar: 21 sccm, 300 ° C)Lampani
Rule: 650 ° C, 1 atm, N_Two: 100% for 30 secondsBlanket W film CVD : 600 nm (10.7 kP
a, WF₆: H_Two: Ar = 40: 400: 2250sc
cm, 450 ° C.) Next, as shown in FIG.
After forming the plug 312 buried in the connection hole,
The entire upper conductor wiring material is completely removed by magnetron sputtering.
Surface deposition, photoresist patterning and anisotropic ions
Conductive wiring 320 is formed by etching.Embedded plug processing : 1st STEP (W etching): 45.5 Pa, 27
5W, SF₆: Ar: He = 110: 90: 5 sccm 2nd STEP (TiN etching): 6.5 Pa, 250 W, Ar: Cl_Two= 75: 5scc
m 3rdSTEP (W overetch): 32.5 Pa, 70 W, SF₆: Ar: He = 20: 1
0: 10sccm Conductor wiring formation : Barrier metal: Ti: 20 nm (0.52 Pa, 2 kW, Ar35sc)
cm, 300 ° C.) TiN: 20 nm (0.78 Pa, 6 kW, N_Two; 42
sccm, Ar 65 sccm, 300 ° C.) Aluminum alloy: Al-0.5% Cu: 500 nm (0.52 Pa, 15)
kW, Ar; 65 sccm, 300 ° C. Cap metal: Ti: 10 nm (0.52 Pa, 2 kW, Ar; 35 s)
ccm, 300 ° C.) TiN: 100 nm (0.78 Pa, 6 kW, N2; 4)
(2 sccm, Ar: 21 sccm, 300 ° C.)Conductive wiring reactive ion etching : BCl_Three/ Cl_Two= 100 / 150sccm, 1Pa,
Microwave 400mA, RF110W Just + 40% overetching In the structure of the contact hole manufactured as described above, FIG.
As shown, the diameter of φ0.4 μm (hole aspect ratio 1.
In 5), since the upper wiring layer has a narrow wiring pitch,
An area BLC in which the gusten plug is exposed occurs (baud
Darless contact). Semiconductor formed by the above process
Body device P⁺1 million steps of contact chain yield of Si
Mari is φ0.4μm diameter (hole aspect ratio 1.5)
To 50%, φ0.3μm diameter (Hole Aspect
At 2.0%) was 100%. This phenomenon is
For 0.4 μm diameter, the area where the tungsten plug is exposed
Occurs, resulting in a lack of adhesion between the plug and the wiring layer.
It is thought to have caused a decrease in contact chain yield
You. On the other hand, with a diameter of 0.3 μm,
No lug exposure, yielding contact chains
Mari was good. However, in this case, the thickness of the interlayer insulating film
Thinner, which is preferable in terms of dielectric strength.
There is no. Therefore, without reducing the hole diameter,
When reducing the product, the upper conductor wiring and borderless contour
Production of semiconductor devices with high yield is expected
Disappears.

There is also a method of forming a wiring with the same kind of metal as the plug after the tungsten is buried and then performing wiring patterning. However, etching cannot be stopped at the upper portion of the plug selectively and with good controllability during wiring processing. Occurs and there is a concern about reliability problems.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor device capable of forming an ohmic, high-yield multilayer wiring without increasing the circuit area, forming a highly integrated fine wiring, and a method of manufacturing the same. The purpose is to provide.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a connected layer to which a wiring layer is to be connected, an interlayer insulating film covering the connected layer, and penetrating the interlayer insulating film. A connection hole that reaches the connected layer, the area of the opening is larger than the area of the bottom, an insulating sidewall that covers the inner peripheral wall of the connection hole, and a buried conductor that fills the connection hole. And a wiring layer wired on the interlayer insulating film, wherein the connected layer is electrically connected to the wiring layer via the buried conductor. I will provide a.

In order to achieve the above object, according to the present invention, a connection hole having an opening area larger than a bottom area is provided in an interlayer insulating film covering a connection target layer to which a wiring layer is to be connected. Opening, forming an insulating sidewall around the inner peripheral wall of the connection hole, and forming a buried conductor that fills the connection hole and connects to a wiring layer on the interlayer insulating film. And a method for manufacturing a semiconductor device, comprising:

In the semiconductor device of the present invention, the shape of the connection hole is
Since the area of the opening is larger than the area of the bottom, the actual opening area is large and the actual aspect ratio can be reduced, so that the adhesion layer metal can be formed thickly by sputtering or the like at the bottom of the connection hole, By forming a uniform alloy, an ohmic contact can be reliably formed, and as a result, a low-resistance contact can be achieved.

Further, since the insulating sidewall is formed on the peripheral wall of the connection hole, the actual opening area of the connection hole is reduced, the gap between the wiring and the buried conductor is avoided, and the borderless contact is formed. Can be avoided. As a result, high yield, high integration and fine wiring are possible.

Such a connection hole can be used not only for connection to a semiconductor substrate but also for connection of each wiring in a multilayer wiring, and has a very wide range of application. In order to obtain such a semiconductor device, a method of manufacturing a semiconductor device according to the present invention includes, in a normal step, a step of opening a connection hole having an opening area larger than an area of a bottom, and insulating a peripheral wall of the connection hole with an insulating wall. Forming a conductive sidewall.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but the present invention is not limited to the following embodiments. [First Embodiment] This embodiment is an embodiment of a contact structure as shown in FIG. This contact structure
An element isolation insulating film 21 is formed on a semiconductor substrate 10, and a diffusion layer 11 is formed in a region separated by the element isolation insulating film 21. The surface of the semiconductor substrate 10 is covered with an interlayer insulating film 22, and the interlayer insulating film 22 has a tapered connection hole 40 whose opening area is larger than the bottom area and whose diameter gradually increases as approaching the opening. ing. A silicide layer 31, which is an alloy of the semiconductor substrate 10 and a refractory metal, is formed at the bottom of the connection hole. The peripheral wall of the connection hole 40 is covered with the insulating sidewall 24, and the connection hole 4
The inner peripheral wall of the sidewall 0 is formed with an adhesion layer metal 32, and the inside of the connection hole surrounded by the adhesion layer 32 is embedded with an embedded conductor 34. A wiring layer 36 wired on the interlayer insulating film 22 is formed on the buried conductor 34,
The wiring layer 36 is electrically connected to the diffusion layer 11 of the substrate 10 via the buried conductor 34 and the silicide layer 31. The wiring layer 36 includes an adhesion layer 36a, an aluminum alloy layer 36
b, and a laminate with the cap layer 36c.

[0014] Such a contact structure is formed by connecting holes 40.
When the aperture is opened, the effect of the aspect ratio is substantially reduced due to the structure of the tapered opening,
A thick refractory metal layer can be easily formed at the bottom of the connection hole by sputtering or the like.
Thereby, the contact resistance with the substrate can be reduced. Further, at the time of forming the wiring layer, since the insulating sidewall 24 covering the peripheral wall of the connection hole 40 is formed, the same effect as when the diameter of the opening of the tapered connection hole is reduced is obtained. For example, as shown in FIG. Even if the wiring layer is slightly displaced from the opening of the connection hole, the buried conductor 34 is prevented from being exposed, and the connection between the wiring layer 36 and the buried conductor 34 is good.

FIG. 1 shows a structure in which the semiconductor 10 and the wiring layer 36 are connected, but the contact structure of the present invention can be applied to any connection hole in a multilayer wiring. There is no limitation on the type of semiconductor, and the present invention can be applied to any semiconductor using a connection hole.

As a method of obtaining such a contact structure, a step of opening a tapered connection hole instead of opening a connection hole perpendicularly to the interlayer insulating film, as compared with the step of a normal contact structure, is adopted. And a step of forming an insulating sidewall in the tapered connection hole.

The diameter of the opening of the connection hole differs depending on whether or not the collimating type high directivity sputtering is used.
The thickness of the insulating film / the diameter of the opening (pseudo aspect ratio) is 0.
It is preferable to select so as to be in the range of about 5 to 4. Further, the diameter of the opening of the connection hole / the diameter of the bottom is 1.2 to
It is preferably about 3.0. In order to form such a tapered connection hole, for example, when a tapered connection hole is opened in BPSG, for example, reactive ion etching is performed by -3.
0 ° C, 5.3 Pa, 1200 W, gas is CO: 200 s
ccm, CHF ₃ : 1000 sccm, just +30
It can be formed by performing it under the condition of% over etching. In addition, for example, + 20 ° C., 5.3P
a, 1450 W, gas: CO: 35 sccm, C ₄ F
g: 7 sccm, Ar: 200 sccm, just +3
It can be formed even by 0% over-etching.

The insulating sidewall can be formed by forming an insulating film to fill the connection hole, and then vertically etching back by reactive ion etching or the like. As the type of the insulating film constituting the sidewall, various insulating films such as a TEOS plasma CVD method, plasma SiN, SiON, normal pressure, and low pressure CVD can be used.

Next, an example of a process for manufacturing the semiconductor as shown in FIG. 1 will be described with reference to FIGS.
The process leading to the structure shown in FIG. 2A will be described. For example, an element isolation insulating film 21 is formed on an N-type substrate 10 and a diffusion layer 1 is formed.
Form one. An interlayer insulating film 22 is formed by atmospheric pressure CVD and heat treatment is performed. Examples of the conditions of the diffusion layer, the insulating film formation, and the heat treatment are shown below. Diffusion layer formation : BF ₂ ⁺ ion implantation (35 keV, 3 × 10 ¹⁵ ions)
/ Cm ² ) Heat treatment (vertical diffusion furnace annealing, 900 ° C., N ₂ , 10
Min.) Insulating film formation : normal pressure CVD TEOS: 60 sccm, TMPO: 15 sccm, T
EB: 520 ° C. at 15 sccm, 2% by weight of boron (B), 5% by weight of phosphorus (P), 1200 nm- thick insulating film Heat treatment method : Vertical diffusion furnace annealing N ₂ : 100%, 750 ° C., 10 minutes, and then connection The resist patterning R1 of the hole is performed. Next, as shown in FIG. 2B, a connection hole 40 is opened by reactive ion etching. At this time, etching is performed so as to have a tapered shape. The processing conditions are shown below. Connection hole processing : Reactive ion etching: (−30 ° C., 5.3 Pa, 1
200 W) CO: 200 sccm, CHF ₃ : 1000 sccm Just + 30% over-etching Diameter of opening (resist opening) of connection hole: 0.4 μm Depth of connection hole (thickness of insulating film): 1.2 μm After the connection hole was opened, as shown in FIG. 2C, the resist was removed, contact ion implantation and heat treatment were performed, and pretreatment for removing the oxide film was performed. After that, the adhesion layer metal layer 3
For example, a metal silicide layer 31 is formed on the bottom of the connection hole by performing a lamp anneal on the entire surface by a magnetron sputtering method, for example. Examples of each condition are shown below. Contact impurity activation : BF ₂ , 20 keV, 3 × 10 ¹⁵ ions / cm ² Oxide film removal : H ₂ O: buffered hydrofluoric acid = 400: 1, 60 seconds adhesion layer metal sputtering : collimation Ti: 30 nm (0.52 Pa) , 8kW, A
r35 sccm, 300 ° C.) TiN: 70 nm (0.78 Pa, 6 kW, N ₂ : 42)
(sccm, Ar: 21 sccm, 300 ° C.) Lamp annealing: 650 ° C., 1 atm, N ₂ : 100%, 30 seconds In this case, it is only necessary to form a metal silicide at the bottom of the connection hole, so that TiN can be omitted.

Next, as shown in FIG.
The adhesion layer metal is removed by, for example, wet etching.
An example of the condition is shown below.Removal of adhesion layer : NH_Three: H_TwoO_Two: H_TwoO = 1: 2: 7, 30 ° C., 20
Then, as shown in FIG.
For example, plasma SiO 2_TwoCVD and overall etch bar
It is formed by a hook. Examples of forming conditions are shown below.Insulation film formation : Plasma CVD TEOS: 800 sccm, O_Two: 600 sccm, 1
133.2 Pa 400 ° C., RF 700 W, film thickness 100 nm Etch back: reactive ion etching (−30 ° C.,
2.7 Pa, 500 W) CHF_Three: 50 sccm just + 30% over-etching Thickness of side wall: figure after formation of side wall 24
As shown in FIG. 3 (f), the thin adhesion layer metal layer 32 is
The tungsten film 33 by thermal CVD
The entire surface is formed by a method. Examples of each processing condition are as follows
Shown inSecond adhesion layer metal sputter : TiN: 30 nm (0.78 Pa, 6 kW, N_Two: 42
sccm, Ar: 21 sccm, 300 ° C)Blanket W film CVD : 600 nm (10.7 kP
a, WF₆: H_Two: Ar = 40: 400: 2250sc
cm, 450 ° C.) Next, as shown in FIG.
After forming the plug 34 of the connection hole by the
Barrier metal layer 36a, aluminum as upper conductor wiring material
The nickel alloy layer 36b and the cap metal layer 36c are
Deposit the entire surface by tron sputtering
Conductor layout by patterning and anisotropic ion etching
Line 36 can be formed to achieve the structure shown in FIG.
Wear.Embedded plug processing : 1st STEP (W etching): 45.5 Pa, 275 W, SF₆: Ar: He = 110: 90: 5 sccm 2nd STEP (TiN etching): 6.5 Pa, 250 W, Ar: Cl_Two= 75: 5scc
m 3rdSTEP (W overetch): 32.5 Pa, 70 W, SF₆: Ar: He = 20: 1
0: 10sccm Conductor wiring formation : Barrier metal: Ti: 20 nm (0.52 Pa, 2 kW, Ar35sc)
cm, 300 ° C.) TiN: 20 nm (0.78 Pa, 6 kW, N_Two; 42
sccm, Ar 65 sccm, 300 ° C.) Aluminum alloy: Al-0.5% Cu: 500 nm (0.52 Pa, 15)
kW, Ar; 65 sccm, 300 ° C. Cap metal: Ti: 10 nm (0.52 Pa, 2 kW, Ar; 35 s)
ccm, 300 ° C.) TiN: 100 nm (0.78 Pa, 6 kW, N_Two; 4
(2 sccm, Ar: 21 sccm, 300 ° C.)Conductive wiring layer reactive ion etching : BCl_Three/ Cl_Two= 100 / 150sccm, 1Pa,
Microwave 400mA, RF110W Just + 40% overetching The fine connection hole formed by the above process is before the adhesion layer is formed.
Connection hole top diameter of φ0.4μm (Hole aspect ratio
3.0), the bottom Ti film thickness is 5 nm or more.
Filmed, P⁺Si contacts exhibit ohmic characteristics
Was. Also, by forming insulating sidewalls, narrow wiring
Because the pitch does not become borderless contact,
100% yield of 1,000,000 steps contact chain
there were.

In the above example, the adhesion layer metal is TiN /
In addition to the Ti film, various materials such as TiW, Co, Ni, Ta, or a compound thereof can be used. As the buried conductor, Cu, Al, or other low resistivity metal other than tungsten can be used. is there. Furthermore, in the above example, as a method of forming the buried conductor, a method of forming a wiring by etching back after forming the W layer was described. Alternatively, after forming a conductor on the entire surface, this is patterned into the wiring. Then, there is a method of forming a wiring with the same conductor. Further, there is no particular limitation on the method of forming the buried conductor, such as a method of forming a wiring after selectively forming a film of tungsten in the connection hole by CVD. [Second Embodiment] In the first embodiment, the adhesion layer is removed after the formation of the metal silicide. However, in this embodiment, the adhesion layer of the connection hole is left. This step will be described with reference to FIGS. 4A will be described. For example, an element isolation insulating film 21 is formed on an N-type substrate 10 and a diffusion layer 11 is formed. Normal pressure CV for the interlayer insulating film 22
D is formed and heat treatment is performed. The conditions of the diffusion layer, the insulating film formation, and the heat treatment are shown below. Diffusion layer formation : BF ₂ ⁺ ion implantation (35 keV, 3 × 10 ¹⁵ ions)
/ Cm ² ) Heat treatment (vertical diffusion furnace annealing, 900 ° C., N ₂ , 10
Min.) Insulating film formation : normal pressure CVD TEOS: 60 sccm, TMPO: 15 sccm, T
EB: 520 ° C. at 15 sccm, 2% by weight of boron (B), 5% by weight of phosphorus (P), 1200 nm- thick insulating film Heat treatment method : Vertical diffusion furnace annealing N ₂ : 100%, 750 ° C., 10 minutes, and then connection After resist patterning of the hole,
The structure shown in (a) can be obtained.

Next, as shown in FIG.
A connection hole 41 is opened by on-etching. This and
Etching is performed to obtain a tapered shape.
U. The processing conditions are shown below.Connection hole processing : Reactive ion etching: (−30 ° C., 5.3 Pa, 1
200W) CO: 200sccm, CHF_Three: 1000 sccm Just + 30% over-etching Diameter of opening of connection hole (opening of resist): 0.4 μm Depth of connection hole (thickness of insulating film): 1.2 μm Diameter of bottom of connection hole: approx. After opening the connection hole of 3 μm, as shown in FIG.
The contact is removed, contact ion implantation and heat treatment are performed.
After performing the pretreatment for removing the oxide film, the adhesion layer metal layer 30 is
For example, the entire surface is formed by magnetron sputtering,
Anneal the metal silicide layer 31 to the bottom of the contact hole.
Formed in the part. Examples of each condition are shown below.Activation of contact impurities : BF_Two, 20 keV, 3 × 10^Fifteenions / cm^Two Oxide film removal : H_TwoO: buffered hydrofluoric acid = 400: 1, 60 secondsAdhesion layer metal sputter : Collimated Ti: 30 nm (0.52 Pa, 8 kW, A
r35sccm, 300 ° C) TiN: 70 nm (0.78 Pa, 6 kW, N_Two: 42
sccm, Ar: 21 sccm, 300 ° C)Lamp annealing : 650 ° C, 1 atm, N_Two: 100%, 30 seconds Then, as shown in FIG.
For example, plasma SiO 2_TwoCVD and overall etch
The back is formed. Examples of forming conditions are shown below.Insulation film formation : Plasma CVD TEOS: 800 sccm, O_Two: 600 sccm, 1
133.2Pa 400 ° C, RF 700W, film thickness 100nmEtch back : Reactive ion etching (-30 ° C,
2.7 Pa, 500 W) CHF_Three: 50 sccm just + 30% overetching Sidewall thickness: 100 nm After the formation of the sidewall 24, as shown in FIG.
A thin adhesion layer metal layer 32 is formed by a sputtering method,
A tungsten film 33 is entirely formed by a thermal CVD method.
Examples of each processing condition are shown below.Second adhesion layer metal sputter : TiN: 30 nm (0.78 Pa, 6 kW, N_Two: 42
sccm, Ar: 21 sccm, 300 ° C)Blanket W film CVD : 600 nm (10.7 kP
a, WF₆: H_Two: Ar = 40: 400: 2250sc
cm, 450 ° C.) Next, as shown in FIG.
After forming the buried conductor 34 of the connection hole by ching,
Barrier metal layer 36a, aluminum
Alloy layer 36b and cap metal layer 36c
The entire surface is formed by the Ron sputtering method, and the photoresist
Conductor wiring by turning and anisotropic ion etching
A layer 36 is formed.Embedded conductor processing : 1st STEP (W etching): 45.5 Pa, 275 W, SF₆: Ar: He = 110: 90: 5 sccm 2nd STEP (TiN etching): 6.5 Pa, 250 W, Ar: Cl_Two= 75: 5scc
m 3rdSTEP (W overetch): 32.5 Pa, 70 W, SF₆: Ar: He = 20: 1
0: 10sccm Conductor wiring layer formation : Barrier metal: Ti: 20 nm (0.52 Pa, 2 kW, Ar35sc)
cm, 300 ° C.) TiN: 20 nm (0.78 Pa, 6 kW, N_Two; 42
sccm, Ar 65 sccm, 300 ° C.) Aluminum alloy: Al-0.5% Cu: 500 nm (0.52 Pa, 15)
kW, Ar; 65 sccm, 300 ° C. Cap metal: Ti: 10 nm (0.52 Pa, 2 kW, Ar; 35 s)
ccm, 300 ° C.) TiN: 100 nm (0.78 Pa, 6 kW, N2; 4)
(2 sccm, Ar: 21 sccm, 300 ° C.)Conductive wiring reactive ion etching : BCl_Three/ Cl_Two= 100 / 150sccm, 1Pa,
Microwave 400mA, RF110W Just + 40% overetching The fine connection hole formed by the above process is before the adhesion layer is formed.
Connection hole top diameter of φ0.4μm (Hole aspect ratio
3.0), the bottom Ti film thickness is 5 nm or more.
Filmed, P⁺Si contacts exhibit ohmic characteristics
Was. Also, by forming insulating sidewalls, narrow wiring
Because the pitch does not become borderless contact,
100% yield of 1,000,000 steps contact chain
there were.

In the above example, the adhesion layer metal is TiN
Various materials such as TiW, Co, Ni, Ta, etc. or their compounds can be used in addition to the / Ti film, and the buried conductor can also be Cu, Al, or other low resistivity metal in addition to tungsten. It is. Furthermore, in the above example, as a method of forming the buried conductor, a method of forming a wiring by etching back after forming the W layer was described. Alternatively, after forming a conductor on the entire surface, this is patterned into the wiring. Then, there is a method of forming a wiring with the same conductor. Further, there is no particular limitation on the method of forming the buried conductor, such as a method of forming a wiring after selectively forming a film of tungsten in the connection hole by CVD.

[0024]

The semiconductor device of the present invention has low contact resistance, good adhesion between the wiring layer and the buried conductor in the connection hole, and high reliability. Further, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor device having low contact resistance and high wiring yield can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views each showing a manufacturing process of the semiconductor device of FIG. 1;

FIGS. 3 (d) to 3 (f) are cross-sectional views showing steps subsequent to FIG.

FIGS. 4A and 4B are cross-sectional views illustrating manufacturing steps of a semiconductor device according to a second embodiment of the present invention.

FIGS. 5D to 5F are cross-sectional views showing steps subsequent to FIG. 4;

FIGS. 6A and 6B are cross-sectional views showing steps of manufacturing a conventional semiconductor device.

FIG. 7 is a sectional view showing a semiconductor device manufactured by the process shown in FIG. 6;

8 (a) to 8 (c) are cross-sectional views showing different manufacturing steps of a conventional semiconductor device.

9 is a cross-sectional view showing a semiconductor device manufactured by the manufacturing process shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... board | substrate, 21 ... element isolation insulating film, 22 ... interlayer insulating film, 24 ... insulating sidewall, 31 ... silicide layer (alloy layer), 34 ... embedded conductor, 36 ... wiring layer, 40 ... connection hole

Claims (5)

[Claims] A connection layer to which a wiring layer is to be connected; an interlayer insulating film covering the connection layer; an interlayer insulating film that penetrates the interlayer insulating film to reach the connection layer; A connection hole having a larger area, an insulating sidewall covering an inner peripheral wall of the connection hole, a buried conductor filling the connection hole, and a wiring layer wired on the interlayer insulating film. A semiconductor device having a structure in which the connected layer is electrically connected to the wiring layer via the buried conductor. 2. The semiconductor device according to claim 1, wherein the buried conductor is electrically connected to the connection layer via an alloy layer of the connection layer and a metal at the bottom of the connection hole. 3. A step of forming a connection hole having an opening area larger than a bottom area in an interlayer insulating film covering a connection layer to which a wiring layer is to be connected; A semiconductor device comprising: a step of forming an insulating sidewall around the peripheral wall; and a step of filling the connection hole and forming a buried conductor connected to a wiring layer on the interlayer insulating film. Production method. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of forming an adhesion metal layer at the bottom of the connection hole after opening the connection hole. 5. A step of forming the alloy layer at the bottom of the connection hole by reacting the connected layer and the contact metal layer after forming the contact metal layer, and removing an unreacted contact metal layer. 5. The method for manufacturing a semiconductor device according to claim 4, comprising: