JPH10327059A - Driving method and driving circuit for electrostatic induction transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To drive a static induction transistor(SIT) at a low ON voltage and with a small switching loss by applying the forward bias voltage of a value smaller than the value of the built-in voltage of a pn junction composed of a gate area and a drift area between a gate and a source at the time of conducting the SIT in a forward direction. SOLUTION: By adding a forward bias between the gate and the source, since the width of a depletion layer generated in the junction of a first conductive drift area and a second conductive gate area is narrowed, a conducting area is widened and the ON voltage at the time of forward direction conducting is reduced. Also, in the range of the time 11-20 μsec, the gate voltage VG is set to the value larger than 0 V and smaller than the built-in voltage. For instance, since the built-in voltage is 2.7 V, the voltage VG is set to 2.5 V. At the time, the SIT maintains an ON state. Then, since a part between a gate electrode and a source electrode is biased in the forward direction, the ON voltage is lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a circuit for driving an electrostatic induction transistor used in a power converter or the like.

[0002]

2. Description of the Related Art With the demand for higher power and higher frequency of power converters, it has been desired to develop a semiconductor switching element which not only has a large controllable current but also operates at high speed with low loss. There are the following two methods to meet such demands.

One method is to use silicon, which is most frequently used today, as an element material, review the combination of the element structure and the operating principle, and further improve the performance of existing elements.
Since this method can utilize highly established manufacturing technology and a lot of knowledge, it is easy to improve device performance,
There is a problem that the performance is limited by the physical theoretical limit of silicon, and a significant improvement in device performance cannot be expected.

The other is to review the raw materials of the device,
There is a method for realizing a high-performance power semiconductor device far beyond the limit of silicon. For example, when silicon carbide (hereinafter, referred to as SiC) is used, the performance of the device is more than 10 times that of a device using silicon.
ctron Device Letters, Vol. 10, No. 10, pp. 455 (198
It is shown in 9). The reason why a device having excellent element performance can be realized by using SiC is that the avalanche breakdown electric field is large. For example, Si
C has an avalanche breakdown field as large as about 10 times that of silicon and can reduce the electric resistance of the drift layer of the element by about two orders of magnitude, according to the literature: IEEE Transaction of Electron Device.
s, Vol. 40, No. 3, p. 645 (1993).
For this reason, great expectations are placed on reducing the power loss that occurs when the element is in the ON state.

In order to aim for a next-generation power semiconductor device using SiC, a unipolar type is desirable. This is because a large-capacity device that satisfies all three basic requirements of high speed, low loss, and voltage control can be expected.

A MOSFET (Metal Oxide Semiconductor Field)
Effect Transistor) is a typical unipolar switching element. In recent years, however, problems with MOSFETs using SiC have become apparent. In a DMOS (Double Diffusion MOS) structure in which a p-base region is formed by ion implantation, the electron mobility of the inversion layer is small and the low resistance of the drift layer cannot be utilized.
InternationalHigh Temperature Electronics Conferen
ce, pp. XI-3, June (1994). Further, in the trench MOS structure, dielectric breakdown occurs in the oxide film before SiC avalanche breakdown due to insufficient dielectric strength of the trench SiO ₂ film. Therefore, it is necessary to increase the thickness of the drift layer in order to prevent the electric field at the interface between SiC and the oxide film from exceeding the critical electric field of the oxide film. ISPSD96, pp. 119-122,
May, (1996).

As another unipolar switching element, a static induction transistor (hereinafter referred to as SIT) is used.
ion Transistor). Since the SIT is a kind of the junction type FET, the problems of the mobility at the oxide film interface and the dielectric strength of the oxide film as described above can be avoided.

Hereinafter, the outline of the structure of the SIT and the main points of the operation will be described with reference to FIG. In the semiconductor substrate 10 in which the SIT shown in FIG. 2 is formed, for example, an epitaxial layer having a lower impurity concentration than the drain region 11 is formed as a drift region 12 on the upper surface of the n-type high impurity concentration drain region 11.
From the surface of the drift region 12
As shown in the figure, a pair of slightly deep island-shaped gate regions 13 are formed, and an n-type source region 14 is formed at a high impurity concentration on the surface of the drift region 12 between the p-type gate regions 13. And drain region 11 via drain electrode 25.
, A drain terminal D, a gate terminal G via the gate electrode 26, a gate terminal G from the gate region 13, and a source terminal S via the electrode 27 from the source region 14. This SIT is
In the off state, by applying a reverse bias between the gate and the source, the voltage between the drift region 12 and the gate region 13 is reduced.
The depletion layer mainly extends from the n-junction to the drift region 12. Therefore, a potential barrier for electrons is generated in a region called a channel in which a current flows between a source and a drain between the gate region 13 and another adjacent gate region 13, and a source-drain voltage can be blocked.

[0009]

In order to obtain a high blocking gain when producing an SIT of SiC, it is necessary to use a SiC SIT.
The gate needs to be made finer than the SIT. There are two possible reasons for this. One is S
In the case of iC, since it is difficult to drive in the dopant by thermal diffusion, a deep gate layer cannot be formed. Another is that since the impurity concentration of the drift layer is high, it is difficult to pinch in the depletion layer channel region.

As described above, in the case of SIT of SiC, the resistance of the drift layer can be reduced, but on the other hand, there is a problem that the on-resistance is increased in spite of using SiC because the gate needs to be miniaturized.

As a means for reducing the on-resistance of a conventional SIT having a miniaturized gate, a method of reducing the on-voltage by applying a forward bias to the SIT gate has been proposed [Reference: IEDM Tech. Dig., pp. 676, (1978)], and is referred to as a bipolar mode SIT (hereinafter, referred to as BSIT). In BSIT, a forward bias is applied to the gate, and holes serving as minority carriers are injected from the gate region into the drift region, so that the resistance of the drift region 12 is reduced by conductivity modulation.

[0012] While the SIT is of the voltage driven type,
Since the SIT is of a current drive type, the drive power is large. Further, at the time of turn-off, there is a problem that turn-off time and turn-off loss increase due to accumulation of minority carriers.

[0013]

In order to solve the above-mentioned problems, the present invention provides a forward bias voltage having a value smaller than a value of a built-in voltage of a pn junction formed by a gate region and a drift region during forward conduction of an SIT. Is applied between the gate and the source.

By applying a forward bias between the gate and the source, the width of the depletion layer formed at the junction between the first conductivity type drift region and the second conductivity type gate region is reduced, so that the conduction area is increased, and the forward conduction is increased. ON voltage at the time can be reduced. Further, by making the gate forward bias smaller than the built-in voltage, minority carriers are not injected from the gate region to the drain region, and only a current corresponding to the capacity of the depletion layer flows between the gate and the source. Can be kept low. Further, since no minority carriers are accumulated in the SIT, the turn-off time and the turn-off loss do not increase. That is, the high-speed switching performance which is a characteristic of the unipolar element is not lost.

[0015]

FIG. 1 is a block diagram showing an embodiment of the present invention.
The method for driving the gate of the iC-SIT is shown. The junction structure of the SIT is the same as that of the conventional example shown in FIG. 2, but single crystal SiC is used as a semiconductor material. The SIT of this embodiment is 10
When a gate reverse bias voltage of V or more is applied, it has a withstand voltage of 900V class. Further, in the present SIT, the built-in voltage between the gate electrode and the source electrode, that is, the built-in voltage of the pn junction between the gate region and the drift region is about 2.7V.

As shown in FIG. 1, a drain electrode is connected to one end of a main power supply, and a source electrode is connected to the other end of the same main power supply. The gate electrode and the source electrode are connected to a gate drive circuit, and a gate voltage V is applied between these electrodes.
_G is given. V _G between the gate electrode and the source electrode
There is forward biased to a positive value, V _G is the case of negative values are reverse biased.

In this embodiment, the time is 0 to 10 μs
As -20V and V _G in the range of c, it has a SIT off. At this time, SIT is equal to the withstand voltage of 9
Main power supply voltage up to 00V can be blocked. Next, in the range of time 10~11μsec, -20V and V _G
To 2.5V. Since the bias direction between the gate electrode and the source electrode changes from reverse bias to forward bias, SIT turns on. Next, at times 11 and 2
The range of 0μsec, V _G is set to a value smaller than the larger and the built-in voltage than 0V. In this embodiment, since the built-in voltage is 2.7V, V _G is 2.
It is set to 5V. At this time, the SIT maintains the ON state. Further, since the area between the gate electrode and the source electrode is biased in the forward direction, the on-state voltage is reduced for a reason described later. Next, in the time range 20～21Myusec, varying the V _G from 2.5V to -20 V. The SIT is turned off because the bias direction between the gate electrode and the source electrode changes from forward bias to reverse bias. At this time, the magnitude of V _G at the turn-off before the on state is less than the built-in voltage, the internal SIT, is hardly injected minority carriers from the gate region into the drift region. Therefore, the turn-off time and the turn-off loss of the SIT are reduced. Time 21μsec
Thereafter, it changes in such V _G as described above is repeated.

[0018] Figure 3, the gate voltage V _G at the time of forward bias in the above embodiment, the current density JF 400A /
The relationship between the ON voltage V _{on in} cm ² and the turn-off loss _Err is shown. Range of V _G is from 0V to 2.7V is with increasing V _G, the ON voltage V _on is suddenly lowered from 1.2V to 0.5V. However, V _G is not observed little difference from 2.7V to 5.0V, indicating the saturation characteristics. On the other hand, the turn-off loss E _rr, V _G is rapidly increased from the vicinity of 2.7V.

[0019] With the increase in V _G, described why the on-voltage drops. 1 embodiment, since the built-in voltage is about 2.7V, V _G is 0 to 2.7
At V, the injection of minority carriers from the gate region to the drift region hardly occurs. That is, the conductivity modulation hardly causes a decrease in the ON voltage. According to the inventor's study results, factor on the voltage drop, the depletion layer spreading from the gate region is narrowed by V _G, it decreases the potential barrier of the channel portion in the SIT channel portion X-X 'in FIG. 1 And the conduction area increases. Hereinafter, the results of the study by the present inventors will be described in detail.

FIG. 4 shows the distribution of potential barriers for electrons along the channel section XX 'of FIG. For comparison, the potential barrier distribution is also shown for the case of Si (silicon) -SIT in FIG. Incidentally, V _G is 0V i.e. non-bias state.

In FIG. 4, the built-in voltages for Si and SiC are about 0.7 V and about 2.7 V, respectively. Therefore, the potential barrier of SiC is about four times higher than that of silicon. Further, the relationship between the built-in voltage and the depletion layer width W in the non-bias state can be expressed by equation (1).

[0022]

(Equation 1)

Here, ε is a dielectric constant, V _bi is a built-in voltage, q is a unit charge of electrons, and N _d is an impurity concentration of the drift region. Since the built-in voltage of SiC is about four times that of silicon, the depletion layer of SiC is about twice as wide as silicon when ε and _Nd are the same. Biasing the gate electrode and the source electrode in the forward direction is equivalent to reducing the potential barrier and increasing the conduction area by narrowing such a wide depletion layer.

As is clear from FIG. 4, since the potential barrier in the non-bias state is originally low in silicon, the effect is small even if the potential barrier is lowered by forward biasing between the gate electrode and the source electrode. on the other hand,
In SiC, since the potential barrier is high even in a non-bias state, the effect of reducing the potential barrier and increasing the conductive area is significant.

[0025] On the other hand, in FIG. 3, the reason for V _G is the turn-off loss from the vicinity of 2.7V sharply increases is as follows. When V _G exceeds built-in voltage, the holes that are minority carriers are injected from the gate region to the drift region. Since this hole becomes a residual carrier at the time of turn-off, _Err increases.

[0026] As described above, in the embodiment of FIG. 1, the turn-off before the on-state, provides a gate voltage V _G so as to bias between the gate electrode and the source electrode in the forward direction, the value of the further V _G Is larger than 0 V and smaller than the built-in voltage, the ON voltage of the SIT can be reduced from the non-bias state, and the loss generated during turn-off switching can be reduced.

[0027] Figure 5 illustrates a built-in voltage V _bi, the relationship between the decrease width [Delta] V _F of the on-voltage when providing the gate voltage V _G to bias between the gate electrode and the source electrode in the forward direction. Here, ΔV _F is the difference between the ON voltage in the non-bias state and the ON voltage in the gate forward bias state. V _G
Is set to 90% of V _bi . The junction structure of the SIT is the same as that of FIG. 2, and the gate depth X _j is 2 μm.
m, channel width W _ch is 1.0 μm, drift region thickness L
_n is 8 μm, and the impurity concentration N _d of the drift region is 1.53.
× 10 ¹⁶ / cm ³ . Up to V _bi of 2.0 V, the effect of the gate forward bias is small. On the other hand, V _bi is 2.0V
Beyond this level, the reduction width ΔV _F of the ON voltage increases.

In FIG. 5, V _bi exceeds 2.0 V.
The reason why the gate forward bias is effective in reducing the ON voltage in IT will be described with reference to FIGS. In each of the drawings, the SIT bonding structure is the same as in FIG.

FIG. 6 shows a built-in voltage V of silicon or the like.
_In the SIT of a semiconductor material having a small _bi , the depletion layer 28 expands in a non-bias state between the gate electrode and the source electrode. Due to the depletion layer extending from the junction of gate region 13 and drift region 12 to drift region 12, the width W _{current of the} region where current flows in the channel portion during conduction is reduced, but a region where no depletion layer is formed in the channel portion remains ing. For this reason, current flows relatively easily even between the gate electrode and the source electrode in a non-bias state. Therefore, when a bias is applied between the gate electrode and the source electrode in the forward direction, the effect of reducing the on-state voltage is effective but not significant.

On the other hand, in a SIT made of a semiconductor material such as SiC having a larger V _bi than Si, a region where a depletion layer is generated in a channel portion is wider than that in the case of silicon. Therefore, W _current becomes 0 as shown in FIG. That is, the depletion layer is pinched off in the channel portion. At this time, in a non-bias state between the gate electrode and the source electrode, a potential barrier of electrons is increased in the entire channel portion, so that current hardly flows even when a power supply voltage is applied between the source electrode and the drain electrode. For this reason, the ON voltage becomes very high. In such a state, when a slight forward bias is applied between the gate electrode and the source electrode, W
_{Since the current} becomes larger than 0, the state becomes the same as that of FIG. 6 and the on-voltage suddenly decreases.

FIG. 8 shows the built-in voltages V _bi and W
The relationship of _current (conduction width of channel) is shown. As V _bi increases, W _current decreases. When V _bi exceeds 2 V, W _current becomes 0 μm. SIT at this time
Is in a state as shown in FIG. 7, that is, a state in which the effect of the gate forward bias is remarkably exhibited.

As apparent from the description of FIGS. 6 to 8, the effect of the present invention is particularly remarkable in the SIT in which the depletion layer pinches off in the channel region due to the built-in voltage V _bi in the gate non-bias state. Therefore, the present invention is particularly effective in an SIT made of a semiconductor material having a large energy band gap.

FIG. 9 shows the relationship between the band gap E _g and the built-in voltage V _bi . As for E _g and V _bi , the relations of Expressions (2) and (3) are known.

[0034]

(Equation 2)

Here, n _i is the intrinsic carrier concentration, N _c is the state density of the conduction band, N _v is the state density of the valence band, E _g is the band gap, k is the Boltzmann constant, and T is the absolute temperature.

[0036]

(Equation 3)

Here, q is the electron charge, N _A is the acceptor concentration, and N _D is the donor concentration. FIG. 9 is obtained from these relationships, and shows that a semiconductor material having a larger E _g has a larger V _bi . As described above, V _bi is 2V
In the case where it exceeds, the effect of the present invention is great. Therefore, FIG.
Therefore, when an SIT is manufactured using a semiconductor material having a band gap E _{g of} more than 2.4 eV, the effect of the present invention is particularly enhanced. As a specific semiconductor material, SiC (E
_g : 3.0 eV), gallium nitride GaN (E _g : 3.4 e)
V), zinc sulfide ZnS (E _g : 3.7 eV), diamond (E _g : 5.5 eV) and the like.

The decrease width ΔV of the ON voltage as described with reference to FIG.
The relationship between _F and the built-in voltage V _bi actually varies depending on the channel depth X _j , the channel width W _ch , and the drift layer concentration N _d . Therefore, FIG. 10 shows that X _j is 0.5 to 5.0 μm.
m, W _ch is 0.2 to 5.0 .mu.m, N _d is 5 × 10 ¹⁴ ~5 ×
The relationship between ΔV _F and V _bi when changing in the range of 10 ¹⁶ cm ^-2 is shown. The filled part is Δ in the above condition range.
V _F range. From this figure, the built-in voltage is 1.
It can be seen that the gate driving method of the present invention is effective for semiconductor materials having a band gap of 12 V or more, that is, silicon or more. That is, the present invention can be applied to an SIT made of silicon.

FIG. 11 shows an SIT gate drive circuit according to an embodiment of the present invention. This drive circuit includes a DC power supply 88,
The collector terminal is connected to the positive terminal of DC power supply 88.
It includes a PN transistor 85 and a resistor 84 having one terminal connected to the emitter terminal of the NPN transistor 85. The other terminal of the resistor 84 is connected to the gate terminal of the SIT 81, and the negative terminal of the DC power supply 88 is connected to the source terminal of the SIT 81. A Zener diode 82 is connected between the gate and source of the SIT. Here, the cathode and the anode of the Zener diode 82 are connected to the gate terminal and the source terminal of the SIT, respectively.
The Zener voltage of the Zener diode 82 is set to be equal to or less than the built-in voltage between the gate and the source of the SIT.

In FIG. 11, when an ON command signal is applied to an input terminal 89, an NPN transistor 85 is turned on, and a DC power supply 88 receives a gate of SIT from a DC power supply 88 via a resistor 84.
A forward bias on-gate voltage is applied between the sources. At this time, the on-gate voltage applied between the gate and source of the SIT by the Zener diode 82 becomes a value equal to or less than the built-in voltage, and the same effect as the driving method of FIG. 1 is produced. In this embodiment, a circuit for applying a reverse bias off-gate voltage is omitted.

FIG. 12 shows another embodiment of the SIT gate drive circuit according to the present invention. The Zener diode 82 in FIG. The circuit configuration and operation other than the diode 91 are the same as those in FIG. However, the cathode of the diode 91 is connected to the source terminal of the SIT, and the anode of the diode 91 is connected to the gate of the SIT. The built-in voltage of the diode 91 is lower than the built-in voltage between the gate and the source of the SIT. As a result, the on-gate voltage applied between the gate and source of the SIT becomes equal to or less than the built-in voltage,
The same effect as the driving method of FIG. 1 is obtained. In this embodiment, if the same semiconductor material is used for the SIT 81 and the diode 91, the magnitude relationship between the built-in voltage of the SIT 81 and the built-in voltage of the diode 91 is maintained even if the built-in voltage changes due to a temperature change. Therefore, the operation stability of the SIT against a temperature change is improved.

FIG. 13 shows another embodiment of the SIT driving method according to the present invention. Gate voltage V _G is turned gate pulse and the turn-off gate pulses are alternately repeated, FIG 13 is mainly showing one gate pulse for turning on. In A of FIG. 13, the maximum voltage of the turn-on gate pulse is less than the built-in voltage V _bi between SIT gate-source, V _G is raised and lowered in a stepwise manner at the time of turn-on and turn-off. As a result, SIT at turn-on and turn-off
Does not change rapidly but changes slowly.
Therefore, it is possible to prevent transient overvoltage from occurring in the parasitic inductance of the circuit and the inductance of the load. The voltage value of the number and each step of the step change in V _G can be appropriately selected.

[0043] In B of FIG. 13, the value of V _G in certain period or SIT ON steady state after turn-on is larger than V _bi, the on-voltage by injecting carriers from the gate region of the SIT into the drift region Reduce enough. Further, keeping a certain period immediately before the transition to the turn-off gate pulse, the value of V _G to a value smaller than V _bi. As a result, when the turn-off gate pulse is applied, the number of carriers stored in the SIT is reduced.
Turn-off loss can be reduced.

FIG. 14 shows an embodiment of a power SIT inverter device according to the present invention. This inverter device includes a pair of DC terminals 121 and 122 and three AC terminals 131 to 133 equal in number to AC phases. A DC power supply is connected to the DC terminals, and the SITs 101 to 106 are switched. The power is converted to AC power and output to the AC terminal. Note that flywheel diodes 111 to 116 are connected in anti-parallel to the SITs 101 to 106, respectively. A series of SITs 101 and 102, 1 connected in series are connected between DC terminals.
03 and 104, and both ends of 105 and 106 are connected.
AC terminals B1 to B3 are extracted from the series connection point of the two SITs in each set of SITs. Although not shown in FIG. 14, the SITs 101 to 106 are switching-controlled by the driving method or the driving circuit according to the present invention. By implementing the driving method or the driving circuit of the present invention, the power loss of the SIT inverter device is reduced.

FIG. 15 shows a configuration in which the rectifier (AC / DC converter) is constituted by a synchronous rectifier circuit based on SIT switching and includes a forward characteristic of the SIT and a rectifier circuit constituted by a pn junction diode having the same withstand voltage as the SIT. 5 shows the forward characteristics of a pn junction diode when the pn junction diode is used. Here, the semiconductor material of both the SIT and the pn junction diode is SiC. The SIT is driven by the driving method or the driving circuit according to the present invention. As shown in FIG. 15, pn junction diode of SiC, although an increase in the ON voltage V _F from a current begins to flow less, the absolute value of the ON voltage to the built-in voltage V _bi is as large as about 2.7V is large Become. For this reason, when a rectifier is configured with a pn junction diode of SiC, the power loss of the device increases. On the other hand, according to the present invention, since the power loss of the SIT can be reduced and the current path inside the SIT does not pass through the pn junction, the effect of V _bi does not appear on the forward characteristics as shown in FIG. Therefore, a low-loss rectifier can be realized.

[0046]

As described above, according to the present invention,
The SIT can be driven with low on-voltage and low switching loss. Further, according to the present invention, the power loss of the power converter using the SIT is reduced, and the device can be downsized.

[Brief description of the drawings]

FIG. 1 shows a gate driving method for an SIT according to an embodiment of the present invention.

FIG. 2 is a sectional structural view of an SIT.

FIG. 3 shows a relationship between a gate forward bias, an on-voltage, and a turn-off loss.

FIG. 4 is a potential distribution in a channel portion.

FIG. 5 is a relationship between a built-in voltage and an on-voltage reduction width.

FIG. 6 is a cross-sectional view of a SIT made of a semiconductor material having a small V _{bi in} a gate non-bias state.

FIG. 7 is a cross-sectional view of a SIT made of a semiconductor material having a large V _{bi in} a gate non-bias state.

FIG. 8 shows a relationship between a built-in voltage and a conduction width.

FIG. 9 shows a relationship between a band gap and a built-in voltage.

FIG. 10 shows the relationship between the built-in voltage and the ON voltage reduction width when the channel width, channel depth, and drift layer carrier concentration are changed.

FIG. 11 shows an embodiment of an SIT drive circuit according to the present invention.

FIG. 12 shows another embodiment of the SIT drive circuit according to the present invention.

FIG. 13 shows another embodiment of the driving method according to the present invention.

FIG. 14 is a main circuit of a SIT inverter device according to an embodiment of the present invention.

FIG. 15 shows forward characteristics when SiC-SIT is used for a synchronous rectifier circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Drain region, 12 ... Drift region, 13 ... Gate region, 14 ... Source region, 25 ...
Drain electrode, 26 gate electrode, 27 source electrode,
28 depletion layer, 81 electrostatic induction transistor, 82 zener diode, 84 resistance, 85 NPN transistor, 88 DC power supply, 89 input terminal, 91 diode, 101 to 106 electrostatic induction transistor, 111
~ 116 ... flywheel diode, 121-122
... DC terminals, 131 to 133 ... AC terminals.

Claims (14)

[Claims] 1. A method of driving an electrostatic induction transistor having a drain electrode, a source electrode, and a gate electrode provided on a semiconductor substrate, wherein a voltage is applied between the source electrode and the gate electrode when the electrostatic induction transistor is on. A period in which the value of the forward gate voltage is kept higher than 0 (V) and equal to or lower than the built-in voltage between the source electrode and the gate electrode. Method. 2. The method of driving an electrostatic induction transistor according to claim 1, wherein a band gap of a semiconductor material of said semiconductor substrate is larger than a band gap of silicon. . 3. The method for driving an electrostatic induction transistor according to claim 2, wherein a band gap of a semiconductor material of said semiconductor substrate is 2.4 eV or more. 4. A method for driving an electrostatic induction transistor according to claim 1, wherein the semiconductor material of said semiconductor substrate is any one of silicon carbide, gallium nitride and diamond. A method for driving a transistor. 5. The method of driving an electrostatic induction transistor according to claim 1, wherein the electrostatic induction transistor extends from a surface of the semiconductor substrate into the semiconductor substrate, and has a conductivity type opposite to that of the semiconductor substrate. A plurality of semiconductor regions, the drain electrode contacting the semiconductor substrate, the source electrode contacting the semiconductor substrate between the plurality of semiconductor regions, and the gate electrode contacting the plurality of semiconductor regions. The method for driving an electrostatic induction transistor, wherein the built-in voltage is a built-in voltage of a pn junction between the semiconductor substrate and the semiconductor region. 6. The method for driving an electrostatic induction transistor according to claim 1, wherein the value of the gate voltage in the ON state changes stepwise. 7. The method for driving an electrostatic induction transistor according to claim 6, wherein a gate voltage in a forward direction is always higher than 0 (V) and equal to or lower than the built-in voltage in the on-state. Driving method of the electrostatic induction transistor. 8. The method of driving an electrostatic induction transistor according to claim 7, wherein the value of the gate voltage increases stepwise. 9. The method of driving an electrostatic induction transistor according to claim 7, wherein the value of the gate voltage decreases stepwise. 10. The method of driving an electrostatic induction transistor according to claim 6, wherein in the on-state, a period in which the value of the gate voltage is larger than 0 (V) and smaller than the built-in voltage; A method for driving an electrostatic induction transistor, characterized in that there is a period during which the value of the voltage is higher than the built-in voltage. 11. A drain electrode provided on a semiconductor substrate,
A driving circuit for an electrostatic induction transistor including a source electrode and a gate electrode, further comprising: a Zener diode connected in parallel between the source electrode and the gate electrode of the electrostatic induction transistor, wherein a Zener voltage of the Zener diode is A driving voltage of the static induction transistor, which is lower than a built-in voltage between the source electrode and the gate electrode. 12. A drain electrode provided on a semiconductor substrate,
A driving circuit for an electrostatic induction transistor including a source electrode and a gate electrode, comprising a diode connected in parallel between the source electrode and the gate electrode of the electrostatic induction transistor, wherein the built-in voltage of the diode is A driving circuit for an electrostatic induction transistor, wherein the driving voltage is equal to or lower than a built-in voltage between a source electrode and the gate electrode. 13. A driving circuit for an electrostatic induction transistor according to claim 12, wherein a material of said semiconductor substrate and a material of said diode are the same semiconductor material. circuit. 14. A driving circuit for an electrostatic induction transistor according to claim 13, wherein said semiconductor material is any one of silicon carbide, gallium nitride and diamond. circuit.