JPH1032794A - Imaging device - Google Patents

Abstract

(57) [Problem] To provide an imaging apparatus capable of independently changing an aspect ratio of an image signal supplied to a main line system and an image signal signal supplied to a viewfinder system. A CCD image sensor (1R, 1G, 1B) is provided.
A digital image signal of the first aspect ratio generated by the process processing unit 4 based on the imaging output of the subject image by Aspect ratio conversion circuits 11, 12, 13 for cutting out and outputting;
The microcomputer 19 controls the operation mode of the aspect ratio conversion circuit 5 for extracting and outputting at least a part of the sample of the image represented by the digital image signal in the horizontal direction independently of the aspect ratio conversion circuits 11, 12, and 13. Control switching.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus having a function of converting an aspect ratio of a digital image signal.

[0002]

2. Description of the Related Art Television broadcasting has an aspect ratio of 4:
3 NTSC (National Television System Committe)
e) HDTV (High Dependency) with 16: 9 aspect ratio
finition television). Therefore, the present applicant has proposed an aspect ratio conversion device in Japanese Patent Application Laid-Open No. 5-252538. When converting the aspect ratio, the imaging apparatus to which the aspect ratio conversion device is applied supplies the image signal to the recording / reproducing system after converting the aspect ratio of the image signal, and when not converting the aspect ratio, The image signal is directly supplied to the recording / reproducing system without passing through the aspect ratio conversion device.

[0003]

By the way, in the above-mentioned image pickup apparatus, when the aspect ratio of the image signal is converted, not only the image signal supplied to the main line system but also the image signal supplied to the viewfinder system is converted. As a result, the image based on the main line image signal and the image based on the viewfinder image signal have the same content.For example, the entire surroundings of the object being imaged can be checked with the viewfinder, It is not necessary to observe only the main part of a moving object with a viewfinder.

An object of the present invention is to provide an image pickup apparatus capable of independently changing the aspect ratio between an image signal supplied to a main line system and an image signal signal supplied to a viewfinder system.

Another object of the present invention is to provide an image pickup apparatus capable of cutting out a part of an image based on an image signal supplied to a main line system and supplying an image signal enlarged in the horizontal direction to a viewfinder system. It is in.

Still another object of the present invention is to provide an image pickup apparatus capable of supplying an image signal including images on both sides in the horizontal direction of an image based on an image signal supplied to a main line system to a viewfinder system. is there.

[0007]

According to the present invention, a digital image signal having a first aspect ratio generated by an image pickup means based on a subject image in a horizontal direction of an image represented by the digital image signal is provided. First converting means for cutting out and outputting at least a part of the samples;
And the second conversion means for cutting out and outputting at least a part of the sample in the horizontal direction of the image represented by the digital image signal independently of the first conversion means. Controlled by means. Then, by controlling the number of samples cut out by the first converting means to be smaller than the number of samples cut out by the second converting means, the digital image signal is represented by a digital image signal output from the first converting means. A digital image signal of an image obtained by enlarging a part of the image in the horizontal direction is output from the second conversion means. Further, by controlling the number of samples cut out by the first conversion means to be larger than the number of samples cut out by the second conversion means, the digital image signal having the first aspect ratio generated by the imaging means is controlled. Is converted into a digital image signal having a second aspect ratio obtained by cutting out a part of the image represented by the digital image signal output from the second conversion means, and outputting the digital image signal. Further, the operation of the first and second conversion means is switched between the first mode and the second mode by the control means, and
In this mode, the number of samples cut out by the first conversion means is controlled to be larger than the number of samples cut out by the second conversion means, so that the digital image signal output from the first conversion means can be represented. A digital image signal of an image obtained by enlarging a part of the image
Of the digital image signal output from the first conversion means by controlling the number of samples cut out by the second conversion means in the second mode. A digital image signal of an image obtained by enlarging a part of the image to be horizontally enlarged is output from the second conversion means.

That is, an image pickup apparatus according to the present invention comprises an image pickup means for generating a digital image signal having a first aspect ratio based on a subject image, and a predetermined group delay added to the digital image signal generated by the image pickup means. And a first conversion unit that cuts out and outputs at least a part of a sample in the horizontal direction of the image represented by the digital image signal, and converts the first conversion unit into a digital image signal generated by the imaging unit. A second conversion unit that cuts out and outputs at least a part of samples in the horizontal direction of the image represented by the digital image signal independently of the first conversion unit, A display unit connected to the conversion unit and displaying an image based on the digital image signal output from the second conversion unit. And operating means for setting an operation mode of said first and second converting means including a first mode, when the first mode is set by said operation means,
The number of samples cut out by the first conversion means is equal to the second
And control means for controlling the first and second conversion means so as to be smaller than the number of samples cut out by the conversion means.

According to another aspect of the present invention, there is provided an image pickup apparatus for generating a digital image signal having a first aspect ratio based on a subject image, and a predetermined group delay for the digital image signal generated by the image pickup means. And a first conversion unit that cuts out and outputs at least a part of a sample in the horizontal direction of the image represented by the digital image signal, and converts the first conversion unit into a digital image signal generated by the imaging unit. A second conversion unit that cuts out and outputs at least a part of samples in the horizontal direction of the image represented by the digital image signal independently of the first conversion unit,
Display means for displaying an image based on the digital image signal output from the second conversion means, and an operation mode of the first and second conversion means including at least a third mode. Operating means for setting, and when the third mode is set by the operating means, the number of samples cut out by the first converting means is larger than the number of samples cut out by the second converting means. Control means for controlling the first and second conversion means.

Further, an image pickup apparatus according to the present invention includes an image pickup means for generating a digital image signal having a first aspect ratio based on a subject image, and a predetermined group delay added to the digital image signal generated by the image pickup means. And a first conversion unit that cuts out and outputs at least a part of a sample in the horizontal direction of the image represented by the digital image signal, and converts the first conversion unit into a digital image signal generated by the imaging unit. A second conversion unit that cuts out and outputs at least a part of samples in the horizontal direction of the image represented by the digital image signal independently of the first conversion unit, Display means connected to the conversion means for displaying an image based on the digital image signal output from the second conversion means; And operating means for setting the operation mode of the second converting means, based on the setting of the operating means, at least, it is the number of samples cut out of the first conversion means,
The first mode for controlling the first and second conversion means so that the number of samples cut out by the second conversion means is smaller than the number of samples cut out by the first conversion means is the second conversion mode. And control means for controlling switching to the second mode for controlling the first and second conversion means so as to increase the number of samples cut out by the means.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The present invention is applied to, for example, a video camera having a configuration as shown in FIG. This video camera has three primary color imaging signals R (red) and G according to imaging light of a subject.
CCD image sensor 1 that outputs (green) and B (blue)
A color video camera of a three-panel type provided with R, 1G, 1B, wherein each color image signal R, G, B from the CCD image sensor 1R, 1G, 1B is correlated double sampling (CD
S: Correlated Double sampling) circuit 2R, 2G, 2
The signals are supplied to A / D converters 3R, 3G, and 3B via B, and are converted into digital signals by the A / D converters 3R, 3G, and 3B, respectively, and converted into digital signals. It is being supplied.

In this video camera, the brightness data VFY for the viewfinder is supplied from the process unit 4 to the D / A converter 6 via the aspect ratio conversion circuit 5, and the brightness for the viewfinder is supplied by the D / A converter 6. The data VFY is converted into an analog signal and supplied to the viewfinder 7 as an image signal for the viewfinder. The aspect ratio conversion circuit 5 includes four FIFO memories 5a to 5d connected in parallel.

The video camera has a processing unit 4
From the main line system luminance data Y and color difference data RY, BY
Is D / D via the aspect ratio conversion circuits 11, 12, and 13.
The data is supplied to the A converter 9 and the D / A converter 9 converts the main line luminance data Y and the color difference data RY and BY to analog signals, which are supplied to the encoder 10 as the main line luminance signal and color difference signal. It has become. Each of the aspect ratio conversion circuits 11, 12, 13 includes four FIFO memories 11a to 11d, 1 connected in parallel.
2a to 12d and 13a to 13d.

Further, the video camera has an operation unit 18.
And a microcomputer (hereinafter, referred to as a microcomputer) 19 for controlling the aspect ratio conversion circuit 5 and the like in accordance with the operation.

The three CCD image sensors 1R, 1G,
1B decomposes, for example, imaging light incident from an unillustrated imaging lens via an unillustrated optical low-pass filter into three primary color light components by an unillustrated light separation prism,
The three primary color images of the subject image are captured, and the respective color imaging signals R, G,
B is output. The CCD image sensor 1R,
1G and 1B have an aspect ratio of 16: 9. Therefore, an image signal composed of the image signals R, G, and B of each color also has an aspect ratio of 16: 9.

Here, the CCD image sensors 1R, 1
G and 1B are driven by a CCD driver 17 to which a clock CK1 is supplied from a timing generator 16. Note that the timing generator 16 divides the frequency (36 MHz) of the clock CK1D supplied from the clock generation circuit 20 by 、 and changes the frequency synchronized with the synchronization signal supplied from the sync generator 15 to 18
MHz clock CK1 and generates the clock CK1.
To the CCD driver 17 and A / D converters 3R, 3
G, 3B.

The clock generation circuit 20 supplies a clock CK1D having a frequency of 36 MHz to the selector 23 and to the 1/2 frequency dividing circuit 21. The 1/2 frequency dividing circuit 21 operates at a frequency (36 MHz) of the clock CK1D.
Is divided into 1/2, and a clock C having a frequency of 18 MHz
K1 is supplied to the selector 23, the inverter 30, and the 1/2 frequency dividing circuit 22. The 1/2 frequency dividing circuit 22 outputs the clock C
The frequency of K1 (18 MHz) is divided by half, and a clock CK1H1 having a frequency of 9 MHz is supplied to the selector 23 and the phase correction circuit 27. The inverter 30 is 1 /
The clock CK1 output from the divide-by-2 circuit 21 is inverted and the clock CK1 ′ is supplied to the selector 23.

Further, the phase correction circuit 27 outputs the clock CK
Three clocks CK1H2, CK1H3, and CK1H having the same frequency (1 MHz) as 1H1 and different phases by π / 2.
4 is generated and supplied to the selector 23.

The clock generation circuit 24 generates a clock CK3D having a frequency of 27 MHz, and supplies the clock CK3D to the selector 23 and also to the に frequency dividing circuit 25. The 分 frequency divider 25 divides the frequency (27 MHz) of the clock CK3D into １ ／,
Select the clock CK3 having a frequency of 13.5 MHz to the selector 2
3, supply to the inverter 31 and the 1/2 frequency dividing circuit 26. The 分 frequency dividing circuit 26 divides the frequency (13.5 MHz) of the clock CK3 into 、, and sets the frequency to 6.
The 75 MHz clock CK3H1 is supplied to the selector 23 and the phase correction circuit 28. The inverter 31 is １ ／
The clock CK3 output from the frequency dividing circuit 25 is inverted and the clock CK3 ′ is supplied to the selector 23.

Further, the phase correction circuit 28 controls the clock CK
Three clocks CK3H2, CK3H3, C with the same frequency (6.75 MHz) as π3H and different phases by π / 2
K3H4 is generated and supplied to the selector 23. Note that these three clocks CK3H2, CK3H3, CK3H
4 is used in other than the six operation modes described later.

Further, the switching signal generator 29 operates in the mode for performing the aspect conversion, and has a phase of π in synchronization with the horizontal synchronizing signal HD from the sync generator 15.
Generates the offset switching signal ID _o and switching signal IDe, supplies a switching signal IDe to the selector 23 indicating the switching signal ID _o and an even line period showing the odd line period "High" level in the "High" level.

The microcomputer 19 selects write clocks WCK1 and WCK2, read clocks RCK1 and RCK2, and output enable signals OE1 and OE2 according to the mode setting of the operation unit 18 from the clocks supplied to the selector 23. The selector 23 is controlled as described above. The selector 23, based on the control of the microcomputer 23,
Write clock WCK1, Read clock RCK1
And the output enable signal OE1 are supplied to the aspect ratio conversion circuits 11, 12, and 13, respectively, and the write clock WCK2, the read clock RCK2, and the output enable signal OE1 are supplied to the aspect ratio conversion circuit 5.

The CDS circuits 2R, 2G, and 2B extract data portions from the color image signals R, G, and B supplied from the CCD image sensors 1R, 1G, and 1B, and remove random noise. G and B are supplied to A / D converters 3R, 3G and 3B.

The A / D converters 3R, 3G, and 3B synchronize with the clock CK1 from the timing generator 16 and, for example, each color imaging signal R, G, and B each color imaging data R, G, each of which consists of 10 bits. , B, and supplies the color image data R, G, B to the process unit 4.

The process section 4 includes an A / D converter 3R,
For each color image data R, G, B supplied from 3G, 3B, the clock CK1D
A so-called camera process such as image enhancement processing, pedestal addition, non-linear processing such as gamma knee, etc. is performed based on.
Then, the process unit 4 performs a matrix process on the color image data R, G, and B to generate a clock CK, respectively.
The image data is converted into image data consisting of luminance data Y and chrominance data RY, BY having a rate equal to 1D, that is, a 36 MHz rate, and luminance data VFY for the viewfinder is supplied to the aspect ratio conversion circuit 5 and the main line system is converted. The luminance data Y and the chrominance data RY, BY are supplied to the aspect ratio conversion circuits 11, 12, and 13.

When the aspect ratio conversion circuit 5 performs aspect ratio conversion on the luminance data VFY for the viewfinder, the luminance data VFY of the odd-numbered lines is
The luminance data VFY of the even line is written into the memories 5a and 5b and the FIFO memories 5c and 5b.
The data is written to the IFO memory 5d. Specifically, FIF
The luminance data VFY of the odd-numbered sample of the odd-numbered line is written into the O memory 5a, and the luminance data VF of the even-numbered sample of the odd-numbered line is written into the FIFO memory 5b.
Y is written. Further, the luminance data VFY of the odd-numbered sample of the even-numbered line is written to the FIFO memory 5c, and the luminance data VFY of the even-numbered sample of the even-numbered line is written to the FIFO memory 5d.

In this case, when the luminance data VFY of the odd lines is written in the FIFO memories 5a and 5b based on the write clock WCK2, the even lines are read from the FIFO memories 5c and 5d based on the read clock RCK2. Is read out, and the read clock RC
When the odd line luminance data VFY is being read from the FIFO memory 5a and the FIFO memory 5b based on K2, the FI signal is read based on the write clock WCK2.
The luminance data VFY of the even line is written to the FO memory 5c and the FIFO memory 5d.

Note that the FIFO memory 5a and the FIFO memory 5b collectively have at least one horizontal period (hereinafter, one horizontal period).
The FIFO memory 5c and the FIFO memory 5d have a capacity capable of storing at least the 1H period luminance data VFY.

The main line luminance data Y and color difference data R−
Aspect ratio conversion circuits 11, 1 to which Y, BY are supplied
In the aspect ratio conversion in 2, 13 as well,
Similarly to the aspect ratio conversion circuit 5, the samples of the odd lines are stored in FIFO memories 11a, 12a, 13a and FIFO memories.
The data is written into the O memories 11b, 12b and 13b, and the samples of the even lines are stored in the FIFO memories 11c, 12c and 13b.
c and FIFO memories 11d, 12d, 13d.

Next, the conversion of the aspect ratio will be described in more detail. The case where the aspect ratio is converted from 16: 9 to 4: 3 using the aspect ratio conversion circuit 5 as an example will be described with reference to FIG. In FIG. 2, input data is luminance data VFY supplied from the process unit 4 to the aspect ratio conversion circuit 5, and is synchronized with the H-cycle horizontal blanking signal BLK, and includes 1H period including the horizontal blanking period. There are N samples of data inside.

In this case, the aspect ratio conversion circuit 5
Is a write clock WCK2 having a frequency of 18 MHz.
The luminance data VFY is written to the FIFO memories 5a to 5d in synchronization with (CK1), and the written luminance data VF is written.
The aspect ratio is converted by reading a part of Y in synchronization with a read clock RCK2 (CK3) having a frequency of 13.5 MHz.

That is, when the operation section 18 sets the operation mode for converting the aspect ratio of the VF system or the main line system from 16: 9 to 4: 3, the microcomputer 19 sets the clocks CCK and WCK2 as the write clocks WCK1 and WCK2, respectively.
K1 and CK1 'are selected and clocks CK3 and CCK are used as read clocks RCK1 and RCK2, respectively.
The selector 23 is controlled so as to select K3 '. Further, the microcomputer 19 converts the cutout signal C1 corresponding to this operation mode into the main line aspect ratio conversion circuits 11, 12,
13 and also supplies the cutout signal C2 to the VF aspect ratio conversion circuit 5.

Here, the cut-out signals C1 and C2 are 1H
In the FIFO memory into which valid image data for the period is taken, the number of samples for the 1H period including invalid image data corresponding to a blanking period is set to N, and the number of samples for the 1H period is changed from the last sample to the preceding sample. An address indicating a reading start position of the image data defined by the number of samples L counted toward the front, that is, an image data cutting start position is given. Note that the microcomputer 19 can set the cutout start position based on the setting of the operation unit 18.

The clocks CK1 and CK are respectively written in the FIFO memories 5a and 5b as write clocks WCK2.
1 'is supplied. Then, the write clock WC
In synchronism with K2 (CK1, CK1 '), N samples of luminance data (luminance data of all samples in the 1H period) VFY on odd lines are stored in FIFO memories 5a,
5b are written alternately.

In FIG. 2, CKox is a write clock WCK2 for writing and reading luminance data VFY of odd-numbered lines to and from the FIFO memories 5a and 5b.
(CK1, CK1 ') and read clock RCK2 (C
K3, CK3 '). The CKox is a two-phase clock having a phase corresponding to an odd-numbered sample and a phase corresponding to an even-numbered sample of an odd-numbered line. This CK
The x in ox indicates a clock corresponding to both odd and even samples. That is, CK1, CK
1 ′ and CK3 and CK3 ′ are shown, respectively. Also, OEo
x indicates an output enable signal OE2 for reading out and outputting luminance data VFY of odd-numbered lines from the FIFO memories 5a and 5b. This OEox is “High” during the writing period of the odd line luminance data VFY.
During the period of reading the luminance data VFY of the odd line, a two-phase clock having a phase corresponding to the odd sample and a phase corresponding to the even sample of the odd line, that is, the read clocks RCK2 (CK3, CK).
3 '). These two-phase clocks correspond to CKxo and CKxe in FIG. 5 described later.

During the writing period of the luminance data VFY of the odd-numbered line, the OEox is fixed at the “High” level, so that the luminance data VFY is not output from the FIFO memories 5a and 5b, and the write clock WCK2 ( CK1, CK1 '), the luminance data VFY of the odd-numbered lines is stored in the FIFO memory 5 for each sample.
a and 5b are written alternately. During the reading period of the odd line luminance data VFY, the OEox repeatedly changes between the “High” level and the “Low” level in synchronization with the read clock RCK2 (CK3, CK3 ′). VFY is read out and output by the read clock RCK2 (CK3, CK3 ').

That is, the luminance data VFY of the odd-numbered lines
During the writing period, as shown in FIG. 3, the luminance data VFY (o1, o3, o5...) Of the odd-numbered samples of the odd-numbered lines are written into the FIFO memory 5a.
In the IFO memory 5b, the luminance data VFY (o2, o4, o6...) Of the even-numbered samples of the odd-numbered lines are written.

In the next 1H period, that is, in the reading period of the luminance data VFY of the odd-numbered line, the luminance data V of the E sample written after the cutout start position C2.
FY is alternately read from the FIFO memories 5a and 5b for each sample, and output as odd-line luminance data VFY. In FIG. 2, OUToo indicates luminance data VFY of an odd-numbered sample row of an odd line read from the FIFO memory 5a, and OUToe indicates luminance data VFY of an even-numbered sample row of an odd line read from the FIFO memory 5b. Show. This OUToo corresponds to OUTxo in FIG. 5, and OUToe corresponds to OU in FIG.
Txe corresponds.

In FIG. 2, CKex is the FIF
The luminance data V of the even lines are stored in the O memories 5c and 5d.
Write clock WC for writing and reading FY
K2 (CK1, CK1 ') and read clock RCK2
(CK3, CK3 ′). In addition, OEex
Indicates an output enable signal OE2 for reading out and outputting even-numbered-line luminance data VFY from the FIFO memories 5c and 5d.

The FIFO memories 5c and 5d also store
Similarly to the IFO memories 5a and 5b, the luminance data VFY of the even-numbered lines is written by the write clock WCK2 (CK1, CK1).
CK1 ′), the clipping start position is set based on the clipping signal C2, and the luminance data VFY is clipped in synchronization with the read clock RCK2 (CK3, CK3 ′). However, FIFO memories 5a and 5b and FIFO memories 5c,
5d indicates that the writing and reading of the luminance data VFY are in opposite phases.

That is, the luminance data V of the odd-numbered line
During the FY reading period, the luminance data VFY of the even-numbered line
, And the write clock WCK
2 (CK1, CK1 '), N samples of luminance data (luminance data of all samples in the 1H period) VFY in even lines are stored in FIFO memories 5c, 5c for each sample.
d is written alternately. In other words, as shown in FIG. 3, the luminance data VFY (e1, e3, e5...) Of the odd-numbered samples of the even-numbered lines are stored in the FIFO memory 5c.
Is written into the FIFO memory 5d, and the luminance data VFY (e2, e
4, e6...) Are written. Then, in the next 1H period, the luminance data VFY of the E sample written after the cutout start position C2 is alternately read from the FIFO memories 5a and 5b for each sample, and output as the luminance data VFY of the odd line.

In this aspect ratio conversion circuit 5, F
Since the period during which the luminance data VFY is read from the IFO memories 5a to 5d is the 1H period, the read clocks RCK2 (CK3, CK) are set from the set cutout start position.
3 ′), the luminance data VFY of E (= N × RCK2 / WCK2) samples is read out with a group delay of 1H. Therefore, in the case of the mode for converting the aspect ratio from 16: 9 to 4: 3, the aspect ratio conversion circuit 5 converts 3/4 of the luminance data VFY for the 1H period into the 1H period while a group delay of the 1H period occurs. It can be cut out as data.

As described above, the aspect ratio conversion circuit 5
Is provided with two FIFO memories used for writing the luminance data VFY at a certain timing when converting the aspect ratio of the luminance data VFY, and two FIFO memories used for reading the luminance data VFY at the above timing. . Therefore, the clock rates of the write clock WCK2 and the read clock RCK2 can be halved as compared with the case where one FIFO memory is used. As a result, there is no need to use an expensive FIFO memory that can support a write clock and a read clock having a high clock rate.

As shown in FIG. 4, in the aspect ratio conversion circuit 5 composed of four FIFO memories 5a to 5d connected in parallel, at the time of the aspect conversion, the read clock RCK2 (CKoo) and the output enable signal OE2 are output.
By supplying (OEoo) to the FIFO memory 5a, the luminance data VFY of the odd-numbered sample of the odd line is read from the FIFO memory 5a, and the read clock RCK2 (CKoe) and the output enable signal OE2 are output.
By giving (OEoe) to the FIFO memory 5b, the luminance data VFY of the even-numbered samples of the odd-numbered lines is read from the FIFO memory 5b, and the read clock RCK2 (CKeo) and the output enable signal OE2 are output.
By supplying (OEeo) to the FIFO memory 5c, the luminance data VFY of the odd-numbered samples of the even-numbered line is read out from the FIFO memory 5c, and further, the read clock RCK2 (CKee) and the output enable signal OE2 (OEee) are output. 5d, the luminance data VFY of the even-numbered sample of the even-numbered line is read out from the FIFO memory 5d.

FIG. 5 shows a FIFO read control pattern at the time of aspect conversion in such an aspect ratio conversion circuit 5. As shown in FIG. 5, a read clock RCK2 (CKxo) for reading the odd-numbered sample luminance data VFY and a read clock RCK2 for reading the even-numbered sample luminance data VFY.
(CKxe) have opposite phases to each other. The read clock RCK2 (CKxo) corresponds to the frequency (27) of the clock CK3D generated by the clock generation circuit 24.
MH3) is a clock CK3 obtained by dividing the frequency into 1/2 by the 1/2 frequency dividing circuit 25. The read clock RCK2 (CKxe) is obtained by inverting the phase of the clock CK3 by the inverter 31.
K3 '.

Here, it is shown that x of CKxe and CKxo is common to all lines. That is, CK
oe and CKee are the same clock, and CKo
o and CKeo are the same clock.

Then, the read clock RCK2 (CK
xo), the FIFO memory 5a or the FIFO memory 5
c, the output data O of the odd-numbered sample read from c.
UTxo outputs the read clock RCK2 (CKx
Output enable signal OE2 (OExo) synchronized with o)
Is output during the period of the “Low” level, and the FIFO memory 5 is output by the read clock RCK2 (CKxe).
b or the output data OUTxe of the even-numbered sample read from the FIFO memory 5d is an odd number because the output enable signal OE2 (OExo) synchronized with the read clock RCK2 (CKxo) is output during the period of “Low” level. Output data O of the second sample
UTxo and output data OUTxe of the even-numbered sample
Are multiplexed and output as output data OUT alternately arranged for each sample.

That is, in the four FIFO memories 5a to 5d connected to each other and constituting the aspect ratio conversion circuit 5, the output enable signal OE2 is set to "Hi".
gh ”level, the output is in a high impedance state, and the“ Low ”level output enable signal O
The output is alternatively selected by the supply of E2, and the luminance data VFY is read.

Next, a case where the aspect ratio is not converted will be described. Here, a case where the aspect ratio is not converted will be described with reference to FIG. 6 using the aspect ratio conversion circuit 5 as an example. In FIG. 6, the input data is the luminance data VFY supplied from the process unit 4 to the aspect ratio conversion circuit 5, and is the horizontal blanking signal BL of H cycle.
It is synchronized with K and becomes N samples of data during the 1H period including the horizontal blanking period.

In this case, the aspect ratio conversion circuit 5
Is, for example, a write clock WCK having a frequency of 9 MHz.
2 (CK1H1 to CK1H4), the luminance data VFY is written into the FIFO memories 5a to 5d, and all the written luminance data VFY is read out in synchronization with the 9 MHz read clock RCK2 (CK1H1 to CK1H4). The luminance data VFY is output as it is without converting the ratio. As a result, even when the aspect ratio conversion is not performed and the aspect ratio conversion is not performed, the aspect ratio conversion circuit 5 applies a group delay of 1H period to the luminance data VFY and outputs the same as when the luminance data VFY is extracted. can do.

That is, when the operation unit 18 sets the through mode in which the aspect ratio is not converted, the microcomputer 19 selects the clocks CK1H1 to CK1H4 whose phases have been corrected by the phase correction circuit 27 as the write clock WCK2 and the read clock RCK2. The selector 23 is controlled so as to perform the operation. The selector 23 is connected to the microcomputer 19
Of the aspect ratio conversion circuit 5 based on the control of
A write clock WCK2 (CK1H1 to CK1H4), a read clock RCK2 (CK1H1 to CK1H4) and an output enable signal OE2 (CK1H1 to CK1H4) whose phases are shifted by π / 2 are supplied to the memories 5a to 5d. That is, the FIFO memory 5a
Are supplied with a write clock WCK2 (CK1H1), a read clock RCK2 (CK1H1) and an output enable signal OE2 (CK1H1), and the FIFO memory 5b is supplied with a write clock WCK2 (CK1H1).
2) The read clock RCK2 (CK1H2) and the output enable signal OE2 (CK1H2) are supplied,
The write clock WCK2 (C
K1H3), read clock RCK2 (CK1H3)
And an output enable signal OE2 (CK1H3), and a write clock WCK2 (CK1H4) and a read clock RCK2 are supplied to the FIFO memory 5d.
(CK1H4) and the output enable signal OE2 (CK1
H1 to CK1H4) are supplied. Here, the read clock RCK2 (CK1H1 to CK1H4) has a predetermined phase delay with respect to the write clock WCK2 (CK1H1 to CK1H4).

In this through mode, the microcomputer 19 uses the number of samples N for the 1H period as the number of samples L defining the address indicating the start position of the cutout of the image data, so that the top of the FIFO memories 5a to 5d can be used. A cutout signal C2 for specifying an address is supplied to the aspect ratio conversion circuit 5. The FIFO memories 5a to 5d
When the cutout signal C2 is supplied from the microcomputer 19, the cutout start position is set to the first address. That is, the FIFO memories 5a to 5d store all the luminance data V
FY is set to be read.

Then, the luminance data VFY supplied to the aspect ratio conversion circuit 5 is equal to the write clock WCK2.
In synchronization with (CK1H1 to CK1H4), the data is sequentially distributed and written to the FIFO memories 5a to 5d for each sample. Therefore, in the FIFO memories 5a to 5b,
In the 1H period, N samples of luminance data VFY are sequentially sorted for each sample, so that N / 4 samples of luminance data VFY are written.

That is, as shown in FIG. 7, the write clock WCK2 (CK1H1) is stored in the FIFO memory 5a.
, The luminance data VFY (x1, x5,
x9...), the luminance data VFY (x2, x6, x10...) are written to the FIFO memory 5b every four samples by the clock WCK2 (CK1H2), and the clock WCK2 (CK) is written to the FIFO memory 5c.
1H3), the luminance data VFY (x
3, x7, x11...) Are written.
The FO memory 5d stores the luminance data VFY (x1, x5, x) every four samples by the clock WCK2 (CK1H4).
9 ...) are written. Note that x in x1, x2,... Indicates that either of the odd and even lines may be used.

Here, in FIG. 6, CKxx is FI
The luminance data VFY is stored in the FO memories 5a to 5b line by line.
Clock WCK2 for writing and reading data
(CK1H1 to CK1H4) and read clock RCK
2 (CK1H1 to CK1H4). This CK
xx is a four-phase clock (CK1H1 to CK1H4) having a phase corresponding to each sample. Also, OEx
x indicates an output enable signal OE2 (CK1H1 to CK1H4) for reading out and outputting luminance data VFY for each line from the FIFO memories 5a to 5d. The OExx is stored in the FIFO memories 5a to 5d as 1
A four-phase clock having a phase corresponding to each sample of the luminance data VFY read out for each line, that is, a four-phase clock that goes to the “Low” level for only one sample output period in synchronization with the read clocks RCK2 (CK1H1 to CK1H4). It is.

Then, the FIFO memories 5a, 5b, 5
The luminance data VFY written to c and 5d respectively is
Read clock RCK2 (CK1H1 to CK1H4)
, All the samples are read out in synchronism with the above, giving a group delay of 1H period as in the case of performing the aspect ratio conversion.

As described above, in the aspect ratio conversion circuit 5 in the through mode, the luminance data VFY of the odd-numbered or even-numbered lines of the N samples is written in the write clock W in the 1H period.
FI at the timing of CK2 (CK1H1 to CK1H4)
While being written to the FO memories 5a to 5d,
All the luminance data VFY of the even or odd lines written before the H period are read clock RCK2 (CK).
1H1 to CK1H4). Note that the read clock RCK2 must be set within a range where the write timing cannot catch up with the read timing.
(CK1H1 to CK1H4) are the write clocks WC
It has a predetermined phase delay with respect to K2 (CK1H1 to CK1H4). Thereby, the aspect ratio conversion circuit 5
Can output the luminance data VFY without changing the group delay regardless of the presence or absence of the aspect ratio conversion. Therefore, it is not necessary to adjust the phase of the signal processing system provided after the aspect ratio conversion circuit 5 irrespective of the presence or absence of the aspect ratio conversion.

FIG. 8 shows a FIFO read control pattern in the aspect ratio conversion circuit 5 in the through mode.

In FIG. 8, CKoo is a FIFO
A read clock RCK2 (CK1H1) for reading the luminance data VFY from the memory 5a is shown.
Indicates a read clock RCK2 (CK1H2) for reading the luminance data VFY from the FIFO memory 5b, and CKeo indicates the luminance data VCK from the FIFO memory 5c.
Read clock RCK2 (CK) for reading FY
1H3), and CKee is a read clock R for reading the luminance data VFY from the FIFO memory 5d.
CK2 (CK1H4) is shown. Also, OUToo
Indicates an output from the FIFO memory 5a read by CKoo, OUToe indicates an output from the FIFO memory 5b read by CKoe, and OUTe
o is a FIFO memory 5c read by CKeo
OUTee indicates an output from the FIFO memory 5d that is read by CKee.

That is, in this through mode, the frequency obtained by dividing the frequency (36 MHz) of the clock CK1D generated by the clock generation circuit 20 into １ ／ by the 分 frequency divider circuits 21 and 22 is obtained. 9M
Hz clock CK1H1, and three clocks CK1H2, CK1H3, and CK having different phases by π / 2 generated from the clock CK1H1 by the phase correction circuit 27.
1H4 receives the luminance data VF from the FIFO memories 5a to 5d.
Read clock RCK2 (CK1
H1 to CK1H4).

Each output O from the FIFO memories 5a to 5d read at a frequency of 9 MHz and read by four-phase read clocks RCK2 (CK1H1 to CK1H4).
In UToo, OUToe, OUTeo, and OUTee, one sample for every four samples shown by hatching in FIG. 8 is a four-phase output enable signal OE2 (CK1H1 to CK1H1).
CK1H4) is output and multiplexed during the output period in which it is at the “Low” level, and is output as output data OUT arranged in order for each sample.

The write clock WCK2, the read clock RCK2, the output enable signal OE2, and the cutout signal C2 are supplied to the aspect conversion circuit 5 to operate in the aspect ratio conversion mode and the through mode. , Each FIFO memory 5a to 5d
Clock input to each FIFO, and each FIFO
The output enable signal OE2 for the memories 5a to 5d operates as a different lock depending on High or Low.
That is, when the output enable signal OE2 is High, it operates as the read clock RCK, and when it is Low, it operates as the write clock WCK.

Next, the form of the aspect ratio conversion circuit according to the present invention will be described. Here, the aspect ratio conversion circuit 5 will be described as an example, but it goes without saying that the same applies to the other aspect ratio conversion circuits 11, 12, and 13.

In the aspect ratio conversion circuit 5 shown in FIG. 4, since the outputs of the FIFO memories 5a to 5d are directly connected to each other, each of the FIFO memories 5a to 5d is connected to the other FIFO memories 5a to 5d. Output capacity (11
pF) can be regarded as being added as a parasitic capacitance. Therefore, for example, when the luminance data VFY is output from the FIFO memory 5a, the luminance data VFY is affected by the output capacity of each of the other FIFO memories 5b, 5c, and 5d.
Good image data may not be output.

Therefore, the embodiment shown in FIG. 9 prevents such an adverse effect due to the output capacitance.

The aspect ratio conversion circuit 5 shown in FIG. 9 corresponding to the aspect ratio conversion circuit 5 in the above embodiment.
A is a FIFO memory 5a, 5b whose input side and output side are connected in parallel, and FIFO memories 5a, 5b.
b flip-flop 25 connected to the output side of b.
FIF with input side and output side connected in parallel
It has O memories 5c and 5d and a D flip-flop 26 connected to the output side of the FIFO memories 5c and 5d.

In the aspect ratio conversion circuit 5A, the write clock WCK2
Based on (CK1, CK1 '), the FIFO memory 5
The luminance data VFY of the odd-numbered lines are alternately written into the a and 5b during the writing period of the odd-numbered lines.
Even-line luminance data VFY is alternately written into the O memories 5c and 5d during the even-line writing period.
Then, the read clocks RCK2 (CK3, CK
3 ′), the luminance data VF of the odd-numbered lines are read from the FIFO memories 5a and 5b during the period of reading the odd-numbered lines.
Y are alternately read, and the FIFO memories 5c and 5
From d, the luminance data VFY of the even line is read alternately during the reading period of the even line.

As shown in FIG. 10, the D-flip-flop 25 operates when the 2H-cycle switching signal IDo generated by the switching signal generator 29 is at the "High" level. And the D-flip-flop 26 outputs the switching signal IDo.
And the switching signal IDe whose phase is shifted by π is “Hig
h "level. As a result, when the switching signal IDo is at the "High" level, the luminance data VFY of the odd line is read from the FIFO memories 5a and 5b, and when the switching signal IDe is at the "High" level,
Even line luminance data V from IFO memories 5c and 5d
FY is read.

Here, the clock generation circuit 24 described above
Clock CK1D supplied from clock generation circuit 20
Phase locked loop (PLL: Phase Locked
Loop), and as shown in FIG.
Matching the timing of the rising edge of the switching signal ID _o, clocks CK1 and CK3 immediately before the timing to produce state transition IDe generated at the boundary i.e. switching signal generator 29 of the readout period of the odd lines and the reading period of the even lines It is made to let.
This makes it possible to fix the number of samples of the luminance data VFY included in each of the odd-line readout period and the even-line readout period.

That is, the D-flip-flop 25 is
During the reading period of the odd-numbered line in which the switching signal IDo is at the “High” level, the FIFO memories 5a and 5
The luminance data VFY of the odd-numbered line read from b is latched and output based on the read clock RCK2. In addition, the D-flip-flop 26 outputs the even line luminance data VFY read from the FIFO memories 5c and 5d during the clock RCK during the reading period of the even line in which the switching signal IDe is at the “High” level.
2 and output.

As described above, the D flip-flops 25, 2
6 performs the same role as the switch, and the switching signal ID
When o is at the "High" level, the luminance data of the odd lines is read out via the D-flip-flop 25, and when the switching signal IDe is at the "High" level, the luminance data of the even lines is read through the D-flip-flop 2. Data VF
Y is read. Therefore, for example, the FIFO memory 5a stores the luminance data V through the D-flip-flop 25.
When FY is output, the D flip-flop 26
Eliminates the influence of the output capacities of the FIFO memories 5c and 5d, whereby good luminance data VFY is output.

In other words, FIFO memories 5a and 5b
Is FIFO via D-flip-flops 25 and 26
By being connected to the memories 5c and 5d, the luminance data VFY of the odd-numbered lines can be read without being affected by the output capacity from the FIFO memories 5c and 5d. Similarly, in the FIFO memories 5c and 5d,
The luminance data VFY of the even-numbered line is read without being affected by the output capacities from the FIFO memories 5a and 5b.

In the aspect ratio conversion circuit 5A having such a configuration, the outputs of the FIFO memories 5a and 5b are
The outputs of the FO memories 5c and 5d are D-flip-flops 2
5 and 26, there is no need to switch the output enable signal OE2 between the odd and even lines, and the FIFO memories 5a and 5c are supplied with the output enable signal OExo having a phase corresponding to the odd-numbered sample.
The FIFO memory 5b, 5d may be supplied with an output enable signal OExoe having a phase corresponding to the even-numbered sample.

Next, still another embodiment of the aspect conversion circuit according to the present invention will be described. It is to be noted that the same components as those of the above-described embodiment are denoted by the same reference numerals, and detailed description is omitted. Here, the aspect ratio conversion circuit 5 will be described as an example.

The aspect ratio conversion circuit 5B shown in FIG.
Is the F whose input side and output side are connected in parallel, respectively.
FIFO memories 5a and 5b and FIFO memories 5a and 5b
Circuit connected to the output side of the FIFO memory 5 and the FIFO memory 5 having the input side and the output side connected in parallel, respectively.
c, 5d, and a buffer circuit 36 connected to the output side of the FIFO memories 5c, 5d.

The operation of the buffer circuits 35 and 36 is reciprocally switched by the switching signal ID at the time of the aspect conversion.
The supply of the "high" level switching signal ID turns on the buffer circuit 35 and the buffer circuit 36 in a non-operating state, and supplies the "Low" level switching signal ID during the reading period of the even line. As a result, the buffer circuit 36 becomes inactive and the buffer circuit 36 becomes active. The output side of the buffer circuits 35 and 36 in the non-operating state is in a high impedance state.

In the aspect ratio conversion circuit 5B shown in FIG. 11, the buffer circuits 35 and 36 play the same role as the switches, and the switching signal ID is "High".
During the reading period of the odd-numbered line at level F
The luminance data VFY of the odd lines read from the IFO memories 5a and 5b is output via the buffer circuit 35, and during the reading period of the even lines in which the switching signal ID is at the "Low" level, the FIFO memories 5c and 5c 5d luminance data V read from even line
FY is output via the buffer circuit 36.

As described above, the FIFO memories 5a and 5b and the FIFO memories 5c and 5c are connected via the buffer circuits 35 and 36.
5d, the FIFO memory 5c,
The luminance data of the odd-numbered lines can be read from the FIFO memories 5c and 5d without being affected by the load capacity of 5d, and the loads generated by the FIFO memories 5a and 5b can be similarly read from the FIFO memories 5c and 5d. The luminance data of the even-numbered lines can be read out without being affected by the capacity.

Next, a case will be described in which the aspect ratio conversion of the main line image signal and the aspect ratio conversion of the VF system are independently controlled. Although the aspect ratio conversion of the main line is performed by the aspect ratio conversion circuits 11, 12, and 13, respectively, the aspect ratio conversion circuit 11 will be described as an example. However, other aspect ratio conversion circuits 1
Needless to say, the same applies to 2, 13.

Specifically, for example, as shown in FIG.
There are operation modes from type 1 to type 6.

Here, the CCD image sensors 1R, 1R
G and 1B have an effective pixel number of 500,000 pixels, an aspect ratio of 16: 9, and output an imaging signal of 1144 samples in a 1H period. That is, the CCD image sensors 1R, 1G, and 1B have an aspect ratio of 16:
9 are output.

Table 1 shows the clocks used as the write clocks WCK1 and WCK2 and the read clocks RCK1 and RCK2 in each of the operation modes from Type 1 to Type 6. In Table 1, CK1 "indicates two-phase clocks CH1 and CK1 ', CK3" indicates two-phase clocks CH3 and CK3', and CK1 "
1H ^* means four-phase clocks CK1H1 to CK1H4.

[0084]

[Table 1]

Further, Table 2 shows the number of cutout samples (E) and the number of samples (L) defining the cutout start position in the operation modes of type 1 to type 6.

[0086]

[Table 2]

First, the operation mode of type 1 will be described. When the operation unit 18 is operated to enter the type 1 operation mode, the microcomputer 19 supplies the clock CK1 ″ as the write clocks WCK1 and WCK2 of the aspect ratio conversion circuit 5 and the aspect ratio conversion circuit 11, respectively, as shown in Table 1. Select and select each read clock RCK1, R
The selector 23 is controlled so as to select the clock CK3 ″ as the clock CK2. Thus, the aspect ratio conversion circuit 5 causes the write clock WCK2 (CK
1 ″), the luminance data VFY of the odd-numbered line becomes F
The data is written to the FIFO memories 5a and 5b, and the luminance data VFY of the even lines is written to the FIFO memories 5c and 5d. Further, in the aspect ratio conversion circuit 11, in synchronization with the write clock WCK1 (CK1 ″), the luminance data Y of the odd line is written in the FIFO memories 11a and 11b, and the luminance data VFY of the even line is written in the FIFO memory 1b.
1c and 11d.

The microcomputer 19 outputs the write clocks WCK1 (CK1 "), WCK2 (CK1") and read clocks RCK1 (CK3 "), RCK2 (CCK).
K3 ″) are supplied to the aspect ratio conversion circuits 5 and 11. In the type 1 operation mode, the cutout signals C1 and C2 are 1 shown in Table 2.
Based on the number of samples L (1022) defining the cutout start position from the number of samples N (1144) for the H period,
Extraction start address = NL = 1144-1022 =
122 is given.

As a result, in the aspect ratio conversion circuit 5, the luminance data VFY up to the 122nd sample specified by the cutout start address 122 given by the cutout signal C2 is not read, and the read clock RCK2 (CK3 ″) is read. In synchronization with this, the luminance data VFY of the 123rd and subsequent samples of the odd-numbered lines are read from the FIFO memories 5a and 5b, and the luminance data VFY of the even-numbered lines of the 123rd and subsequent samples are read from the FIFO memories 5c and 5d.

Therefore, the aspect ratio conversion circuit 5
Every 1H period, the luminance data VFY of 858 samples at the center of the effective image area from the luminance data VFY of 1144 samples
FY is cut out, and the number of samples of the luminance data VFY for one line is reduced to 3/4. As a result, as shown in FIG. 12, the aspect ratio conversion circuit 5 can cut out a 4: 3 (12: 9) image from a VF 16: 9 image. Then, the aspect ratio conversion circuit 5 outputs luminance data VFY having an aspect ratio of 4: 3.
FY is converted to a view finder 7 via a D / A converter 6.
To supply.

Similarly, the aspect ratio conversion circuit 11
The number of samples of the luminance data Y for the line is reduced to 3/4.
As a result, as shown in FIG. 12, a 4: 3 image can be cut out from the 16: 9 main line image. The aspect ratio conversion circuit 11 outputs the 4: 3 luminance data Y, and supplies the luminance data Y to the encoder 10 via the D / A converter 9.

As described above, in this type 1 operation mode, the encoder 10 and the viewfinder 7 are supplied with image data having the same number of samples for one line. Therefore, the user can confirm the same image as the image of the imaging output on the viewfinder 7.

Next, the operation mode of the type 2 will be described. When the operation unit 18 is operated to enter the type 2 operation mode, the microcomputer 19 selects the clock CK1 ″ as the write clock WCK2 of the aspect ratio conversion circuit 5 and the clock CK3H1 as its read clock RCK2 as shown in Table 1. , Aspect ratio conversion circuit 11
The selector 23 is controlled so as to select the clock CK1 ″ as the write clock WCK1 and the clock CK3 as the read clock RCK1.
In the aspect ratio conversion circuit 5, the write clock WCK
2 (CK1 ″), the luminance data V of the odd-numbered line
FY is written to the FIFO memories 5a and 5b, and the luminance data VFY of the even-numbered lines are written to the FIFO memories 5c and 5d. In the aspect ratio conversion circuit 11, the luminance data Y of the odd-numbered lines is stored in the FIFO memories 11a and 11b in synchronization with the write clock WCK1 (CK1 ″).
Then, the luminance data Y of the even line is written into the FIFO memories 11c and 11d.

Further, the microcomputer 19 controls the write clocks WCK1 and WCK2 and the read clock RCK.
1 and RCK2 are supplied to the aspect ratio conversion circuit 5 and the aspect ratio conversion circuit 11, respectively. In the type 2 operation mode, the main line cutout signal C1 has the number of samples N for the 1H period.
From (1144), based on the number of samples L (1022) defining the cutout start position, the cutout start address =
NL = 1144-1022 = 122. Also,
The cut-out signal C2 of the VF system is based on the sample number N (1144) for the 1H period and the sample start address =
NL = 1144-837 = 307.

As a result, in the aspect ratio conversion circuit 5, the luminance data VFY up to the 307th sample specified by the cutout start address 307 given by the cutout signal C2 is not read out, but is supplied to the read clock RCK2 (CK1H). In synchronism, the luminance data VFY of the 308th and subsequent samples of the odd lines are read from the FIFO memories 5a and 5b, and the luminance data VFY of the 307th and subsequent samples of the even lines are read from the FIFO memories 5c and 5d. In the aspect ratio conversion circuit 11, the luminance data VFY up to the 122nd sample specified by the cutout start address 307 given by the cutout signal C2 is not read out, but is synchronized with the read clock RCK1 (CK3 ″). , One of odd lines from FIFO memories 11a and 11b.
The luminance data Y from the 23rd sample onward is read out, and the even-numbered line 1 is read from the FIFO memories 11c and 11d.
The luminance data Y of the 22nd and subsequent samples are read.

Therefore, the aspect ratio conversion circuit 5
For each 1H period, the luminance data VFY of 429 samples at the center of the effective image area are obtained from the luminance data VFY of 1144 samples.
FY is cut out, and the number of samples of the luminance data VFY for one line is reduced to 3/8. As a result, as shown in FIG. 12, the aspect ratio conversion circuit 5 cuts out a 2: 3 (6: 9) image from the VF-based 16: 9 image so that the cut out image becomes 4: 3. Expanding horizontally. That is, the aspect ratio conversion circuit 5 outputs the luminance data VFY
The number of samples of is reduced to ／, and this image is
The aspect ratio is converted to 4: 3 by magnifying twice. Then, the aspect ratio conversion circuit 5 supplies the brightness data VFY whose aspect ratio has been converted to the viewfinder 7 via the D / A converter 6.

Further, the aspect ratio conversion circuit 11 is 1H
For each period, 858 from the luminance data Y of 1144 samples
The luminance data Y of the sample is cut out, and the number of samples of the luminance data Y for one line is reduced to ／. As a result, as shown in FIG.
A 4: 3 (12: 9) image can be cut out from a 6: 9 image. Then, the aspect ratio conversion circuit 11
The luminance data Y having an aspect ratio of 4: 3 is output, and the luminance data Y is output to the encoder 10 via the D / A converter 9.
To supply.

Therefore, in this type 2 operation mode, the luminance data VFY supplied to the viewfinder 7
Is smaller than the number of samples for one line of the luminance data Y supplied to the encoder 10, a part of the image in the width direction of the captured output image is enlarged in the viewfinder 7. The image is displayed. Accordingly, the user can easily perform the manual focus adjustment because the main part of the image of the captured output can be enlarged and confirmed on the viewfinder 7.

Next, the operation mode of type 3 will be described. When the operation unit 18 is operated, the microcomputer 19 operates as a type 3 microcomputer.
In the operation mode, as shown in Table 1, as the write clock WCK2 and the read clock RCK2 of the aspect ratio conversion circuit 5, the clock CK1H ^*, ie, C
K1H1 to CK1H4 are selected, and the clock CK is used as the write clock WCK1 of the aspect ratio conversion circuit 11.
1 "as the read clock RCK1 and the clock C
The selector 23 is controlled so as to select K3 ″.

Therefore, the selector 23 supplies the aspect ratio conversion circuit 5 with the clock CK1H ^*, that is, the four-phase clock CK1 as the write clock WCK2.
H1 to CK1H4 are selected and supplied corresponding to the FIFO memories 5a to 5d. This aspect ratio conversion circuit 5
Assuming that all the odd-numbered and even-numbered lines are X lines as shown in FIG.
1 is stored in the FIFO memory 5a, and the second sample X
2 is stored in the FIFO memory 5b, and the third sample X
3 is stored in the FIFO memory 5c, and the fourth sample X
4 is stored in the FIFO memory 5d.

In the aspect ratio conversion circuit 11, in synchronization with the write clock WCK1 (CK1 ″), the luminance data Y of the odd lines is written to the FIFO memories 11a and 11b, and the luminance data Y of the even lines is written to the FIFO memory 11c. , 11d.

Further, the microcomputer 19 controls the write clocks WCK1, WCK2 and the read clocks RCK1, RCK.
The cutout signals C1 and C2 corresponding to CK2 are supplied to the aspect ratio conversion circuit 5 and the aspect ratio conversion circuit 11, respectively. In the type 3 operation mode, the main-line cutout signal C1 has the number of samples N (114
4), the sample number L (1
022), the cut-out start address = N−L =
1144-1022 = 122. The VF cutout signal C2 has a sample number N (11
44) The number of samples L defining the cutout start position
Based on (1144), the cutout start address = N−
L = 1144-1144 = 0 is given.

The aspect ratio conversion circuit 5 supplies the readout clock RCK2 (CK1H ^* ) by giving the cutout start address = 0 by the cutout signal C2.
In synchronization with the 1H period, 1144 samples of the luminance data VFY written to the FIFO memories 5a to 5b every 1H period are 1
Read from the sample. Further, the aspect ratio conversion circuit 11 receives the clipping start address = 122 by the clipping signal C1 and synchronizes the luminance data Y of the 123rd and subsequent samples of the odd-numbered line with the FIFO in synchronization with the read clock RCK1 (CK3 ″). The luminance data Y read from the memories 11a and 11b and from the 123rd and subsequent samples of the even-numbered lines are stored in the FIFO memories 11c and 11b.
11d.

Therefore, the aspect ratio conversion circuit 5
Every 1H period, the luminance data VFY of all the 1144 samples after the first sample is cut out from the luminance data VFY of 1144 samples written in the FIFO memories 5a to 5d, and the luminance data VFY of one line is output as it is. As a result, the aspect ratio conversion circuit 5 outputs (through) the luminance data VFY having the aspect ratio of 16: 9 as it is, and converts the luminance data VFY into the D / A converter 6.
Is supplied to the view finder 7 via the.

Also, the aspect ratio conversion circuit 11 has a 1H
FIFO memory 11a, 11b or FIFO
From the 1,144 samples of the luminance data Y written in the memories 11c, 11d, 858 samples of the luminance data Y from the 123rd sample are cut out, and the number of samples of the luminance data for one line is reduced to ／. As a result, as shown in FIG. 12, the aspect ratio conversion circuit 11 can cut out a 4: 3 (12: 9) image from a 16: 9 image. Then, the aspect ratio conversion circuit 5 outputs an image signal having an aspect ratio of 4: 3, and supplies this image signal to the encoder 10 via the D / A converter 9.

Accordingly, in this type 3 operation mode, the encoder 10 is supplied with the clipped image signal having the aspect ratio of 4: 3, and the viewfinder 7 is supplied with the uncut 16: 9 image signal. Is supplied as is. Thereby, the user can check an image in a wider range than the image of the imaging output on the viewfinder 7. In other words, it is possible to take an image of an object that may enter the recording image area by checking with the viewfinder 7 by moving the object or panning the camera.

Next, the type 4 operation mode will be described. When the operation unit 18 is operated to enter the type 4 operation mode, the microcomputer 19 selects the clock CK1 ″ as the write clock WCK2 of the aspect ratio conversion circuit 5 and the clock CK1H1 as its read clock RCK2 as shown in Table 1. , Aspect ratio conversion circuit 11
The clock CK1 "is used as the write clock WCK1 for the clock CK3" as the read clock RCK1.
The selector 23 is controlled so as to select. As a result, in the aspect ratio conversion circuit 5, the write clock W
In synchronization with CK2 (CK1 ″), the luminance data VFY of the odd line is written into the FIFO memories 5a and 5b, and the luminance data VFY of the even line is written into the FIFO memories 5c and 5d.
Is written to. Further, in the aspect ratio conversion circuit 11, the luminance data Y of the odd-numbered lines is stored in the FIFO memory 11 in synchronization with the write clock WCK1 (CK1 ″).
a, 11b are written, and the luminance data Y of the even line is F
The data is written to the IFO memories 11c and 11d.

[0108] Further, the microcomputer 19 outputs the write clocks WCK1 and WCK2 and the read clocks RCK1 and RCK1.
The cutout signals C1 and C2 corresponding to CK2 are supplied to the aspect ratio conversion circuit 5 and the aspect ratio conversion circuit 11, respectively. In the type 4 operation mode, the main line cutout signal C1 has the number of samples N (114
4), the sample number L (1
022), the cut-out start address = N−L =
1144-1022 = 122. The VF cutout signal C2 has a sample number N (11
44) The number of samples L defining the cutout start position
(899), the cut-out start address = NL
= 1144-899 = 245.

As a result, in the aspect ratio conversion circuit 5, the cutout start address = 245 is given by the cutout signal C2, so that the read clock R
In synchronization with CK2 (CK1H1), the FIFO memory 5
a, 5b, the luminance data VFY of the 246th and subsequent samples of the odd-numbered lines are read out.
From c and 5d, the luminance data VFY of the 246th and subsequent samples of the even line is read. In addition, in the aspect ratio conversion circuit 11, the cutout start address = 122 is given by the cutout signal C1, so that the luminance data Y of the 123rd and subsequent samples of the odd line is FIFO-synchronized with the read clock RCK1 (CK3 ″). The luminance data Y is read from the memories 11a and 11b, and the luminance data Y of the 123rd and subsequent samples of the even line is read from the FIFO memories 11c and 11d.

Therefore, in the aspect ratio conversion circuit 5, every 1H period, the luminance data VFY of 1144 samples written in the FIFO memories 5a to 5b is converted into 246
The luminance data VFY of 572 samples after the sample is cut out, and the number of samples of the luminance data VFY for one line is reduced to １ ／. As a result, the aspect ratio conversion circuit 5
As shown in FIG. 12, 8: 9 image is cut out from the VF 16: 9 image, and the cut out image is
6: 9. That is, the aspect ratio conversion circuit 5
Has an aspect ratio of 16: 9 by enlarging the image in which the number of samples of the luminance data VFY is halved twice in the horizontal direction. The aspect ratio conversion circuit 5
The luminance data Y having an aspect ratio of 16: 9 is supplied to the viewfinder 7 via the D / A converter 6.

In the aspect ratio conversion circuit 11, 1
FIFO memory 11a, 11b or FIFO
858 samples of luminance data Y are cut out from 1144 samples of luminance data Y written in the O memories 11c and 11d, and the number of samples of the luminance data Y for one line is reduced to 3/4. As a result, the aspect ratio conversion circuit 11
Is 4: 3 from the 16: 9 image as shown in FIG.
An image of (12: 9) can be cut out. And
The aspect ratio conversion circuit 11 outputs luminance data Y having an aspect ratio of 4: 3, and supplies the luminance data Y to the encoder 10 via the D / A converter 9.

Accordingly, in this type 4 operation mode, the encoder 10 is supplied with the luminance data Y cut out at 4: 3, is cut out at 8: 9 to the viewfinder 7, and is further doubled in the horizontal direction. An enlarged image signal of 16: 9 is supplied. As a result, an image obtained by enlarging an image obtained by cutting out a part of the main line image in the width direction can be observed by the viewfinder 7, so that manual focus adjustment can be easily performed.

In this type 4 operation mode, V
The frequency is 9 MHz as the read clock RCK2 of the F system.
By selecting the clock CK1H1 of z, an image having an aspect ratio of 16: 9 is displayed on the viewfinder 7 by enlarging the main line image twice in the horizontal direction. As indicated as 4 ′, the VF
The frequency is 6.75 as the system read clock RCK2.
By selecting the clock CK3H1 of MHz, the image of the main line system may be enlarged to 4/3 times in the horizontal direction and an image having an aspect ratio of 16: 9 may be displayed on the viewfinder 7.

Next, the operation mode of type 5 will be described. When the operation unit 18 is operated to enter the type 5 operation mode, the microcomputer 19 operates the aspect ratio conversion circuits 5 and 1.
1 as write clocks WCK1 and WCK2 and read clocks RCK1 and RCK2, respectively.
K1H ^*, that is, four-phase clocks CK1H1 to CK1H
The selector 23 is controlled so as to select No. 4. As a result, in the aspect ratio conversion circuit 5, the write clock R
Synchronously with CK2 (CK1H ^* ), 114 every 1H period
Four samples of luminance data VFY are stored in FIFO memories 5a to
5d is written. In addition, the aspect ratio conversion circuit 11
Then, in synchronization with the write clock RCK1 (CK1H ^* ), 1144 samples of luminance data Y are written to the FIFO memories 11a to 11d every 1H period.

Further, the microcomputer 19 controls the write clocks WCK1 and WCK2 and the read clock RCK.
1 and RCK2 are supplied to the aspect ratio conversion circuits 5 and 11, respectively. In the type 5 operation mode, the main and VF cutout signals C
1, C2 is the number of samples N (1
144), the number of samples L defining the cutout start position
Based on (1144), the cutout start address = N−
L = 1144-1144 = 0 is given.

In the aspect ratio conversion circuit 5, 1144 samples of luminance data VF are read from the FIFO memories 5a to 5d.
Y is read out in synchronization with the read clock RCK2 (CK1H ^* ). Similarly, the aspect ratio conversion circuit 11
The luminance data Y of 1144 samples is read from the FIFO memories 11a to 11d by the read clock RCK1 (CK1
H ^* ).

Therefore, the aspect ratio conversion circuit 5
In the 1H period, the luminance data VFY of one line is written by cutting out all the luminance data VFY of 1144 samples from the luminance data VFY of 1144 samples.
Y is output as it is. As a result, the aspect ratio conversion circuit 5 outputs (through) the luminance data VFY having the aspect ratio of 16: 9 as it is, and outputs this luminance data VFY to D.
The signal is supplied to the viewfinder 7 via the / A converter 6.

Similarly, the aspect ratio conversion circuit 11 outputs luminance data Y having an aspect ratio of 16: 9 by extracting all luminance data Y of 1144 samples from luminance data Y of 1144 samples in a 1H period. Then, this image signal is supplied to the encoder 10 via the D / A converter 9.

Accordingly, in this type 5 operation mode, the view finder 7 and the encoder 10 are simply passed through the aspect ratio conversion circuits 5 and 11, respectively.
6: 9 luminance data VFY, Y is supplied. Thereby, the user can check the image having the same angle of view as the 16: 9 imaging output on the viewfinder 7.

Next, the operation mode of type 6 will be described. The microcomputer 19 operates the operation unit 18 to operate the type 6 microcomputer.
As shown in Table 1, the clock CK1 ″ is selected as the write clock WCK2 of the aspect ratio conversion circuit 5 and the clock CK1H is selected as the read clock RCK2, and the write clock of the aspect ratio conversion circuit 11 is set as shown in Table 1. The clock CK1H ^* is selected as WCK1, and the selector 23 is controlled so as to select the clock CK1H ^* as the read clock RCK1 so that the aspect ratio conversion circuit 5 writes the write clock WCK2 (CK
1 ″), the luminance data VFY of the odd-numbered line becomes F
The data is written to the FIFO memories 5a and 5b, and the luminance data VFY of the even lines is written to the FIFO memories 5c and 5d. In the aspect ratio conversion circuit 11, 1144 samples of luminance data Y are stored in the FIFO memory 1 every 1H period in synchronization with the write clock RCK1 (CK1H ^* ).
1a to 11d.

Further, the microcomputer 19 outputs the write clocks WCK1 (CK1H ^* ) and WCK2 (CK1 ″) and the read clocks RCK1 (CK1H ^* ) and RCK2.
The cut-out signals C1 and C2 corresponding to (CK1H) are supplied to the aspect ratio conversion circuit 5 and the aspect ratio conversion circuit 11, respectively. In the type 6 operation mode, the main line clipping signal C1 is based on the number of samples L (1144) for the 1H period shown in Table 2 and the number of samples L (1144) defining the clipping start position, and the clipping start address = NL = 1144-1144 = 0. In addition, the VF system cutout signal C2 is based on the sample number N (1144) for the 1H period and the sample number L (899) that defines the cutout start position, based on the cutout start address = NL = 1144-899 = 245. give.

As a result, in the aspect ratio conversion circuit 5, the cut-out start address = 245 is given by the cut-out signal C2, so that the read clock R
In synchronization with CK2 (CK1H1), the FIFO memory 5
a, 5b, the luminance data VFY of the 246th and subsequent samples of the odd-numbered lines are read out.
From c and 5d, the luminance data VFY of the 246th and subsequent samples of the even line is read.

In the aspect ratio conversion circuit 11, 1
The luminance data Y of 1144 samples is FIFO
Read clock RCK1 from memories 11a to 11d
It is read out in synchronization with (CK1H ^* ).

Therefore, the aspect ratio conversion circuit 5
For each 1H period, 572 samples of luminance data VFY are cut out from 1144 samples of luminance data VFY, and 1
The number of samples of the luminance VFY for the line is reduced to １ ／. As a result, as shown in FIG. 12, the aspect ratio conversion circuit 5 cuts out the 8: 9 image from the VF 16: 9 image, and makes the cut out image 16: 9 again. That is, the aspect ratio conversion circuit 5 enlarges the image in which the number of samples of the luminance data VFY is １ ／ by two in the horizontal direction, thereby setting the aspect ratio to 16: 9. Then, the aspect ratio conversion circuit 5 supplies the image signal having the aspect ratio of 16: 9 to the viewfinder 7 via the D / A converter 6.

Further, the aspect ratio conversion circuit 11 is 1H
In each period, 1144 samples of luminance data Y to 114
By cutting out all four samples of luminance data Y, luminance data Y having an aspect ratio of 16: 9 is output,
The luminance data Y is supplied to the encoder 10 via the D / A converter 9.

Therefore, in this type 6 operation mode, the encoder 10 is supplied with the 16: 9 luminance data Y simply passed through the aspect ratio conversion circuit 11, and is cut out to the viewfinder 7 at 8: 9. A 16: 9 image signal that is enlarged twice in the horizontal direction is supplied. As a result, an image obtained by enlarging an image obtained by cutting out a part of the main line image in the width direction can be observed by the viewfinder 7, so that manual focus adjustment can be easily performed.

As described above, in the video camera to which the present invention is applied, the microcomputer 19 controls the aspect ratio conversion circuit 5,
By independently controlling the image signals 11 and 11, the aspect ratio of the image signal supplied to the main line system and the aspect ratio of the image signal supplied to the VF system can be changed in accordance with the use situation of the user.

As described above, since the microcomputer 19 can set the start position of the image data cutout according to the operation setting of the operation unit 18, not only the image is cut out from the center of the original image but also For example, it is also possible to cut out only the end image of the original image.

[0129]

According to the image pickup apparatus of the present invention, the digital image signal of the first aspect ratio generated by the image pickup means based on the subject image in the horizontal direction of the image represented by the digital image signal First converting means for cutting out and outputting at least a part of the samples;
And the second conversion means for cutting out and outputting at least a part of the sample in the horizontal direction of the image represented by the digital image signal independently of the first conversion means. The digital image signal whose aspect ratio is independently controlled can be obtained from the first and second conversion means by controlling the image signal. Thus, the aspect ratio of the image signal supplied to the main line system and the image signal signal supplied to the viewfinder system can be changed independently.

Further, in the imaging apparatus according to the present invention, by controlling the number of samples cut out by the first conversion means to be smaller than the number of samples cut out by the second conversion means, the first conversion The digital image signal of an image obtained by enlarging a part of the image represented by the digital image signal output from the means in the horizontal direction can be output from the second conversion means. As a result, it is possible to cut out a part of the image based on the image signal supplied to the main line system and supply the image signal enlarged in the horizontal direction to the viewfinder system.

In the imaging apparatus according to the present invention, the number of samples cut out by the first conversion means is controlled to be larger than the number of samples cut out by the second conversion means, so that the number of samples generated by the imaging means is increased. The converted digital image signal of the first aspect ratio is converted into a digital image signal of the second aspect ratio obtained by cutting out a part of the image represented by the digital image signal output from the second conversion means, and output. can do. Thus, an image signal including images on both sides in the horizontal direction of the image based on the image signal supplied to the main line system can be supplied to the viewfinder system.

Further, in the imaging apparatus according to the present invention, the operation of the first and second conversion means is switched between the first mode and the second mode by the control means, and the first mode is switched to the first mode in the first mode. Is controlled so that the number of samples cut out by the conversion means is larger than the number of samples cut out by the second conversion means, so that a part of the image represented by the digital image signal output from the first conversion means A digital image signal of an image obtained by enlarging the image in the horizontal direction can be output from the second conversion means, and the number of samples cut out by the second conversion means in the second mode is controlled to be smaller. Output a digital image signal of an image obtained by enlarging a part of the image represented by the digital image signal output from the first conversion means in the horizontal direction from the second conversion means. Rukoto can. Thus, the aspect ratio of the image signal supplied to the main line system and the image signal signal supplied to the viewfinder system are independently changed, and in the first mode, a part of the image based on the image signal supplied to the main line system is cut out. An image signal enlarged in the horizontal direction can be supplied to the viewfinder system. In the second mode, an image signal including both horizontal images of the image signal supplied to the main line system is supplied to the viewfinder system. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a video camera to which the present invention is applied.

FIG. 2 is a diagram illustrating cutout and group delay of image data in an aspect ratio conversion circuit of the video camera.

FIG. 3 is a diagram schematically showing a situation in which image data is written to each FIFO memory when aspect ratio conversion is performed in the aspect ratio conversion circuit.

FIG. 4 is an explanatory diagram of an output portion of each FIFO memory.

FIG. 5 is a diagram showing a FIFO control pattern when performing an aspect ratio conversion in an aspect ratio conversion circuit of the video camera.

FIG. 6 is a diagram for explaining extraction of image data and group delay when aspect ratio conversion is not performed in the aspect ratio conversion circuit.

FIG. 7 is a diagram schematically showing a situation in which image data is written to each FIFO memory when aspect ratio conversion is not performed in the aspect ratio conversion circuit.

FIG. 8 is a diagram showing a FIFO control pattern when the aspect ratio conversion is not performed in the aspect ratio conversion circuit of the video camera.

FIG. 9 is a block diagram illustrating a configuration of an aspect ratio conversion circuit according to another embodiment.

FIG. 10 is a timing chart illustrating a switching signal _IDo .

FIG. 11 is a block diagram showing a configuration of an aspect ratio conversion circuit according to another embodiment.

FIG. 12 is a diagram schematically showing a relationship between a captured image and an output image in various operation modes of the video camera.

[Explanation of symbols]

1R, 1G, 1B CCD image sensor, 3R, 3
G, 3B A / D conversion circuit, 5, 11, 12, 13 aspect ratio conversion circuit, 7 view finder, 15 sync generator, 16 timing generator, 1
8 operation unit, 19 microcomputers, 23 selectors, 20, 2
4 clock generation circuit, 21, 22, 25, 26 1 /
Divide-by-2 circuit, 27, 28 Phase correction circuit

Claims (6)

[Claims] An image pickup means for generating a digital image signal having a first aspect ratio based on a subject image, a predetermined group delay is given to the digital image signal generated by the image pickup means, and the digital image signal is given by the digital image signal. A first conversion unit that cuts out and outputs at least a part of samples in a horizontal direction of an image to be represented, and that the digital image signal generated by the imaging unit is given the same group delay as the first conversion unit, and A second conversion unit that cuts out and outputs at least a part of a sample of an image represented by a digital image signal in a horizontal direction independently of the first conversion unit, and that is connected to the second conversion unit; Display means for displaying an image based on the digital image signal output from the second conversion means; and the first and second modes including at least a first mode. Operating means for setting an operation mode of the second converting means; and when the first mode is set by the operating means, the number of samples to be cut out by the first converting means is equal to the number of samples of the second converting means. An imaging device comprising: a control unit that controls the first and second conversion units so that the number of samples to be cut out is smaller than the number of samples to be cut out. 2. The image pickup means generates a digital image signal having a first aspect ratio, and the control means controls the first image signal in the first mode.
By converting only a part of the sample of the digital image signal into a digital image signal having the first aspect ratio and outputting the digital image signal having the second aspect ratio. In the conversion means of 2,
2. The imaging apparatus according to claim 1, wherein the digital image signal having the first aspect ratio is output at the same aspect ratio by cutting out all of the digital image signals. 3. The image pickup means generates a digital image signal having a first aspect ratio, and the control means, when set to a second mode different from the first mode by the operation means, By causing the first conversion means to cut out only a part of the sample of the digital image signal, the digital image signal having the first aspect ratio is converted into a digital image signal having a second aspect ratio. (2) converting the digital image signal having the first aspect ratio into a digital image signal having a second aspect ratio by causing the conversion means of (2) to cut out only a sample equal to the partial sample of the digital image signal. The imaging device according to claim 1, wherein: 4. An image pickup means for generating a digital image signal having a first aspect ratio based on a subject image, a predetermined group delay is given to the digital image signal generated by the image pickup means, and the digital image signal is given by the digital image signal. A first conversion unit that cuts out and outputs at least a part of samples in a horizontal direction of an image to be represented, and that the digital image signal generated by the imaging unit is given the same group delay as the first conversion unit, and A second conversion unit that cuts out and outputs at least a part of a sample of an image represented by a digital image signal in a horizontal direction independently of the first conversion unit, and that is connected to the second conversion unit; Display means for displaying an image based on the digital image signal output from the second conversion means; and the first and second modes including at least a third mode. Operating means for setting an operation mode of the second converting means; and when the third mode is set by the operating means, the number of samples to be cut out by the first converting means is changed by the second converting means. An imaging apparatus comprising: a control unit that controls the first and second conversion units so that the number of samples to be cut out is larger than the number of samples to be cut out. 5. The image capturing means generates a digital image signal having a first aspect ratio, and the control means controls the first image signal in the third mode.
Causes the conversion means to cut out all of the digital image signal, thereby outputting the digital image signal of the first aspect ratio at the same aspect ratio,
Is characterized in that the converting means cuts out only a part of the sample of the digital image signal, thereby converting the digital image signal of the first aspect ratio into a digital image signal of the second aspect ratio and outputting the same. Claim 4
An imaging device according to any one of the preceding claims. 6. An image pickup means for generating a digital image signal having a first aspect ratio based on a subject image, a predetermined group delay is given to the digital image signal generated by the image pickup means, and the digital image signal is given by the digital image signal. A first conversion unit that cuts out and outputs at least a part of samples in a horizontal direction of an image to be represented, and that the digital image signal generated by the imaging unit is given the same group delay as the first conversion unit, and A second conversion unit that cuts out and outputs at least a part of a sample of an image represented by a digital image signal in a horizontal direction independently of the first conversion unit, and that is connected to the second conversion unit; Display means for displaying an image based on the digital image signal output from the second conversion means, and operation modes of the first and second conversion means And operating means for setting, based on the setting of the operating means, at least, the first
So that the number of samples cut out by the conversion means is smaller than the number of samples cut out by the second conversion means.
And a first mode for controlling the second conversion means, and the first and second modes so that the number of samples cut out by the first conversion means is larger than the number of samples cut out by the second conversion means. An imaging device comprising: a control unit configured to switch to a second mode for controlling the conversion unit.