JPH103284A - Liquid crystal driving circuit and liquid crystal display device having the circuit - Google Patents

Abstract

(57) Abstract: A liquid crystal display device having an active matrix type liquid crystal panel and capable of displaying both an interlaced signal and a non-interlaced signal as a video signal has a reduced cost, reduced power consumption, and reduced size. Aim. An input terminal (1) is provided using a line memory unit (3).
The interlace signal input from a is doubled and pseudo-converted to a non-interlace signal, and the signal switching circuit selects and switches between the non-interlace signals input from the input terminals 1b-1 to 1b-4. , And the circuits after the gamma circuit 14 are shared.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device provided with an active matrix type liquid crystal panel and a memory means for converting an interlaced signal into a line-sequential scanning signal, and in particular, means for inputting a non-interlaced signal from a computer. The present invention relates to a liquid crystal display device provided with.

[0002]

2. Description of the Related Art Video signals transmitted to display an image or video on a display device include interlaced signals such as NTSC and PAL and non-interlaced signals such as VGA and SVGA.

FIG. 2 is a schematic view of a scanning line of an interlace signal. In the figure, O _n denotes the n-th row of the odd-numbered rows, E
_n indicates the n-th row of the even-numbered rows. In interlaced scanning, after odd-numbered rows are skipped in odd-numbered fields, even-numbered rows are scanned in even-numbered fields so as to fill the gaps, and are scanned at 30 Hz (NTSC) or 25H.
One image (one frame) is completed by z (PAL). Therefore, one horizontal scanning period is 63.5 μs (NTS
C) or 64 μs (PAL).

FIG. 3 is a schematic view of a scanning line of a non-interlace signal. In the figure, _Fn indicates the n-th row. In the non-interlaced scanning, all lines in each field are sequentially scanned from top to bottom to complete one image. The frame frequency is about 50-60Hz, 1
The horizontal scanning period is about 30 μs, which is half of the interlace signal.

Conventionally, as a liquid crystal display device capable of displaying both an interlaced signal and a non-interlaced signal on the same liquid crystal panel, there has been a liquid crystal display device using a frame memory. FIG. 4 shows a block diagram thereof. In the figure, 1a
Is a first video signal input terminal, and inputs an NTSC TV signal which is an interlace signal here. Reference numeral 2 denotes a signal processing unit for the first video signal, here a decoder unit for converting a composite signal into an RGB color signal. 1
Reference numerals b-1 to 1b-3 denote second video signal input terminals, which are input terminals (R, G, B) of VGA signals which are non-interlace signals. Reference numeral 41 denotes an A / D conversion unit, reference numeral 42 denotes a frame memory unit, and reference numeral 43 denotes a D / A conversion unit. Reference numeral 11 denotes a phase adjustment unit for the second video signal, which includes an analog delay and a sample-and-hold circuit. 12
Is a color switching circuit for switching the color sent to the signal line according to the color arrangement of the liquid crystal pixels. A signal switching circuit 13 selects and switches between the first video signal and the second video signal. Reference numeral 4 denotes a forward / reverse switching amplifier which sequentially switches the signal between forward / reverse at predetermined time intervals and serves as a signal for driving the liquid crystal. It is. Reference numeral 6 denotes an active matrix type liquid crystal panel, of which 7 is a horizontal shift register (HSR) as a horizontal scanning means,
Reference numeral 8 denotes a vertical shift register (VSR) as a vertical scanning unit, and reference numeral 9 denotes a pixel unit.

In the configuration shown in FIG. 4, when an interlace signal is input, the signal input to the input terminal 1a is color-decoded by the decoding unit 2, and then the frame memory unit 42
Is converted to a line-sequential scanning signal, and the liquid crystal panel 6 is rewritten every field. When a non-interlace signal is input, the signals input to the input terminals 1 b-1 to 1 b to 3 are transmitted to the phase adjustment unit 11 and the color switching circuit 12.
After that, the liquid crystal panel 6 is rewritten for each field while keeping the line sequential scanning signal.

In the above configuration, the interlaced signal is temporarily stored in the frame memory section 42, the interlaced scanning signals of the even field and the odd field are alternately read out and converted into the line sequential scanning signal, and then the same signal processing as the non-interlaced signal is performed. Drives the liquid crystal through the system. On the other hand, the non-interlaced signal drives the liquid crystal through a signal processing system without passing through the frame memory unit 42.

[0008]

However, in the above-mentioned conventional liquid crystal display device, the frame memory itself is expensive, and the A / D converters 41 and D for handling digitized video signals are used. Due to the large scale of the system such as the / A conversion unit 43, there are problems that the cost is high, the power consumption is high, and it is difficult to reduce the size. These issues are particularly relevant for HMDs (Head Mounted Display)
This poses a problem when it is mounted on ultra-compact, battery-powered application products.

An object of the present invention is to solve the above-mentioned problems and to provide a small-sized and low-power-consumption liquid crystal display device capable of displaying both interlaced signals and non-interlaced signals.

[0010]

According to the present invention, an interlaced signal is doubled in speed using a low-cost, small-sized and simple-structured line memory, and is pseudo-converted into a non-interlaced signal. A low-cost, low-power, small-sized liquid crystal display device is realized by providing means for switching between non-interlaced signals and sharing the latter part of the output signal, which is AC-inverted and used as a signal for driving the liquid crystal. It is.

That is, according to the first to third aspects of the present invention, the first video signal input means for inputting the first video signal and the first video signal input to the first video signal input means are doubled in speed. A second video signal input means for inputting a second video signal, a first video signal doubled in the line memory means, and a second video signal from the second video signal input means. A liquid crystal driving circuit comprising: a signal switching unit for selecting and switching any one of the video signals; and an inverting unit for inverting an output signal from the signal switching unit with an AC signal. , A liquid crystal display device comprising the liquid crystal driving circuit and an active matrix type liquid crystal panel.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] FIG. 1 is a block diagram of a liquid crystal display device according to Embodiment 1 of the present invention, which uses an analog line memory to support both interlaced signals and non-interlaced signals. In the present embodiment, a case is shown in which an NTSC signal of an interlace signal is displayed as a first video signal, and a VGA signal is displayed as a non-interlace signal as a second video signal.

In FIG. 1, reference numeral 1a denotes a first video signal input terminal which is first video signal input means, and 1b-1 to 1b-4 denote VGAs.
A second video signal input terminal 3 serving as second video signal input means for inputting the R, G, B and synchronization signals of the signal doubles the speed of the NTSC signal input to the first video signal input terminal, and generates a pseudo signal. It is an analog run memory unit which is a line memory means for converting the signal into a non-interlace signal. Reference numeral 11 denotes a phase adjustment unit, which is a phase adjustment circuit for a second video signal, and is configured by, for example, an analog delay element such as a delay line or a sample-and-hold circuit. The phase of the signal is matched to the typical arrangement.

Reference numeral 12 denotes a color switching circuit for switching colors in accordance with the color arrangement of the pixels connected to the vertical signal lines of the liquid crystal panel 6. Reference numeral 13 selects one of the double-speed first video signal (interlace signal) output from the analog line memory unit 3 and the second video signal (non-interlace signal) output from the phase adjustment unit 11. , A signal switching circuit which is a signal switching means for switching. Reference numeral 14 denotes a gamma circuit for converting a video signal having a gamma characteristic suitable for a CRT into a gamma characteristic adapted to a voltage-transmittance characteristic of a liquid crystal. Reference numeral 4 denotes a forward / reverse switching amplifier which is an inversion means for converting a video signal into an AC inversion signal for liquid crystal display.

An active matrix type liquid crystal panel 6 has a horizontal shift register (HSR) 7 as a horizontal scanning means, a vertical shift register (VSR) as a vertical scanning means, and a pixel section 9. I have.

Reference numeral 15 denotes a PLL unit for receiving a synchronization signal of the first and second video signals and synchronously controlling a logic unit. Reference numeral 5 denotes a control unit which forms a control pulse synchronized in the PLL unit and an analog line memory unit. 3, a logic unit that drives the phase adjustment unit 11, the forward / reverse switching amplifier 4, and the liquid crystal panel 6.

FIG. 5 is a block diagram of the analog line memory unit 3 according to the present embodiment. In the figure, 45 is an input stage of a memory stage, 46 is a write shift register (WSR) as a memory writing means, 47 is a start pulse (WST) input terminal for WSR, and 48-1 and 48-2 are WSR input terminals. Two-phase transfer clocks (WCLK1, WCLK
2) An input terminal, 49 is a memory read shift register (RSR), 50 is an RSR start pulse (RSR).
T) input terminal, 51 is a transfer clock (RCL) for RSR
K) An input terminal 52 is a switching control unit for switching a signal to be sent to a signal line of the liquid crystal panel according to the color arrangement of the liquid crystal panel.

Reference numeral 58 denotes a sample-and-hold circuit;
Is an input terminal of the sample hold circuit 58.

Reference numeral 53 denotes an output stage of the memory.
4G and 54B are input terminals for RGB signals, respectively.
55A, 55B, and 55C are R and G, G and B, B, respectively.
And R are switched between even and odd rows of the liquid crystal screen.
Is an output terminal for switching and outputting with the switch of
Is an input terminal of the switching control unit 52.

Reference numerals 57a to 57f denote memory columns of two RGB colors each, and a specific configuration example of this portion is shown in FIG. Here, reference numerals 60A to 60C denote output lines of the memory between the switching control unit 25 and the sample and hold circuit 58 in FIG. Also, 1 to n of 57a to 57f respectively represent the first to nth bits of the memory column. When a signal is read, 57a, 57a,
Select 57c, 57e or 57b, 57d, 57f.

FIG. 7 shows the timing of driving the liquid crystal and the memory during the horizontal scanning period when displaying an interlace signal in the liquid crystal display device of the present embodiment. In the figure, SG1R is a red video signal, SG1G is a green video signal, SG1B is a blue video signal, SG2 is WST, S
G3 is WCLK1, SG4 is WCLK2, SG5 is RS
T, SG6 is RCLK, SG7 is a color selection switching signal,
SG8A to SG8C are signals converted into line-sequential scanning signals output from the memory unit, SG9 is a start pulse (HST) of a horizontal shift register (HSR), and SG10 and SG11 are HSR two-phase clock pulses (H
1, H2).

The signals of each color input to the analog line memory unit are stored in two memories for the even and odd rows of the liquid crystal panel. At this time, since the horizontal positions of pixels of the same color in the even-numbered rows and the odd-numbered rows are normally shifted by a half cycle (1.5 pixels), the sampling timing of the memory is also shifted by a half cycle (1.5 pixels). Write. In this way, the signals sampled at double density are taken out every other time by the color switching signal SG7 at the time of reading,
Scanning is successively performed twice in one horizontal scanning period by a read shift register (RSR), so that two serial signals of even-numbered rows and odd-numbered rows are rearranged in order to match the pixel arrangement of the liquid crystal screen. It is. In this manner, the speed of the interlace signal having information for one row is doubled in one horizontal scanning period to generate information for two rows in a simulated manner, and conversion to a line sequential scanning signal is performed.

When the interlace signal is displayed in Table 1, each row (2n to 2n +
2) shows a signal to be written. Where O _n (m) and O _n '(m) were sampled at different timings in accordance with the n-th signal panels even rows and odd rows of the pixel array of the odd rows of the m th frame of the interlaced signal data It is.

[0024]

[Table 1]

Since both the even and odd rows of the screen are rewritten every field (60 Hz), there is no flicker problem. In addition, the vertical resolution becomes half of the original signal when viewed in one field, but the vertical resolution is increased in a pseudo manner by shifting the display by one line in the next one field.

Next, a case where a non-interlaced signal is displayed will be described. FIG. 8 shows the drive timing of the liquid crystal panel during the horizontal scanning period at this time. In the figure, SG1
R is a red video signal, SG1G is a green video signal, SG
1B is a blue video signal, SG7 is a color selection switching signal,
SG8A to SG8C are signals output from the color switching circuit, SG9 is HST, SG10 is H1, SG11 is H2
It is.

Originally, a non-interlaced signal having a horizontal scanning frequency twice that of an interlaced signal is subjected to color and phase adjustment in accordance with the pixel arrangement of the liquid crystal panel, and then processed using the same signal processing system as the signal output from the memory. It is converted into a driving signal waveform.

When a non-interlaced signal is displayed in Table 2, each row (n to n +
4) shows a signal written to 4). Here, F _n (m) and F _n ′ (m) are data obtained by sampling the n-th signal of the non-interlace signal in the m-th field at different timings according to the pixel arrangement of the even-numbered row and the odd-numbered row of the panel. . For non-interlaced signals,
The screen can be rewritten for each field without lowering the vertical resolution.

[0029]

[Table 2]

In the present invention, the signal processing system for driving the liquid crystal after the gamma circuit can be shared for signals of different vertical scanning methods such as an interlaced signal and a non-interlaced signal. ,
Cost reduction is realized.

Further, by using the analog line memory, low power consumption is achieved and noise is reduced.

[Second Embodiment] As a second embodiment of the present invention, a block diagram of a liquid crystal display device using a digital line memory is shown in FIG.

This embodiment also shows a case where an NTSC signal of an interlace signal is displayed as a first video signal, and a VGA signal is displayed as a non-interlace signal as a second video signal.

In the figure, the same members as those in FIG. The present embodiment has a digital line memory section 91 as a line memory. Therefore, a digital gamma circuit 92 is provided for the gamma circuit 14 of the embodiment, and a video signal is digitally added / subtracted for the forward / reverse switching amplifier 4. Digital forward / reverse switching
An inversion switching amplifier 93 is used, and an A / D converter 41 and a D / A converter 43 are used.

In the present embodiment, A
Although the circuit becomes large by the addition of the / D conversion unit and the D / A conversion unit, the liquid crystal driving signal processing system after the gamma circuit is shared as in the first embodiment. Thus, the size and cost can be reduced. Further, by performing the processing digitally, the signal adjustment can be simplified, and the signal processing can be performed with high accuracy in terms of signal accuracy.

[0036]

As described in detail above, according to the present invention,
The use of inexpensive, compact, and simple line memory allows the circuit to be reduced in scale, reducing power consumption and cost and miniaturizing it. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of a scanning line of an interlace signal.

FIG. 3 is a schematic diagram of a scanning line of a non-interlace signal.

FIG. 4 is a block diagram of a conventional liquid crystal display device.

FIG. 5 is a block diagram of an analog line memory unit of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a specific configuration example of a memory column of an analog line memory unit of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 7 is a timing chart for driving a liquid crystal and a memory when an interlace signal is displayed on the liquid crystal display device according to the first embodiment of the present invention.

FIG. 8 is a timing chart for driving a liquid crystal and a memory when a non-interlaced signal is displayed on the liquid crystal display device according to the first embodiment of the present invention.

FIG. 9 is a block diagram of a liquid crystal display device according to a second embodiment of the present invention.

[Explanation of symbols]

1a First video signal input terminal 1b-1 to 1b-4 Second video signal input terminal 2 Decoder unit 3 Analog line memory unit 4 Forward / inverting control amplifier 5 Logic unit 6 Liquid crystal panel 7 Horizontal shift register (HSR) Reference Signs List 8 vertical shift register (VSR) 9 pixel unit 11 phase adjustment unit 12 color switching circuit 13 signal switching circuit 14 gamma circuit 15 PLL unit 41 A / D conversion unit 42 frame memory unit 43 D / A conversion unit 45 input stage of memory unit 46 Write shift register (WSR) 47 Start pulse (WST) input terminal for WSR 48-1, 48-2 Two-phase clock pulse (WSR) of WSR
CLK1, WCLK2) input terminal 49 Memory read shift register (RSR) 50 Start pulse (RST) input terminal for RSR 51 Transfer clock (RCLK) input terminal for RSR 52 Switching control unit 53 Memory output stage 54R, 54G, 54B RGB signal input terminal 55A, 55B, 55C output terminal 56 switching control signal input terminal 57a-57f memory column 58 sample hold circuit 59 sample hold pulse input terminal 60A-60C memory output line 91 digital line memory section 92 digital gamma circuit 93 digital positive Inversion control amplifier

Claims (4)

[Claims] A first video signal input means for inputting a first video signal; a line memory means for doubling a speed of the first video signal input to the first video signal input means; A second video signal input means for inputting the first video signal, and selecting one of the first video signal doubled in the line memory means and the second video signal from the second video signal input means. A liquid crystal driving circuit, comprising: a signal switching unit for performing a switching operation; and an inversion unit for performing an AC inversion of an output signal from the signal switching unit. 2. The liquid crystal driving circuit according to claim 1, further comprising a gamma circuit for performing gamma conversion on an output signal from said signal switching means. 3. A stage subsequent to the second video signal input means,
3. The image processing apparatus according to claim 1, further comprising a second image signal phase adjustment circuit.
A liquid crystal driving circuit as described in the above. 4. A liquid crystal display device comprising: the liquid crystal driving circuit according to claim 1; and an active matrix type liquid crystal panel.