JPH10340221A - Flash memory device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a flash memory device which can perform writing without using dedicated software and can be handled in the same manner as a normal memory. An address register holding an address of an address bus, a data register holding data of a data bus, and a flash memory for selecting an address of the address bus and an address output by a memory control means. An address selector 50, a flash memory 51 which receives an address output from the flash memory address selector 50 as an address input, a flash memory data buffer 52 which connects the flash memory 51 and the data bus 2, and performs writing / erasing of the flash memory 51. A data memory 44 having the same storage capacity as that of a block, which is a unit of operation, is provided, and these are controlled by the memory control means 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory device such as a personal computer and a portable information terminal.

[0002]

2. Description of the Related Art Conventionally, one method as a main storage device of a personal computer or a portable information terminal uses a dynamic RAM or a static RAM. Was. Another method is to use a nonvolatile memory such as a flash RAM.

[0003]

In the first method of the above-mentioned conventional method, power must be continuously supplied to the memory, so that the battery must be charged or replaced before the battery runs out. . However, since the battery is consumed even when the device is not used, there is a danger that the battery is exhausted during the unused period and the data is destroyed. In addition, since power must be supplied to the memory even when the battery is replaced, a mechanism such as incorporating a small battery is required.

In the second method, since it is not necessary to supply power to the memory while the power is turned off, the danger of the first method is eliminated, but there are some limitations due to the capability of the flash memory. . The flash memory has a read speed comparable to that of a normal memory, but requires a long time to write and requires a write operation in a special mode. In order to avoid this limitation, dedicated software such as a basic software (OS) for managing the flash memory is required. In addition, there is a problem that the performance is deteriorated with respect to a general memory because the writing time to the flash memory is long.

[0005] The present invention solves the above-mentioned problems in using the flash memory as a main storage device of a personal computer, a portable information terminal, or the like, and can perform writing without requiring special software. It is intended to provide a device. In addition, it is an object of the present invention to provide a flash memory device which can reduce performance degradation due to writing time.

[0006]

According to a first aspect of the present invention, there is provided a flash memory device which performs writing / erasing in units of a block composed of a plurality of memory cells, wherein the entire memory is controlled. Control means;
An address register for holding the address of the address bus, a data register for holding the data of the data bus,
A flash memory address selector for selecting an address of an address bus and an address output by the memory control means, a flash memory for inputting an address output from the flash memory address selector as an address input, and a flash memory for connecting the flash memory and the data bus A data buffer and a data memory having the same storage capacity as a block which is a unit for performing writing / erasing of the flash memory are provided, and the memory control means at the time of data reading uses an address of an address bus through a flash memory address selector. To the flash memory, read the address data of the address bus from the flash memory, and send the data read from the flash memory to the data bus through the flash memory data buffer. Was issued, the memory control means, at the time of data writing, to hold the data of the data bus in the data register with and holds the address of the address bus to the address register, writes in the flash memory from the address is held in the address register
The block number of the block to be erased is obtained, and the address contained in the block of this block number is supplied to the flash memory through the flash memory address selector, so that the address register holds all the addresses of the block indicated by the block number. The data at each address other than the address is read from the flash memory, and the data read from the flash memory is written to a position corresponding to each address other than the address held in the address register among all addresses of the block in the data memory. Then, the data held in the data register is written to a position corresponding to the address held in the address register in the data memory, and the data of the block of the block number in the flash memory is erased, and the flash memory is erased. Characterized in that so as to write the data in the data memory to a block having the block number in the directory.

According to this configuration, since writing to the flash memory is controlled by the memory control means, a complicated memory writing operation to the flash memory can be easily performed without requiring dedicated software, It can be handled in the same way as a normal memory. 3. A flash memory device according to claim 2, wherein the flash memory device performs writing / erasing in units of a block composed of a plurality of memory cells, and comprises a memory control means for controlling the whole and a first address bus. An address register for holding a first partial address corresponding to a block number of a block to be written / erased out of an address consisting of a partial address and a second partial address; and a first partial address and an address bus held by the address register. A comparator for comparing a first partial address among the addresses, a flash memory address selector for selecting an address on the address bus and an address output by the memory control means, and an address input for outputting an address output from the flash memory address selector. Flash memory and flash A flash memory data buffer for connecting the memory and the data bus, a data memory address selector for selecting a second partial address among the addresses on the address bus and an address for control output by the memory control means, writing·
A data memory having the same storage capacity as a block as a unit to be erased, and having an address output from a data memory address selector as an address input and a data flag being set corresponding to an address where data is written; A data memory data buffer for connecting the data memory and the data bus, wherein the memory control means causes the comparator to compare the address of the address bus with the address held in the address register when reading data, When an output occurs, the address of the address bus is supplied to the flash memory through the flash memory address selector, and the data of the address of the address bus is read from the flash memory.
The data read from the flash memory is sent out to the data bus through the flash memory data buffer, and when a match is generated from the comparator, the second partial address of the address bus address is transferred to the data memory through the data memory address selector. When the data flag corresponding to the second partial address of the address of the address bus is set in the data memory, the data of the second partial address of the address of the address bus is read from the data memory. The data read from the memory is sent to the data bus through the data memory data buffer. When the data flag corresponding to the second partial address of the address of the address bus is not set in the data memory, the flash memory address The address of the address bus is supplied to the flash memory through the selector, to read the data of the address of the address bus from the flash memory,
The data read from the flash memory is sent to the data bus through the flash memory data buffer, and at the time of data writing, when no data has been written after power-on, the memory control means Is written to an address register, and a second partial address of the address of the address bus is applied to the data memory through a data memory address selector, so that the data on the data bus is passed through a data memory data buffer to the address bus of the data memory. And a data flag corresponding to the second partial address of the address of the address bus is set, and the memory control means sets the data flag when writing the data. When data has been written at least once after power-on, the first partial address held by the address register is compared with the first partial address of the address bus by a comparator. , The second of the addresses on the address bus
By providing the partial address to the data memory through the data memory address selector, the data on the data bus is stored in the address corresponding to the second partial address among the addresses on the address bus of the data memory through the data memory data buffer, and When the data flag corresponding to the second partial address of the address is set, and a non-match output is generated from the comparator,
Each address included in the block corresponding to the first partial address held by the address register is sequentially and commonly applied to the data memory and the flash memory through the data memory address selector and the flash memory address selector, respectively. Of the addresses included in the block corresponding to the first partial address among the addresses of the address bus, only the address for which the data flag is not set in the data memory among the addresses included in the block is copied to the data memory, and the address of the address bus in the flash memory Of the block corresponding to the first partial address of the flash memory, and writes the data of the data memory to the block corresponding to the first partial address of the address of the address bus in the flash memory. To cancel the setting of the data flag of the data memory, write the first partial address of the address of the address bus to the address register, and store the second partial address of the address of the address bus through the data memory address selector. To store the data on the data bus through the data memory data buffer at the position corresponding to the second partial address of the address of the address bus of the data memory, and the second portion of the address of the address bus of the data memory. A data flag corresponding to an address is set.

According to this configuration, since writing to the flash memory is controlled by the memory control means, a complicated memory writing operation to the flash memory can be easily performed without requiring dedicated software. It can be handled in the same way as a normal memory. In addition, continuous writing to the same block is completed by one writing, and the writing time can be reduced.

[0009] A flash memory device according to claim 3 is
A flash memory device that performs writing / erasing in units of a block composed of a plurality of memory cells,
Memory control means for controlling the whole; and a second partial address corresponding to a block number of a block to be written / erased among addresses composed of a first partial address, a second partial address and a third partial address of an address bus. And an address tag memory address selector for selecting an address output from the memory control means, an address output from the address tag memory address selector being an address input, and an address tag flag being set corresponding to an address where data is written. An address tag memory, an address tag memory data buffer for connecting the address tag memory to the address bus and supplying a first partial address of the address bus as a data input to the address tag memory, and a second address bus address of the address bus. Address partial address A comparator for comparing the address read from the address tag memory with the first partial address among the addresses on the address bus; a flash memory address selector for selecting an address on the address bus and an address output by the memory control means; A flash memory having an address input from an address output from a flash memory address selector, a flash memory data buffer connecting the flash memory and a data bus, and a second partial address and a third partial address of addresses on the address bus. And a data memory address selector for selecting an address for control output by the memory control means, and a number corresponding to the size of the address space of the second partial address of the block which is a unit of writing / erasing of the flash memory. the same A data memory having an amount, an address output from a data memory address selector being an address input, and a data flag being set corresponding to an address to which data is written, and a data memory data buffer connecting the data memory and the data bus The memory control means receives the first partial address of the addresses of the address bus and the second partial address of the addresses of the address bus through the address tag memory address selector and inputs the address to the address tag memory when reading data. A comparator compares the data read from the flash memory with the data read out from the flash memory. When a non-match output is generated from the comparator, the address on the address bus is supplied to the flash memory through the flash memory address selector. The data read from the flash memory is sent out to the data bus through the flash memory data buffer, and when a match output is generated from the comparator, the data of the address on the address bus is passed through the data memory address selector. Two part address and third
The partial address is supplied to the data memory, and when the data flags corresponding to the second partial address and the third partial address of the addresses on the address bus are set in the data memory, the data memory transfers the partial address from the address on the address bus. The data of the two-part address and the third partial address are read, and the data read from the data memory is sent to the data bus through the data memory data buffer.
When the data flag corresponding to the partial address and the third partial address is not set in the data memory, the address of the address bus is supplied to the flash memory through the flash memory address selector, and the data of the address of the address bus is read from the flash memory. The data read from the flash memory is sent out to the data bus through the flash memory data buffer, and the memory control means
Before the writing to all the addresses of the address tag memory is completed, the second partial address of the addresses on the address bus is used as an address input through the address tag memory address selector, and the first of the addresses on the address bus is input. Using the partial address as the data input, the address tag memory is written, and the address tag flag corresponding to the address where the data was written in the address tag memory is set. By providing the partial address to the data memory through the data memory address selector, the data on the data bus corresponds to the second partial address and the third partial address among the addresses on the address bus of the data memory through the data memory data buffer. It was together is stored in the position, the second of the address of the address bus in the data memory
The data flags corresponding to the partial address and the third partial address are set, and at the time of data writing, the memory control means completes writing to all addresses of the address tag memory and completes the address corresponding to all addresses of the address tag memory. After all the tag flags have been set, the comparator reads the first partial address of the address bus address and the second partial address of the address bus address from the address tag memory as an address input. When a match output is generated from the comparator, the second partial address and the third partial address of the addresses on the address bus are supplied to the data memory through the data memory address selector, thereby transferring the data on the data bus to the data memory data. Data through buffer Together is stored in the second partial address, and a third partial address in the address bus the address of the memory to the corresponding position, the second partial address in the address bus the address of the data memory and the third
When a data flag corresponding to the partial address is set and a non-match output is generated from the comparator, a plurality of sets of the first partial address and the second partial address determined by all the addresses of the address tag memory and the data stored at those addresses, respectively. The addresses included in the blocks corresponding to the two partial addresses are sequentially and commonly applied to the data memory and the flash memory through the data memory address selector and the flash memory address selector, respectively, so that the address of the address bus in the flash memory is provided. Of the addresses included in the blocks corresponding to the plurality of sets of the first partial address and the second partial address, only the addresses for which the data flag is not set in the data memory are copied to the data memory. It is not to erase the data of all the addresses and blocks corresponding to a plurality of sets of first partial address and a second partial address determined respectively by the data stored in those addresses of the address tag memory,
Causing the data of the data memory to be written to blocks corresponding to a plurality of sets of the first partial address and the second partial address among the addresses of the address bus in the flash memory, canceling the setting of the data flag of the data memory,
Until writing to all the addresses of the address tag memory is completed, the second partial address of the address bus is used as an address input through the address tag memory address selector, and the first partial address of the address bus address is input. Is written as data input to the address tag memory, and the address tag flag corresponding to the address at which the data was written in the address tag memory is set, and the second partial address and the third partial address of the addresses on the address bus are set. To the data memory through the data memory address selector, the data on the data bus corresponds to the second partial address and the third partial address of the addresses on the address bus of the data memory through the data memory data buffer. Together is stored in the position, characterized in that so as to set the data flag corresponding to the second partial address, and a third partial address of the address of the address bus in the data memory.

According to this configuration, since writing to the flash memory is controlled by the memory control means, a complicated memory writing operation to the flash memory can be easily performed without requiring special software. It can be handled in the same way as a normal memory. In addition, continuous writing to a plurality of blocks is completed by one writing, and the writing time can be further reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a flash memory device according to the present invention will be described below in detail with reference to the drawings. (First Embodiment; Corresponding to Claim 1) FIG. 1 is a block diagram showing a configuration of a flash memory device according to a first embodiment of the present invention. In FIG. 1, 1 is an address bus, 2 is a data bus, 3 is a control signal input, 4 is a control signal output, 10 is a memory control means, 20 is an address register, 40 is a data register, 44 is a data memory, and 50 is a data memory.
Is a flash memory address selector, 51 is a flash memory, and 52 is a flash memory data buffer.

In this flash memory device, writing / writing is performed in units of blocks composed of a plurality of memory cells.
This is for erasing. Among them, the memory control means 10
Performs overall control. The address register 20 holds the address of the address bus 1. The data register 40 holds data on the data bus 2. The flash memory address selector 50 selects an address on the address bus 1 and an address output from the memory control means 10. The flash memory 51 is a flash memory address selector 5
An address output by 0 is an address input. The flash memory data buffer 52 connects the flash memory 51 and the data bus 2. The data memory 44 has the same storage capacity as a block which is a unit for performing writing / erasing of the flash memory 51.

At the time of data reading, the memory control means 10 supplies the address of the address bus 1 to the flash memory 51 through the flash memory address selector 50, and reads the data of the address of the address bus 1 from the flash memory 51. Then, the data read from the flash memory 51 is sent to the data bus 2 through the flash memory data buffer 52. The memory control means 10 causes the address register 20 to hold the address of the address bus 1 and the data register 40 to hold the data of the data bus 2 at the time of writing data. Obtain the block number of the block to be written / erased at 51,
By supplying the address contained in the block of the block number to the flash memory 51 through the flash memory address selector 50, the data of each address other than the address held in the address register 20 among all the addresses of the block indicated by the block number is obtained. The flash memory 51 is read from the flash memory 51.
Out of all the addresses of the block in the data memory 44, corresponding to each address other than the address held in the address register 20, and write the data held in the data register 40 to the address in the data memory 44. The data in the block with the block number in the flash memory 51 is erased, and the data in the data memory 44 is written into the block with the block number in the flash memory 51, by writing the data in the position corresponding to the address held in the register 20. ing.

Hereinafter, the operation of this embodiment will be described with reference to FIG. 1 separately for reading, writing, reading or writing during writing. In the drawing, broken lines indicate signals for control. First, reading will be described. At the time of reading, the address signal of the address bus 1 is set to the flash memory address selector 50.
And is added to the flash memory 51. The flash memory 51 outputs the data at the added address, and outputs the data to the data bus 2 through the flash memory data buffer 52. The memory control means 10 controls the selection direction of the flash memory address selector 50 and the flash memory data buffer 52. In this case, simple memory reading is performed.

Next, writing will be described. Writing can be broken down into four stages. The first step is to hold the write address and data requested by the address register 20 and the data register 40. The memory control means 10 controls the address register 20 and the data register 40, and controls the address bus 1 and the data bus 2 respectively.
To keep the contents of The operation to the outside as a memory device can now be completed. Therefore,
From the viewpoint of using a memory device such as a microcomputer, the memory device appears as a simple memory.

The second stage is a stage in which the data of the block to be rewritten in the flash memory 51 is transferred to the data memory 44. The memory control means 10 controls the flash memory address selector 50,
Let the output signal pass. Memory control means 10
Obtains the number of the block to be rewritten from the address held by the address register 20. The memory control means 10
The sequential address is given to the flash memory 51 through the flash memory address selector, so that the data of the flash memory 51 of the obtained block number is sequentially read and stored in the data memory 44. The data memory 44 corresponding to the address of the address register 20 stores the contents of the data register 40. Thus, the data previously stored in the flash memory 51 and the data to be newly rewritten are held in the data memory 44.

The third step is a step of erasing a block of the flash memory 51 to be rewritten. This can be performed by the memory control means 10 writing a command to the flash memory 51. The control of the flash memory address selector 50 is the same as in the second stage. The fourth step is a step of writing new data to the flash memory 51. This can also be performed by the memory control means 10 writing a command to the flash memory 51, as in the third stage. In this way,
The block containing the data to be rewritten can be replaced with new content.

Here, a general flash memory control method will be described. Flash memory is
The contents can be deleted or rewritten. To erase or rewrite the contents, the memory chip enters an erase mode or a write mode by writing specific data to a specific address of the flash memory. Writing specific data to a specific address is referred to as writing a command. When entering the erase mode or write mode, the flash memory
It does not appear as M, but looks like an input / output device, and executes specified processing while exchanging information with the memory control means.

Next, reading or writing during writing will be described. Since a response to an external memory access cannot be made during writing, a response to the memory access is made to wait by the control signal output 4. As soon as the writing is completed, the reading or writing operation is started to complete the memory access response. The data remaining in the address register 20 and the data register 40 must be written to the flash memory 51 before the power is turned off. The writing procedure is the same as that described above.

As described above, according to this embodiment,
Address register 20, data register 40, flash memory address selector 51, and data memory 44
Is provided, and the flash memory 5 is
1 is controlled, so that a complicated memory write operation to the flash memory 51 can be easily performed without requiring dedicated software,
It can be handled in the same way as a normal memory. Therefore, access is possible without being conscious of the flash memory 51, and as a result, software created for a general memory can be operated as it is.

(Second Embodiment: Corresponding to Claim 2) FIG. 2 is a block diagram showing a configuration of a flash memory device according to a second embodiment of the present invention. In FIG.
1 is an address bus, 2 is a data bus, 3 is a control signal input, 4 is a control signal output, 11 is a memory control means, 20 is an address register, 30 is a comparator, 41 is a data memory address selector, 42 is a data memory, 43 is a data memory data buffer, 50 is a flash memory address selector, 51 is a flash memory, and 52 is a flash memory data buffer.

FIG. 4 is a schematic diagram showing a data bit configuration of the data memory 42. In FIG. 4, reference numeral 60 denotes a data portion, and 61 denotes a data flag portion. First, the data memory 42 will be described. The data memory 42 has the same address space as one block of the flash memory 51. The configuration of the data memory 42 will be described with reference to FIG. The data memory 42 stores the data section 6
0 and a data flag section 61. The data section 60 stores data to be updated in the flash memory 51 and can be read and written by the address bus 1 and the data bus 2 or by the memory control means 11. The data flag unit 61 indicates that data is set, and can be read and written only by the memory control unit 11. When writing is performed from the address bus 1 and the data bus 2, the data flag section 61 of the corresponding address is set. It is assumed that all the data flag units 61 are not set after the power is turned on.

Next, the flash memory device will be described. This flash memory device performs writing / erasing in units of a block composed of a plurality of memory cells. In this, the memory control means 11 performs overall control. The address register 20 holds a first partial address corresponding to a block number of a block to be written / erased among addresses composed of a first partial address (upper address) and a second partial address (lower address) of the address bus 1. I do. The comparator 30 compares the first partial address held by the address register 20 with the first partial address of the addresses on the address bus 1. The flash memory address selector 50 selects an address on the address bus 1 and an address output from the memory control means 11. The flash memory 51 receives an address output from the flash memory address selector 50 as an address input. Flash memory data buffer 52
Connects the flash memory 51 and the data bus 2.
The data memory address selector 41 stores the second partial address of the addresses on the address bus 1 and the memory control means 1
1 selects an address for control output. The data memory 42 has the same storage capacity as a block which is a unit of writing / erasing of the flash memory 51, and corresponds to an address to which data is written by using an address output from the data memory address selector 41 as an address input. The data flag is set. The data memory data buffer 43 connects the data memory 42 and the data bus 2.

Here, the memory control means 12 causes the comparator 30 to compare the address of the address bus 1 with the address held in the address register 20 when reading data. When a mismatch output is generated from the comparator 30, the address of the address bus 1 is supplied to the flash memory 51 through the flash memory address selector 50, and the data of the address of the address bus 1 is read from the flash memory 51. The read data is sent to the data bus 2 through the flash memory data buffer 52.

When a coincidence output is generated from the comparator 30, the second partial address of the addresses on the address bus 1 is supplied to the data memory 42 through the data memory address selector 41, and the When the data flag corresponding to the second partial address is set in the data memory 42, the data of the second partial address among the addresses on the address bus 1 is read from the data memory 42, and the data read from the data memory 42 is read. Data is stored in the data memory data buffer 43
When the data flag corresponding to the second partial address of the addresses on the address bus 1 is not set in the data memory 42, the address on the address bus 1 is passed through the flash memory address selector 50. To read the data at the address of the address bus 1 from the flash memory 51 and transfer the data read from the flash memory 51 to the flash memory data buffer 5.
2 to the data bus 2.

The memory control means 11 causes the address register 20 to write the first partial address of the address on the address bus 1 when data has not been written at all after power-on at the time of data writing. By providing the second partial address of the address of the address bus 1 to the data memory 42 through the data memory address selector 41, the data of the data bus 1 is passed through the data memory data buffer 43 to the address of the address bus 1 of the data memory 42. The data is stored at the position corresponding to the second partial address, and the data flag corresponding to the second partial address among the addresses on the address bus 1 is set.

When writing data at least once after power-on at the time of data writing, the memory control means 11 reads the first partial address held by the address register 20 and the first partial address of the address bus 1. Are compared by the comparator 30. In this case, when a match output is generated from the comparator 30, the second partial address of the address on the address bus 1 is transferred to the data memory 42 through the data memory address selector 41.
To store the data on the data bus 2 through the data memory data buffer 43 at a position corresponding to the second partial address of the addresses on the address bus 1 of the data memory 42, The data flag corresponding to the two-part address is set.

When a non-coincidence output is generated from the comparator 30, each address included in the block corresponding to the first partial address held by the address register 20 is sequentially and commonly shared by the data memory address selector 41 and the flash memory address selector. 50, the data is supplied to the data memory 42 and the flash memory 51 in common, so that the data memory 42 of the addresses included in the block corresponding to the first partial address among the addresses of the address bus in the flash memory 51 Data is copied to the data memory 42 only for the address for which the flag is not set, and the data of the block corresponding to the first partial address of the addresses on the address bus 1 in the flash memory 51 is erased.
The data of the data memory 42 is written to the block corresponding to the first partial address of the addresses of the address bus 1 in the flash memory 51, and the data memory 42
, The first partial address of the address on the address bus 1 is written to the address register 20, and the second partial address of the address on the address bus 1 is replaced with the data memory address selector 41.
The data of the data bus 2 is stored in a position corresponding to the second partial address of the addresses of the address bus 1 of the data memory 42 through the data memory data buffer 43. The data flag corresponding to the second partial address among the addresses of the bus 1 is set.

Hereinafter, the operation of the flash memory device will be described in detail. If data has not yet been written to the flash memory device even after power-on, the block number of the address to which the data has been written, that is, the first partial address of the address on the address bus 1 is written to the address register 20. . At the same time, data is written to the data portion 60 of the data memory 42 at an address corresponding to the second partial address of the addresses on the address bus 1, and the data flag portion 61 is set. At this point, no write operation is performed on the flash memory 51.

The operation of this embodiment will be described separately for reading and writing with reference to FIG. First, reading will be described. Reading has two states.
The address register 20 holds the number of the block that has been written in the past. The two states are determined by reading from a block to which writing has been performed in the past or reading from a block to which writing has not been performed in the past.

In the case of reading from a block to which writing has not been performed in the past, the comparator 30 outputs a mismatch signal indicating an address mismatch. In this case, at the time of reading, the address on the address bus 1 is applied to the flash memory 51 through the flash memory address selector 50. The flash memory 51 outputs the data at the added address, and outputs the data to the data bus 2 through the flash memory data buffer 52. The memory control means 11 includes a flash memory address selector 50
, The flash memory data buffer 52 is controlled. In this case, simple memory reading is performed.

When reading from the written block, the comparator 30 outputs a coincidence signal indicating the coincidence. In this case, the address of the address bus 1 is added to the data memory 42 through the data memory address selector 41. When a signal indicating that writing has been performed is obtained from the data flag section 61 (FIG. 4) of the data memory 42, the output of the data section 60 of the data memory 42 is output to the data bus 2 through the data memory data buffer 43. That is, data written in the data memory 42 in the past is read from the data memory 42.
When a signal indicating that writing has not been performed is obtained from the data flag section 61 (FIG. 4) of the data memory 42, the address on the address bus 1 is applied to the flash memory 51 through the flash memory address selector 50. The flash memory 51 outputs the data at the added address, and outputs the data to the data bus 2 through the flash memory data buffer 52. In this case, data has been read from the flash memory 51.

Next, data writing will be described. Writing can be roughly divided into three operations. The first case is that data has not yet been written to the flash memory device even after power-on. The second is when writing to the same block as the block that was recently written.
The third is a case where writing is performed on a block different from the recently written block.

When writing to the same block as the block which has been written recently, when the address supplied from the address bus 1 and the content of the address register 20 are compared by the comparator 30, it is determined that the address matches. Is output, and this is the memory control means 1
1 to determine the control method. The other points are the same as those described above in which data has not been written to the flash memory device even once after the power is turned on.

When writing to a block different from the recently written block, when the address supplied from the address bus 1 and the contents of the address register 20 are compared by the comparator 30, the comparator 30 does not agree. Are output to the memory control means 11 to determine the control method. In this case, writing is performed on the flash memory 51. The write operation is broken down into five stages.

First, the contents of the flash memory 51 are copied to the data memory 42. Memory control means 11
Performs the following operations while sequentially changing the addresses of the flash memory 51 and the data memory 42. First, the data memory 42 is read, and if the data flag section 61 is set, it indicates that writing has occurred, and the process proceeds to the next address. If the data flag section 61 has not been set, the flash memory 51 is read, and the read data is written to the data section 60 of the data memory 42. Thus, the data for updating the flash memory 51 is ready in the data memory 42.

The second stage is erasing of the flash memory 51, and the third stage is writing to the flash memory 51, which is the same as the third and fourth stages described in the first embodiment. The fourth stage is the erasure of the data flag section 61 of the data memory 42. Memory control means 11
Writes a state in which no data is set in the data flag section 61 of the data memory 42.

In the fifth stage, write information is held in the address register 20 and the data memory 42. The block number of the written address is written to the address register 20. At the same time, the data memory 42
Is written into the data section 60 at the corresponding address, and the data flag section 61 is set. The first
Unlike the embodiment, while the writing to the flash memory 51 is being performed, the access is made to wait by the control signal output 4, so that the reading or writing request comes during the writing to the flash memory 51. Never.

As described above, according to this embodiment,
The address register 20, the comparator 30, the data memory address selector 41, the data memory 42, the data memory data buffer 43, and the flash memory address selector 51 are provided, and the writing to the flash memory 51 is controlled by the memory control means 11. Flash memory 5 without special software
1 can easily perform a complicated memory write operation, and can be handled in the same manner as a normal memory. Therefore, access is possible without being conscious of the flash memory 51, and as a result, software created for a general memory can be operated as it is. In addition, in continuous writing to the same block, writing to the flash memory 51 does not occur, and writing occurs for the first time in writing to another block. Therefore, continuous writing to the same block is completed by one writing, and The number of times of writing can be reduced, the access restriction time by writing can be reduced, and the performance degradation due to the use of the flash memory 51 can be relatively reduced.

If a set of an address register and a data register is added, the bus does not wait for writing from the bus in which writing to the flash memory 51 occurs, as in the first embodiment. Can be. Also,
Data memory address selector 41 and data memory 42
The data buffer 43 includes a dual port memory 45 having two address terminals AD1 and AD2 as shown in FIG. 6 and two data terminals DT1 and DT2 corresponding to the address terminals AD1 and AD2, respectively.
Can be replaced by Specifically, two input terminals of the data memory address selector 41 correspond to two address terminals AD1 and AD2 of the dual port memory 45, and an output terminal of the data memory 42 and one data terminal DT1 of the dual port memory 45. Corresponds to the output terminal of the data memory data buffer 43 and the other data terminal DT2 of the dual port memory 45.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a flash memory device according to the embodiment. 3, 1 is an address bus, 2 is a data bus, 3 is a control signal input, 4 is a control signal output, 12 is a memory control means, 21 is an address tag memory address selector, 22 is an address tag memory, 23
Is an address tag memory data buffer, 30 is a comparator,
41 is a data memory address selector, 42 is a data memory, 43 is a data memory data buffer, 50 is a flash memory address selector, 51 is a flash memory, and 52 is a flash memory data buffer.

FIG. 5A shows the bit configuration of the address of the flash memory device, and FIG. 5B shows the bit configuration of the address tag memory 22. In the bit configuration of the address of the flash memory device in FIG. 5A, the left side of the figure shows the upper digit side. The whole can be divided into three parts (first partial address (for example, upper address), second partial address (for example, middle address), and third partial address (for example, lower address)), and lower digits (third partial address) Is a portion corresponding to the block address space of the flash memory 51. For example, if the block size is 25
If there are six addresses, eight bits correspond to this. The next part (second partial address) is a part added to the address of the address tag memory 22. This part and a part corresponding to the above block address are added to the address of the data memory 42. The remaining portion of the address (first partial address) is added to the data in the address tag memory 22.

In the bit configuration of the data in the address tag memory 22 shown in FIG. 5B, reference numeral 62 denotes the data (data stored in the data memory 42) in the uppermost part (first partial address) of FIG. (Part of the block number), which is called an address tag section.
1 is written in accordance with a condition at the time of writing. This portion can be read and written by the memory control means 12, and cannot be read and written from the address bus 1 and the data bus 2.
63 is an address tag flag section,
Is written in accordance with the condition at the time of writing to the address tag unit 62, indicating that the address tag unit 62 is valid, and is set when writing to the address tag unit 62 occurs. This part can be read and written by the memory control means 12, and the address bus 1
In addition, reading and writing from the data bus 2 cannot be performed.

Next, the flash memory device will be described. This flash memory device performs writing / erasing in units of a block composed of a plurality of memory cells. In this, the memory control means 12 performs overall control. The address tag memory address selector 21 stores a second partial address corresponding to a block number of a block to be written / erased out of an address consisting of a first partial address, a second partial address, and a third partial address of the address bus 1 and a memory. An address output by the control means 12 is selected. The address tag memory 22 receives the address output from the address tag memory address selector 21 as an address input, and sets an address tag flag corresponding to the address where data is written. The address tag memory data buffer 23 connects the address tag memory 22 and the address bus 1 and supplies a first partial address of the address bus 1 to the address tag memory 22 as a data input. The comparator 30 compares the address read from the address tag memory 22 with the first partial address of the address bus 1 using the second partial address of the address bus 1 as an address input. Flash memory address selector 5
0 selects an address on the address bus 1 and an address output from the memory control means 12. Flash memory 51
Uses the address output from the flash memory address selector 50 as an address input. The flash memory data buffer 52 connects the flash memory 51 and the data bus 2. The data memory address selector 41 selects a second partial address and a third partial address of the addresses on the address bus 1 and an address for control output from the memory control means 12. Data memory 42
Has the same capacity as the number corresponding to the size of the address space of the second partial address of the block, which is the unit of writing / erasing of the flash memory 51. A data flag is set corresponding to the address where the data is written. Data memory data buffer 43
Connects the data memory 42 and the data bus 2.

The above-mentioned memory control means 12 controls the first of the addresses on the address bus 1 when reading data.
The second of the partial address and the address of the address bus 1
Partial address is assigned to address tag memory address selector
The comparator 30 compares the data read from the address tag memory 22 as the address input through 1 with the comparator 30. In this case, when a mismatch output is generated from the comparator 30, the address of the address bus 1 is transferred to the flash memory 51 through the flash memory address selector 50.
To the address bus 1 from the flash memory 51.
Of the flash memory 5
The data read from 1 is sent to the data bus 2 through the flash memory data buffer 52.

When a coincidence output is generated from the comparator 30, the second partial address and the third partial address of the addresses on the address bus 1 are supplied to the data memory 42 through the data memory address selector 41. Are set in the data memory 42 when the data flags corresponding to the second partial address and the third partial address of the
, The data of the second partial address and the third partial address of the addresses of the address bus 1 are read, and the data read from the data memory 42 is sent to the data bus 2 through the data memory data buffer 43. On the other hand, when the data flags corresponding to the second partial address and the third partial address of the addresses on the address bus 1 are not set in the data memory 42, the address on the address bus 1 is transferred to the flash memory 51 through the flash memory address selector 50. Supply
The data at the address of the address bus 1 is read from the flash memory 51, and the data read from the flash memory 51 is sent to the data bus 2 through the flash memory data buffer 52.

Further, at the time of writing data, the memory control means 12 writes the second partial address of the address on the address bus 1 to the address tag memory before completing writing to all the addresses of the address tag memory 22. The address input is made through the address selector 21 and the first partial address of the address on the address bus 1 is written as data input to the address tag memory 22 to write the data. And the second partial address and the third partial address of the addresses on the address bus 1 are passed through the data memory address selector 41 to the data memory 4.
2 to store the data on the data bus 2 through the data memory data buffer 43 at the positions corresponding to the second and third partial addresses of the addresses on the address bus 1 of the data memory 42, The data flag corresponding to the second partial address and the third partial address among the addresses on the address bus 1 at 42 is set.

Further, at the time of data writing, the memory control means 12 completes writing to all addresses of the address tag memory 22 and
After all the address tag flags corresponding to all the addresses of the address bus 1 are set, the address tag memory 22 receives the first partial address of the address of the address bus 1 and the second partial address of the address of the address bus 1 as an address input. Is compared with the data read from the.

In this case, when a coincidence output is generated from the comparator 30, the second partial address and the third partial address of the addresses on the address bus 1 are transferred to the data memory 42 through the data memory address selector 41.
To store the data on the data bus 2 through the data memory data buffer 43 at a position corresponding to the second partial address and the third partial address of the addresses on the address bus 1 of the data memory 42, and The data flag corresponding to the second partial address and the third partial address among the addresses on the address bus 1 is set.

When a non-coincidence output is generated from the comparator 30, a plurality of sets of the first partial address and the second partial address respectively determined by all the addresses of the address tag memory 22 and the data stored at those addresses are set. Each address included in the corresponding number of blocks is sequentially and commonly applied to the data memory 42 and the flash memory 51 through the data memory address selector 41 and the flash memory address selector 50, respectively. Out of the addresses included in the blocks corresponding to the plurality of sets of the first partial address and the second partial address out of the plurality of addresses, only the addresses for which the data flag is not set in the data memory 42 are stored in the data memory. To be copied to 2. Subsequently, the data of the blocks corresponding to a plurality of sets of the first partial address and the second partial address respectively determined by all the addresses of the address tag memory 22 and the data stored in those addresses are erased. Subsequently, the data of the data memory 42 is written to blocks corresponding to a plurality of sets of the first partial address and the second partial address among the addresses of the address bus 1 in the flash memory 51. Subsequently, the setting of the data flag in the data memory 42 is canceled. Then, until the writing to all the addresses of the address tag memory 22 is completed, the second partial address of the addresses on the address bus 1 is used as the address input through the address tag memory address selector 21 and the address of the address on the address bus 1 is input. The first part of the addresses is used as a data input to write to the address tag memory 22, and the address tag flag corresponding to the address in the address tag memory 22 at which the data is written is set. Address bus 1
Are given to the data memory 42 through the data memory address selector 41 to transfer the data of the data bus 2 to the address of the address bus 1 of the data memory 42 through the data memory data buffer 43. Among the addresses of the address bus 1 in the data memory 42 and the third partial address and the third partial address.
The data flag corresponding to the partial address is set.

The basic operation in this embodiment is as follows.
Since it is close to the second embodiment, only the difference will be described in more detail. The big difference is the address register 2
0, the address tag memory address selector 21
And the use of the address tag memory 22 and the address tag memory data buffer 23, and the capacity of the data memory 42 is increased corresponding to the capacity. As a result, the written data can be held in a plurality of blocks, and the number of writes to the flash memory 51 can be reduced as compared with the second embodiment.

In reading, blocks to which writing has been performed in the past are recorded in the address tag memory 22. At the time of reading from a block in which writing has not occurred in the past, the comparator 30 generates a mismatch signal.
A path for the flash memory data buffer 52 and the data bus 2 is created. This is a direct read from the flash memory 51.

When reading from a block in which writing has occurred in the past, the comparator 30 issues a coincidence signal,
In response to this, the memory control means 12 first makes two paths including the paths of the address bus 1, the data memory address selector 41 and the data memory 42 and the paths of the address bus 1, the flash memory address selector 50 and the flash memory 51. . Here, if a signal indicating that data has been written in the past is obtained from the data flag unit 61 of the data memory 42, the data memory data buffer 4
3. Create a path for the data bus 2 and output the contents of the past write. On the other hand, if a signal indicating that writing has not been performed in the past is obtained from the data flag unit 61 of the data memory 42, the flash memory data buffer 5
2. Make a path for the data bus 2 and use the flash memory 51
Output the contents of

If a signal indicating the coincidence is obtained from the comparator 30 in the writing, the data memory address selector 4
1. The contents written along the path of the data memory 42 are stored in the data memory 42. When a signal indicating a mismatch is obtained from the comparator 30, writing to the flash memory 51 is performed. This part is the same as in the second embodiment. When the writing to the flash memory 51 is completed, the address tag memory 22 and the data memory 42 are updated.

As described above, according to this embodiment, the address tag memory address selector 21, the address tag memory 22, the address tag memory data buffer 23,
The comparator 30, the data memory address selector 41, the data memory 42, the data memory data buffer 43, and the flash memory address selector 51 are provided, and the writing to the flash memory 51 is controlled by the memory control means 12. , A complicated memory write operation to the flash memory 51 can be easily performed, and can be handled in the same manner as a normal memory. Therefore, access is possible without being conscious of the flash memory 51,
As a result, software created for a general memory can be operated as it is. In addition, in continuous writing to a plurality of blocks, writing to the flash memory 51 does not occur, and writing to a plurality of blocks occurs for the first time in writing to another block other than the plurality of blocks. The writing is completed by one writing, and the writing time can be further reduced. Therefore, the number of times of writing can be further reduced, and the access restriction time by writing is further reduced.
Can be further reduced by the use of a.

Instead of the address tag memory address selector 21, the address tag memory 22, and the address tag memory data buffer 23, two address terminals AD1 and AD2 as shown in FIG.
1, AD2, two systems of data terminals DT1, DT
A dual port RAM 24 having two RAMs can also be used. Specifically, two input terminals of the address tag memory address selector 21 and the dual port RAM 24
Address terminals AD1 and AD2 correspond to the output terminal of the address tag memory 22 and the dual port RAM.
It corresponds to one of the 24 data terminals DT1. In addition,
The other data terminal DT2 of the dual port RAM 24
Is connected to the address terminal AD2 of the dual port RAM 24.

In FIG. 5A, the arrangement order of the bit configuration in the address space can be rearranged, and there is no need to continuously divide the bits. As mentioned in the second embodiment, it is possible to open the bus at the beginning of the write operation by placing the address register and the data register before the address memory address selector and the data memory address selector.

[0058]

According to the flash memory device of the first aspect, since writing to the flash memory is controlled by the memory control means, complicated memory writing to the flash memory can be performed without requiring dedicated software. The operation can be performed easily, and it can be handled in the same way as a normal memory. Therefore, a memory device that can use the software of a conventional personal computer or personal digital assistant using a general memory as it is, can reduce the performance degradation due to the use of the flash memory, and has no danger due to the loss of the battery Can be realized, which is very advantageous in practice.

According to the flash memory device of the present invention, since writing to the flash memory is controlled by the memory control means, a complicated memory writing operation to the flash memory can be performed without requiring dedicated software. It can be done easily and can be handled like a normal memory. In addition, continuous writing to the same block is completed by one writing, and the writing time can be reduced. Therefore, a memory device that can use the software of a conventional personal computer or personal digital assistant using a general memory as it is, can reduce the performance degradation due to the use of the flash memory, and has no danger due to the loss of the battery Can be realized, which is very advantageous in practice. According to the flash memory device of the third aspect, since writing to the flash memory is controlled by the memory control means, a complicated memory writing operation to the flash memory can be easily performed without requiring dedicated software. And can be treated like normal memory.
In addition, continuous writing to a plurality of blocks is completed by one writing, and the writing time can be further reduced. Therefore, a memory device that can use the software of a conventional personal computer or personal digital assistant using a general memory as it is, can reduce the performance degradation due to the use of the flash memory, and has no danger due to the loss of the battery Can be realized, which is very advantageous in practice.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a flash memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a flash memory device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a flash memory device according to a third embodiment of the present invention.

FIG. 4 is a schematic diagram showing a bit configuration of data in a data memory.

FIG. 5 is a schematic diagram showing a bit configuration of data of an address tag memory.

FIG. 6 is a schematic diagram for explaining replacement of a data memory address selector, a data memory, and a data memory data buffer with a dual port memory;

FIG. 7 is a schematic diagram for explaining replacement of an address tag memory address selector, an address tag memory, and an address tag memory data buffer with a dual-port memory;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address bus 2 Data bus 3 Control signal input 4 Control signal output 10 Memory control means 11 Memory control means 12 Memory control means 20 Address register 21 Address tag memory address selector 22 Address tag memory 23 Address tag memory data buffer 30 Comparator 40 Data Register 41 Data memory address selector 42 Data memory 43 Data memory data buffer 44 Data memory 50 Flash memory address selector 51 Flash memory 52 Flash memory data buffer 60 Data section 61 Data flag section 62 Address tag section 63 Address tag flag section

Claims (3)

[Claims] 1. A flash memory device for performing writing / erasing in units of a block composed of a plurality of memory cells, comprising: a memory control means for controlling the whole; an address register for holding an address of an address bus; A data register for holding data on a data bus, a flash memory address selector for selecting an address of the address bus and an address output by the memory control means, and an address output by the flash memory address selector as an address input. A flash memory, a flash memory data buffer connecting the flash memory and the data bus, and a data memory having the same storage capacity as a block which is a unit for performing writing / erasing of the flash memory, The memory control means When reading data, the address of the address bus is supplied to the flash memory through the flash memory address selector, the data of the address of the address bus is read from the flash memory, and the data read from the flash memory is read. Through the flash memory data buffer to the data bus.The memory control means causes the address register to hold the address of the address bus and the data register to hold the data of the data bus when writing data. Obtains a block number of a block to be written / erased in the flash memory from the address held in the address register, and writes an address included in the block of the block number into the flash memory. The data of each address other than the address held in the address register among all the addresses of the block indicated by the block number is read from the flash memory by supplying the data to the flash memory through a flash memory address selector. The data read from the memory is written in a position corresponding to each address other than the address held in the address register among all addresses of the block in the data memory, and the data held in the data register is written in the data memory. At the position corresponding to the address held in the address register, erase the data of the block of the block number in the flash memory, and delete the block of the block number in the flash memory. Flash memory device is characterized in that so as to write the data of the data memory for. 2. A flash memory device for performing writing / erasing in units of a block composed of a plurality of memory cells, comprising: a memory control means for controlling the whole; a first partial address and a second address on an address bus. An address register for holding a first partial address corresponding to a block number of a block to be written / erased among addresses composed of partial addresses; and a first partial address held by the address register and an address of the address bus. A flash memory address selector for selecting an address on the address bus and an address output from the memory control means; and an address input for outputting an address output from the flash memory address selector. Flash memory and the flash A flash memory data buffer for connecting a memory and the data bus, a data memory address selector for selecting a second partial address of the addresses on the address bus and an address for control output by the memory control means, The flash memory has the same storage capacity as a block which is a unit for performing writing / erasing, and an address output from the data memory address selector is used as an address input, and a data flag is set corresponding to an address where data is written. A data memory to be set, and a data memory data buffer for connecting the data memory and the data bus, wherein the memory control unit is configured to control the address of the address bus and the address held in the address register when reading data. With the above comparator When a mismatch output is generated from the comparator, the address of the address bus is supplied to the flash memory through the flash memory address selector, and the data of the address of the address bus is read from the flash memory. The data read from the memory is sent to the data bus through the flash memory data buffer. When a match output is generated from the comparator, the second partial address of the address on the address bus is passed through the data memory address selector. Is supplied to the data memory, and when the data flag corresponding to the second partial address of the addresses on the address bus is set in the data memory, the address of the address on the address bus is read from the data memory. The data of the second partial address is read out, and the data read out from the data memory is sent out to the data bus through the data memory data buffer, and the data corresponding to the second partial address among the addresses of the address bus is read. When the data flag is not set in the data memory, the address of the address bus is supplied to the flash memory through the flash memory address selector, and the data of the address of the address bus is read from the flash memory. The data read out from the flash memory is sent out to the data bus through the flash memory data buffer, and at the time of data writing, when no data has been written after power-on, A first partial address of the address bus is written to the address register, and a second partial address of the address bus is provided to the data memory through the data memory address selector, thereby providing data on the data bus. Through the data memory data buffer at a position corresponding to a second partial address of the address of the address bus of the data memory, and a data flag corresponding to a second partial address of the address of the address bus is stored. The memory control means, at the time of data writing, when data has been written at least once after power-on, the first partial address held by the address register and the first partial address of the address bus are compared with each other. Comparator When a match output is generated from the comparator, a second partial address of the address on the address bus is supplied to the data memory through the data memory address selector, thereby transferring the data on the data bus to the data memory. Storing the data in the data memory at a position corresponding to a second partial address of the addresses of the address bus through the data buffer, and setting a data flag corresponding to a second partial address of the addresses of the address bus; When a mismatch output is generated from the comparator, each address included in the block corresponding to the first partial address held by the address register is sequentially and commonly passed through the data memory address selector and the flash memory address selector, respectively. The data flag is not set in the data memory among the addresses included in the block corresponding to the first partial address of the addresses of the address bus in the flash memory by commonly providing the data to the memory and the flash memory. Only the data of the address is copied to the data memory, the data of the block corresponding to the first partial address of the address of the address bus in the flash memory is erased, and the data of the address of the address bus in the flash memory is deleted. First
Causing the data of the data memory to be written to a block corresponding to the partial address, canceling the setting of a data flag of the data memory, and writing the first partial address of the addresses of the address bus to the address register; Of the address bus of the data memory through the data memory data buffer by providing a second partial address among the addresses of the data memory to the data memory through the data memory address selector.
A flash memory device which is stored at a position corresponding to a partial address and sets a data flag corresponding to a second partial address of the addresses on the address bus of the data memory. 3. A flash memory device for performing writing / erasing in units of a block composed of a plurality of memory cells, comprising: a memory control means for controlling the whole; a first partial address of an address bus; An address tag memory address selector for selecting a second partial address corresponding to a block number of a block to be written / erased among addresses composed of a partial address and a third partial address and an address output by the memory control means; An address tag memory in which an address output from the address tag memory address selector is set as an address input and an address tag flag is set corresponding to an address where data is written, and the address tag memory and the address bus are connected. Before the first partial address of the address bus. An address tag memory data buffer to be supplied to the address tag memory as a data input; and an address read out from the address tag memory using the second partial address of the addresses of the address bus as an address input and a second address of the address bus address. A comparator for comparing one partial address; a flash memory address selector for selecting an address on the address bus and an address output by the memory control means; and an address output from the flash memory address selector as an address input. A flash memory, a flash memory data buffer for connecting the flash memory and the data bus, a second partial address and a third partial address of the addresses on the address bus, and a control for outputting the data from the memory control means. A data memory address selector for selecting an address for control, and the same capacity as the number corresponding to the size of the address space of the second partial address of the block which is a unit of writing / erasing of the flash memory, An address output from the data memory address selector as an address input, a data memory in which a data flag is set corresponding to an address in which data is written, a data memory data buffer connecting the data memory and the data bus, The memory control means, at the time of data reading, uses a first partial address of the address of the address bus and a second partial address of the address of the address bus as an address input through the address tag memory address selector. From the address tag memory The read data is compared with the comparator. When a mismatch output is generated from the comparator, the address of the address bus is supplied to the flash memory through the flash memory address selector, and the address is output from the flash memory. The data of the address of the bus is read, the data read from the flash memory is sent to the data bus through the flash memory data buffer, and when a match output is generated from the comparator, the data is output through the data memory address selector. A second partial address and a third partial address of the addresses of the address bus are supplied to the data memory, and a data flag corresponding to the second partial address and the third partial address of the addresses of the address bus is stored in the data memory. The second partial address, and a third of the address of said address bus from said data memory when it is set in the memory
Causing the data of the partial address to be read, sending the data read from the data memory to the data bus through the data memory data buffer, and selecting a second partial address and a third of the addresses of the address bus.
When the data flag corresponding to the partial address is not set in the data memory, the address of the address bus is supplied to the flash memory through the flash memory address selector, and the data of the address of the address bus is read from the flash memory. And causing the data read from the flash memory to be sent out to the data bus through the flash memory data buffer. At the time of data writing, the memory control means completes writing to all addresses of the address tag memory. In the prior art, a second partial address of the addresses on the address bus is used as an address input through the address tag memory address selector, and a first partial address of the addresses on the address bus is used as data. As an input, the address tag memory is written, and an address tag flag corresponding to the address at which data is written in the address tag memory is set, and a second partial address and a third partial address of the addresses of the address bus are set. By providing an address to the data memory through the data memory address selector, the data on the data bus corresponds to a second partial address and a third partial address of the address on the address bus of the data memory through the data memory data buffer. And setting a data flag corresponding to a second partial address and a third partial address of the addresses of the address bus in the data memory. At the time of writing, after writing to all addresses of the address tag memory is completed and all address tag flags corresponding to all addresses of the address tag memory are set,
The comparator compares data read from the address tag memory with a first partial address of the addresses of the address bus and a second partial address of the addresses of the address bus as an address input. When a match output is generated from the data bus, the data on the data bus is supplied to the data memory by providing the second partial address and the third partial address of the addresses on the address bus to the data memory through the data memory address selector. The data is stored in a position corresponding to a second partial address and a third partial address of the addresses of the address bus of the data memory through a buffer, and the second partial address and the second of the addresses of the address bus of the data memory are stored. Supports three-part addresses When a non-coincidence output is generated from the comparator, a plurality of sets of a first partial address and a second partial address respectively determined by all the addresses of the address tag memory and the data stored at those addresses are set. By sequentially giving each address included in the blocks corresponding to the addresses to the data memory and the flash memory in common through the data memory address selector and the flash memory address selector, respectively, the address in the flash memory is obtained. Only the addresses of the buses where the data flag is not set in the data memory among the addresses included in the blocks corresponding to the plurality of sets of the first partial address and the second partial address among the addresses of the bus are forwarded. A plurality of sets of the first partial address and the second partial address corresponding to all the addresses in the address tag memory and the data stored in the addresses, and erase the data in the blocks corresponding to the plurality of sets, Causing the data of the data memory to be written to blocks corresponding to a plurality of sets of the first partial address and the second partial address of the addresses of the address bus in the flash memory, canceling a data flag set of the data memory, Until the writing to all the addresses of the address tag memory is completed, the second partial address of the addresses on the address bus is used as an address input through the address tag memory address selector, and the second partial address of the addresses on the address bus is input. One-part address data As an input, the address tag memory is written, and an address tag flag corresponding to the address at which data is written in the address tag memory is set, and a second partial address and a third partial address of the addresses of the address bus are set. By providing an address to the data memory through the data memory address selector, the data on the data bus corresponds to a second partial address and a third partial address of the address on the address bus of the data memory through the data memory data buffer. And a data flag corresponding to a second partial address and a third partial address of the addresses of the address bus in the data memory. Yumemori apparatus.