JPH103748A - Digital signal recording method and reproduced signal processing device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To prevent pseudo sync detection when matching a recording form of a disk. A pair of search counters (56, 58) for detecting a sync code from a reproduced digital signal and counting macroblock length data obtained based on a sync pulse (SP) at that time, and a check pulse (CPa) obtained from each counter. , CPb and the sync pulse, the determination pulses JPa and JPb are generated, and the reproduced digital signal is captured by the AND output of these determination pulses to generate a macroblock header and the like and return to the data stream before recording. Sync pulse SP when pulses CPa and CPb are obtained by sync determination means 60
Of the reproduced pseudo sync is determined by the presence or absence of. At the same time, when the sync pulse SP cannot be obtained, it is regarded as a pseudo sync and the header generation processing is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording method for recording a serial digital signal on a disk-shaped recording medium, and a reproduction signal processing apparatus therefor. Specifically, if the synchronization bit included in the data stream exceeds the data transfer unit length of the disk-shaped recording medium, only a plurality of specific synchronization bits are used, and these are converted to a specific sync code and recorded. Then, processing is performed on the basis of the reproduced sync code so that the synchronization bit can be restored and the pseudo sync generated by the reproduction can be eliminated.

[0002]

2. Description of the Related Art A serial digital interface SDI interface is known as a type of serial transmission of digital signals, but the SDI interface limits the media that can be transmitted. So recently,
A serial digital data interface SDDI interface is known as an extended interface that diversifies the media that can be handled while maintaining compatibility with the SDI interface. MPEG2 4: 2: 2 studio profile signals, which are a kind of image compression format, are transmitted in this SDDI format.

The SDDI interface will be described with reference to FIG. As shown in FIG. 6, one frame of image information is compression-encoded in units of macroblocks MB. In the case of the NTSC system, one frame of image information is divided into 45 blocks in the horizontal direction X and 32 blocks in the vertical direction Y.

The SDDI format is shown in FIG.
GOP (Group of Pic)
ture) is composed of a plurality of sectors, and one sector is 40 sectors.
It consists of 96 bytes. As shown in the figure, a sector has a plurality of system data (such as a time code) at the head in byte units, and is followed by a macroblock header (MB-byte).
(Y, MB-X). After the macroblock header, a length indicating the data length of the macroblock (Length)
And macro block data (data) follow. Since the macroblock data has a variable length, the number of macroblocks inserted in one sector is not constant.

As described above, the header of the macroblock (macroblock address data) and the length indicating the data length are always inserted before the macroblock data. Further, as shown in the figure, immediately before the macroblock header, a 1-bit macroblock synchronization bit (SYNC B)
IT) is added. This ensures that macroblock information can be detected. By adding this synchronization bit, the data length inserted immediately before the macroblock header becomes 9 bits.

[0006]

When such a serial digital signal of the SDDI format is recorded on a recording medium, for example, a large-capacity disk such as a magneto-optical disk MO, the data must be recorded and reproduced on the disk in 8 minutes.
Since the transmission is performed in units of bits, the transmission data of the SDDI format must be converted into a data width corresponding to the disk.

This data conversion may be performed while allocating the synchronization bit to a unique code (a sync code having an n-word structure) that is not used when coding image data, for example. Unique codes assigned as sync codes include (00,00,00,00,00,8
A sync code having a 6-word configuration such as 0) can be considered.

However, in this case, since an n-word synchronization code is added in units of macroblocks, the entire data length increases, and it is hard to say that this is a very effective conversion means. When such a conversion code is used, a data error may occur this time.

In the above-described disc, pre-erase is performed, and data on the disc is all zero (00).
After that, data recording is performed, but if dust or the like is attached to the disc, a block-like writing error may occur. Then, at the time of reproduction, this block-like write error portion is reproduced as continuous data of "00", which may cause a pseudo sync code.

This possibility is higher than when a hard disk drive that does not perform pre-erase processing is used. If the pseudo code is processed as a sync code, an incorrect reproduction process will be performed because it cannot be distinguished from a correct sync code.

Accordingly, the present invention has been made to solve such a conventional problem. Even when a digital signal is converted so as to conform to a disk format, the digital signal can be converted without increasing the entire data amount. In addition, the present invention proposes a method for recording serial digital data and a reproduction signal processing device for the serial digital data, which can accurately distinguish the pseudo-synchronous code.

[0012]

In order to solve the above-mentioned problem, in a digital signal recording method according to the present invention, a data stream to be recorded includes a synchronization bit for block detection for each unit block. When recording a digital signal exceeding the unit length of data transmission / reception of the recording medium by the synchronization bit on the recording medium, a predetermined number of the synchronization bits provided at the head of the sector for each sector including the unit block. Only the specific sync code is converted to the same unit length as the data transfer, and the digital signal including the converted sync code is recorded on the recording medium.

In the reproduction signal processing apparatus according to the present invention, the reproduction digital signal is supplied to the data inversion means, and the synchronization bit is restored from the reproduction digital signal converted into the data transfer unit length to recover the original bit. And a digital signal of the data stream.

According to the present invention, only the first two synchronization bits of the synchronization bits arranged for each macro block arranged in each sector are used. Then, these synchronization bits are converted into a specific sync code. This sync code is an n-word sync code. The third and subsequent synchronization bits are deleted. At the same time, the macroblock headers MB-Y and MB-X inserted into the third and subsequent macroblocks are also deleted. This is because the amount of data is not increased. By this processing, a serial digital signal converted to the data transfer unit length to the disk is obtained, and is recorded on the disk in this state.

At the time of reproduction, the synchronization bit and the macroblock header are respectively restored based on the detected sync code. Then, based on whether or not the sync code is detected at the data corresponding to the macroblock length, whether the detected sync code is the original sync code,
It is determined whether the code is a pseudo sync code. If no sync code has been obtained for the macroblock length, it is determined to be a pseudo sync code. At that time, restoration processing is not performed, and restoration processing is executed only when the sync code is correct. This can prevent erroneous reproduction processing based on the pseudo sync code.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a serial digital signal recording method and a reproduction signal processing apparatus using the recording method according to the present invention will be described in detail with reference to the drawings.

When a disk such as a magneto-optical disk is used as a recording medium, it is necessary to perform the conversion processing of the synchronization bit and the reverse conversion processing as described above. Therefore, as shown in FIG. 1, in this disk recording / reproducing apparatus 10, a recording signal processing apparatus 20 is inserted in a data recording system,
A reproduction signal processing device 30 is inserted in the reproduction system. Terminal 1
The digital signal conforming to the SDDI format input from 8 is converted into a serial digital signal that can be recorded on the disk 12 by the recording signal processor 20 (for example, a data string of SCSI-II type for high-speed processing).
The information is recorded on the disk 12 using the optical pickup means 16.

The reproduced digital signal reproduced from the disk 12 is inversely converted from the sync code to the original synchronization bit by the reproduced signal processing device 30, and the macro block addresses MB-X and MB lost during recording are described later. −
Y is restored to generate a digital signal in SDDI format.

As shown in FIG. 7, in the SDDI format digital signal (digital signal before recording), system data such as a time code (two bytes in this example) is inserted at the beginning of each sector as described above. And a plurality of macroblock-compressed compressed video data inserted subsequently to the compressed video data. A header for a macroblock MB is inserted at a break between a plurality of compressed video data. This header contains 1 indicating the position of the macroblock.
It is address data (MB-Y, MB-X) for each byte. Further, the data length of the macroblocked video data is inserted immediately after the header as length data (for 2 bytes). Each of these data has a byte configuration, but a 1-bit synchronization bit is inserted immediately before the macroblock header to facilitate detection of the macroblock.

The recording signal processing device 20 converts such a data stream into a signal form after recording as shown in FIG. 7 in order to conform to the recording type of the disk 12. That is, in the present invention, a conversion process as shown in FIG. 7 is performed. (1) The synchronization bit is a unique code, in this example (0
(0,00,00,00,00,80) is converted to a sync code composed of 6 words. (2) Since the new sync code is composed of 6 words,
If all the synchronization bits are converted into this sync code, the data amount of the sector exceeds the specified data amount (4096 bytes). Therefore, in this example, at least the first and second synchronization bits of each sector correspond to the above-mentioned sync code. And the other synchronization bits are removed from the data stream (bit stream). (3) Along with the removal of the synchronization bit, only the first and second block headers of the macroblock MB are used, and all others are removed. However, length data indicating the data length of the macroblock is left. By the processing of (1), the data width is all 8 bits. 6 as sync code
By performing the processes (2) and (3) such that the third and subsequent synchronization bits and the macroblock header (address data) are deleted instead of assigning a word, the data amount of the entire digital signal can be increased. Absent.

The greater the number of synchronization bits used as a sync code, the more reliably macroblock data can be detected, but the greater the data redundancy. Therefore, the number of conversion synchronization bits is actually 2 to 4.

At the time of data reproduction, the first and second sync codes and the macroblock header inserted at the beginning of the sector are used to restore the addresses and synchronization bits of the subsequent macroblocks, respectively. , The restored macroblock header and synchronization bit are inserted and added. Then, a countermeasure against a pseudo sync code at the time of reproduction is performed using these two sync codes.

FIG. 2 shows an embodiment of the reproduction signal processing device 30 which takes measures against the pseudo sync code. A serial digital signal (reproduced data string) reproduced from the disk 12 is supplied to the terminal 32, and this is temporarily stored in a buffer memory 36 via a SCSI controller 34. Thereafter, the data is supplied to an inverse conversion processing circuit 50, and insertion and addition processing of a macroblock header is performed. In the inverse conversion processing circuit 50, as described later, a process of discriminating the pseudo sync code from the original sync code is performed, and when it is determined that the pseudo sync code is used, the inverse conversion process is not performed.

The data sequence after the inverse conversion processing is stored in a main memory 38 composed of a plurality of frame memories, and then the digital signals sequentially read out from the memory 38 are supplied to a sync addition circuit 40 to generate a 1-bit synchronous signal. Bits are added to form the data stream shown in FIG.
The data is sent to the DDI transmission unit 42. Then, the digital signal of the SDDI format as shown in FIG.
It is sent to an I transmission system (not shown).

FIG. 3 shows an example of the inverse conversion processing circuit 50.
Referring to FIG.
2 and a sync code is detected. The sync code is a unique special code that is not used as a conversion code or control code for image data as shown in FIG. 7, and in this example, is a six-word (00,00,00,00,00,80,80). Since the configured code is used as the conversion sync code for the synchronization bit, this sync code is detected. Therefore, a sync code is detected based on the system clock CK (FIG. 4A).

When a sync code is detected, a sync pulse S for one clock immediately after the last sync word (80) is detected.
P (FIG. 4D) is output. The sync pulse SP is supplied to the counter control means 54, and further supplied with a sector head pulse STP (C in the figure) indicating the head of the sector, the clock CK described above, and a determination pulse JP (J in the figure) described later. Is done.

From the reproduced digital signal input based on these signals, the macroblock length data Length
.. Are extracted. Therefore, the control means 54
4E, a sampling pulse EP shown in FIG. 4E is formed based on the sync pulse SP, and the length data is sampled.

The extracted length data is loaded to one of a pair of counters (search counters) 56 and 58 provided at the subsequent stage of the counter control means 54. Immediately after the sector head pulse STP is output, the output port Oa is always selected. On the other hand, in the case of the extraction pulse EP based on the second sync pulse SP, only when the level of the determination pulse JP is at the high level “H”,
The second output port Ob is selected.

Output ports Oa and Ob output length data, and also output load pulses LD and load start pulses Pa and Pb. Therefore, the first and second search counters 56 and 58 receive the load pulse LD, and at the timing when the start pulses Pa and Pb are obtained, data (6 words of the sync code added to the corresponding length data). (Hereinafter simply referred to as length data).

Each of the counters 56 and 58 is configured as a subtraction counter, and the loaded length data is supplied to the clock CK.
Are decremented one by one in synchronization with (FIG. 4F as an example). When the length data becomes "00", check pulses CPa and CPb (G in the figure) are output from each. The check pulses CPa and CPb are output from the sync determining means 6.
0 to determine whether the detected sync pulse is a true sync pulse or a pseudo sync pulse based on the relationship between these and the sync pulse SP.

That is, as shown in FIG. 4, the timing at which the check pulse CPa based on the first sync pulse SP is obtained is determined by decrementing the length data by one of the last code (80) of the next sync code.
Since the detected sync code is a correct sync code, the sync pulse SP should be present at the timing when the check pulse CPa is obtained.

From this, when the sync pulse SP has not been obtained, it can be determined that the first sync code is not the original sync code. That is, it can be determined that the code is a pseudo sync code. Therefore, a sync determination is performed using the check pulse CPa and the sync pulse SP. When the sync pulse SP is present, the level is inverted to the low level as the determination pulse JPa, and otherwise, the high level is maintained.

Similarly, a sync determination is performed by the check pulse CPb and the sync pulse SP. When the sync pulse SP exists, the level of the determination pulse JPb is inverted to a low level, and otherwise the high level is maintained. Become. The determination pulses JPa and JPb are logically ANDed by an AND circuit 62, and the final output of the determination pulse JP is supplied to the counter control means 54 and the address generation means 64, respectively.

The data sequence of the reproduced digital signal is supplied to the address generating means 64. If the data is the original sync code, the macro block header and the length data at the timing when the sync pulse SP is obtained are fetched. With this, the address of the macroblock header and the length content of the macroblock are memorized. The length up to the next length insertion position is calculated from the stored length data.

Immediately before the detected subsequent length data (# 3, # 4,...), Continuous macroblock headers ({MB-Y (00), MB-X (O2)}, {MB -Y (00), MB-X (0
3)},...) Are generated based on the stored macroblock header, and are inserted into corresponding positions. After that, the sync adding circuit 40 shown in FIG. 2 adds one sync bit in place of the sync code.

If the code is a pseudo sync code, the address generation is prevented by the sync determination pulse JP, so that the above-described macro block address generation processing is not performed.

Therefore, according to the configuration shown in FIG. 3, the operation shown in FIG. 4 is performed in the normal inverse conversion process. The first sync code SC # 1 from which the sector pulse STP is obtained is detected, and the sync pulse SP is obtained (FIGS. 4B, 4C, and 4C).
D). A sampling pulse EP having a width of 2 clocks is formed from the sync pulse SP. At this time, the sync judgment pulse JP
Is a high level, and is the first sync pulse SP after the sector pulse STP is obtained. At this time, the first output port Oa is selected by the counter control means 54, and the length data # 1 is changed to the first output port Oa. Is loaded into the search counter 56. Then, in synchronization with the start pulse Pa (FIG. 4K), the first search counter 56 starts decrementing (FIG. 4F).

During the decrement, the second sync code S
C # 2 arrives. At this time, since the first counter 56 is counting, the selected state of the first output port Oa is maintained in this case as well.

When the decrement is completed and the count output becomes "00", the first check pulse CPa is output and the second sync pulse SP is obtained.
Is inverted to a low level (H in the figure). The second sync determination pulse JPb remains at the high level because the second check pulse CPb cannot be obtained, whereby the determination pulse JP is inverted to start the address generation processing (I and J in FIG. 3). . Judgment pulse JP
Becomes low level, the state of the counter control means 54 is reset.

The above is an example of the inverse conversion processing in the normal state. When the pseudo sync code is mixed in the reproduction data string, the operation is as shown in FIG. FIG. 5 shows a case where a pseudo sync code DSC # is mixed at the beginning of a sector.

Therefore, the reproduced data string is as shown in FIG. 5B, and the pseudo sync code is located first. After the pseudo sync code, a dummy macro block header (MB-
Y, MB-X) and dummy length data # 'follow.
Both the header data and the length data are random data. The pseudo sync code is followed by the correct sync code.

As a result, when the last word (80) of the pseudo sync code is detected after the sector pulse STP is obtained, a sync pulse SP is generated (FIGS. 5B, 5C and 5C).
D). As a result, a sampling pulse EPa is formed,
As a result, dummy length data # 'is fetched and loaded into the first search counter 56 (see FIG.
F).

The load data is decremented at the timing of the start pulse Pa (F and M in the figure), but the original sync code SC # 1 (first sync code) is detected in the middle as shown in the figure. As a result, a second sync pulse SP is generated (FIG. D), and based on this, a sampling pulse EPb (FIG. I) is generated.

The judgment pulse JP (JPa) as shown in FIG.
Is high level, the counter control means 54 selects the second output port Ob, so that the length data # 1 extracted by the extraction pulse EPb is output to the second output port Ob.
Is loaded into the second search counter 58 through the output port Ob of FIG. Then, the decrement operation is started by the start pulse Pb (J, N in the same figure).

When the count output of the second search counter 58 becomes "00", a second check pulse CPb is obtained (O in the figure). This timing is the timing immediately after the last word (80) of the next sync code SC # 2. Therefore, the second sync code SC # 2 is detected and the sync pulse SP is output (D in FIG. 4). When the pulses CPb and SP are aligned, the second sync determination pulse J
Pb is inverted to a low level (K in the figure), and in conjunction with this, the determination pulse JP also goes to a low level (L in the figure).

Therefore, the second sync code SC # 2
Is detected, the address generating means 64 starts operating.

On the other hand, focusing on the pseudo sync code DSC #, the random dummy length data # 'is decremented by, for example, 2 by decrementing the random length data #' as shown in FIG. 5F.
During the first sync code, the first search counter 56
Is "00".

Then, at this time, the check pulse CP
Since a is output, the sync determination means 60 determines the level of the sync pulse SP (D in the figure) when the check pulse CPa is obtained. Since the sync pulse SP does not detect the sync code immediately before it and remains at the high level, even if the check pulse CPa is obtained, the determination pulse JPa is not inverted to the low level (see FIG.
H). Therefore, the determination pulse JP also keeps the high level state, and the address generating means 64 does not operate even if the pseudo sync code is detected after all.

With the above processing, erroneous reproduction processing by the pseudo sync code can be avoided. Pseudo sync code first and 2
The result is the same whether the synchronization code is generated between the second sync codes SC # 1 and SC # 2 or if the pseudo sync code is generated at an arbitrary timing after the second sync code. This is because the sync pulse SP is not detected at the timing when the dummy length data has been decremented.

[0050]

As described above, according to the present invention, when the synchronization bit included in the data stream exceeds the data transfer unit length of the disk-shaped recording medium, only a plurality of specific synchronization bits are used, and Is converted to a specific sync code, recorded, and processed based on the reproduced sync code so that a synchronization bit can be restored and inserted.

According to this, it is possible to convert to a signal form suitable for a disk-shaped recording medium without increasing the entire data length. Further, even if a block-like write error occurs on the disk-shaped recording medium due to this conversion process and a pseudo sync code occurs, the pseudo sync code can be accurately discriminated from the original sync code and the pseudo sync code can be eliminated. It has features such as the elimination of playback processing.

Therefore, the present invention is extremely suitable for application to a recording / reproducing system for recording image data on a magneto-optical disk or the like which is a disk-shaped recording medium for an AV server and which performs a pre-erase process.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an embodiment of a disk recording / reproducing apparatus to which a reproduced signal processing apparatus according to the present invention is applied.

FIG. 2 is a system diagram of a main part showing one embodiment of a reproduction signal processing device according to the present invention.

FIG. 3 is a system diagram of a main part showing an embodiment of an inverse conversion circuit used in the reproduction signal processing device.

FIG. 4 is a diagram illustrating an operation during a normal operation.

FIG. 5 is an operation explanatory diagram when a pseudo sync code is detected.

FIG. 6 is an explanatory diagram of a macro block.

FIG. 7 is a diagram showing an example of a data stream in the SDDI format and a data stream after recording.

[Explanation of symbols]

12: disk, 20: recording signal processing device, 3
0 ... reproduction signal processing device, 40 ... sync addition circuit, 50 ... inversion circuit, 52 ... sync detection means, 54 ... counter control means, 56, 58 ... search counter, 60 ... sync determination means, 64 ...
Address generation means

Claims (8)

[Claims] 1. A data stream to be recorded contains a synchronization bit for block detection for each unit block, and a digital signal exceeding the unit length of data transfer of a recording medium is recorded on the recording medium by the synchronization bit. In doing so, for each sector including the unit block, only a predetermined number of the synchronization bits provided at the head of the sector are converted into a specific sync code and have the same unit length as the data transfer. And recording the digital signal including the sync code of (1) on the recording medium. 2. The unit block is configured as a macro block for video data, and is a digital signal obtained by adding the synchronization bit to macro block data inserted immediately before a macro block header for identifying the macro block. 2. The method for recording a digital signal according to claim 1, wherein: 3. The method according to claim 1, wherein at least the first and second synchronization bits inserted in the sector are converted into a sync code of 6 words, and the third and subsequent synchronization bits are recorded in a deleted state. 2. The method for recording a digital signal according to claim 1, wherein: 4. The apparatus according to claim 3, wherein, together with the deletion of the synchronization bit, a macroblock header inserted for each macroblock from which the synchronization bit has been deleted is also recorded after being deleted at the same time. Digital signal recording method. 5. The digital signal recording method according to claim 1, wherein said recording medium is a disk-shaped recording medium on which pre-erase processing is performed. 6. A digital signal of an original data stream, wherein a reproduced digital signal is supplied to a data reverse conversion means, and a synchronization bit is restored from the reproduced digital signal converted to a data transfer unit length to obtain a digital signal of an original data stream. Playback signal processing device. 7. The reverse conversion means includes: a detection means for detecting a sync code from a reproduced digital signal; a first search counter for counting macroblock length data obtained based on a sync code detected first;
Second counting of macroblock length data obtained based on a sync code following the first sync code
Based on the first and second check pulses obtained from the respective counters and the sync pulse.
A sync determining means for generating the determination pulse of the above, and a sync generating means for capturing the reproduced digital signal by AND output of these determination pulses, generating a macroblock header and converting it into a data stream before recording, 7. The reproduction signal processing device according to claim 6, wherein the reproduced pseudo-sync is excluded by the sync determination means. 8. The level of the first determination pulse is inverted when the sync pulse is present at the timing when the first check pulse is obtained, and the level of the second determination pulse is also inverted. 7. The reproduction signal processing apparatus according to claim 6, wherein when the sync pulse is present at the obtained timing, the level is inverted, and the determination pulse is not inverted depending on the pseudo sync.