JPH103751A - Playback device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable reproduction of accurate data even at the time of a high speed search by improving the configuration of a PLL circuit and generating a clock corresponding to only a frequency of the reproducing data by a head having a prescribed azimuth. SOLUTION: A digital data is reproduced by tracing a magnetic tape 101 with plus and minus azimuth heads 105 and 107, and is outputted via amplifiers 109 and 111 and equalizers (EQ) 113 and 115 to the PLL circuits 117 and 119. Clocks synchronized with the reproducing data in phase from the heads 105 and 107 are generated by the PLL circuits 117 and 119, and are outputted to a track memory 129 and subcode ID detecting circuits 125 and 127 respectively. A reference signal corresponding to a set frequency from a reference signal oscillator (OSC) 121 to be controlled by a CPU 123 is inputted to these PLL circuits. A PLL oscillation frequency at the time when an envelope of the reproducing data is obtained is set by this reference signal, and a PLL lock range is set with this initial oscillation frequency as the center.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus, and more particularly, to an apparatus for reproducing a clock from a digital signal reproduced from a recording medium.

[0002]

2. Description of the Related Art It has been known that a device for transmitting (recording / reproducing) data at high speed, such as a digital VTR, uses a phase locked loop (hereinafter, PLL) when extracting a clock from a received data sequence. I have.

FIG. 8 shows a configuration of such a PLL circuit.

In FIG. 8, data reproduced from a tape (not shown) is input to a phase comparator 301, and a phase difference from a clock output from a voltage controlled oscillator (hereinafter, VCO) 303 is detected. The output of the phase comparator 301 is input to the VCO 303 via the loop filter 302, and outputs a signal having a frequency corresponding to the output voltage of the loop filter as a clock.

That is, uneven rotation of a rotary head (not shown),
When the phase of the reproduced digital data fluctuates due to expansion or contraction of the tape, the phase difference from the clock is detected by the phase comparator 301 and fed back to the VCO 303 via the loop filter 302 to control the oscillation frequency. Can be generated following the phase fluctuation of the clock.

[0006]

Here, consider the case where high-speed reproduction, so-called picture search, is performed.

In a digital VTR, guard bandless recording is usually performed by a plurality of heads having different azimuth angles in order to perform high-density recording.

Therefore, although this does not matter during normal reproduction, the speed component in the direction intersecting azimuth during picture search differs depending on the azimuth angle. The frequency of the data reproduced from is shifted away from the frequency to one higher and the other to the lower frequency in accordance with the search speed.

FIG. 7 shows this state.

In the figure, the horizontal axis represents the search speed, and the vertical axis represents the frequency of data reproduced from two heads having different azimuth angles.

For example, at 250 × speed, the frequency of the reproduction data is −43 in the case where the minus azimuth head is used for normal reproduction.
%, And the plus azimuth head becomes -43% of that during normal reproduction.

Usually, a search while outputting an image, that is, a so-called picture search, is about several times.
Even in the double search, the difference in the frequency of the reproduced data due to azimuth is small, and falls within the PLL lock range.

However, when fast-forwarding and rewinding while searching for an index indicating an index or a still image or the like (hereinafter referred to as an index search), the search speed is increased by 200 times and 30 times.
If it is set to 0 times, the difference in the frequency of the reproduced data due to azimuth becomes remarkable, and furthermore, the fluctuation of the frequency of the reproduced data due to the search is added, and the lock range of the PLL is exceeded.

Therefore, an accurate clock cannot be generated during a high-speed search, and good reproduced data cannot be obtained.

Further, only low-speed search can be performed to obtain good reproduction data.

An object of the present invention is to solve the above-mentioned problems and to provide an apparatus capable of accurately reproducing data even in the case of a high-speed search or the like.

[0017]

SUMMARY OF THE INVENTION In order to solve the conventional problems and achieve the above object, the present invention traces a recording medium by using a plurality of rotating heads having different azimuth angles to transfer data. Reproducing means for reproducing, generating means for generating a clock phase-synchronized with the reproduced data, and generating the clock having a frequency corresponding only to the frequency of data reproduced from a predetermined rotary head among the plurality of rotary heads Control means for controlling the generating operation of the generating means.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail.

FIG. 1 shows a digital VTR to which the present invention is applied.
FIG. 2 is a diagram showing a configuration of a reproduction system of FIG.

In FIG. 1, a magnetic tape 101 is traced by a minus azimuth head 105 and a plus azimuth head 107 mounted close to a rotating drum 103 to reproduce digital data.
And output to the equalizers 117 and 119. The equalizers 117 and 119 compensate for data deterioration in the magnetic recording / reproducing system and output the data to the PLL circuits 117 and 119.
The PLL circuits 117 and 119 generate clocks that are phase-synchronized with the reproduction data from the heads 105 and 107, respectively, and output the clocks to the track memory 129 and the subcode ID detection circuits 125 and 127, as described later.

The PLLs 117 and 119 include:
A reference signal corresponding to a set frequency is input from a reference signal generator 121 controlled by the CPU 123. With this reference signal, the oscillation frequency of the PLL when the envelope of the reproduction data is obtained is set, and the PLL lock range is set around this initial oscillation frequency.

Subcode ID detection circuits 125 and 127
Extracts the subcode and the ID of the subcode in the reproduction data, and outputs the subcode data to the switches 131 and 133. ID and ID for error detection of ID
The parity data is transmitted to the ID parity check circuits 135 and 137.
Output to

The ID parity check circuits 125 and 137
It is checked whether there is an error in the ID and the ID parity, and only when there is no error, the switches 131 and 133 are closed to
The D data is output to the CPU 123.

Also, the track memory 129 stores the PLL1
Reproduced data is stored using clocks output from clocks 17 and 119, and the stored data is rearranged in an order suitable for a subsequent processing circuit and output to the ECC circuit 139.

The ECC circuit 139 corrects an error in the reproduced data using the parity data added at the time of recording,
Output to the VLD circuit 141. The VLD circuit 141 decodes the variable-length encoded reproduction data, and
43. The inverse DCT circuit 143 performs an inverse DCT process on the decoded data and outputs the result to the memory 145. The memory 145 rearranges the reproduced data in the raster scan order, and outputs the data through the D / A converter 147 and the terminal 149.

On the other hand, an FG detector 153 and a PG detector 155 are attached to the drum motor 151, and a DFG pulse and a DPG pulse are generated from each of the detectors.
Output to U123. The CPU 123 uses these DFGs
And the control voltage of the drum motor is calculated by a known method using the DPG, and feedback control is performed via the D / A converter 157 and the motor driver 159 so that the drum motor 151 rotates at the normal rotation speed and phase. .

The magnetic tape 101 is a capstan 1
It is conveyed by a capstan motor 165 between the pinch roller 163 and the pinch roller 163. Capstan motor 1
An FG detection circuit 167 is provided at 65, and a CFG pulse is output to the CPU 123. The CPU 123 uses this CF
The control voltage of the capstan motor is calculated by a known method using G, and the D / A converter 169 and the motor driver 17 are calculated.
The feedback control is performed so that the capstan motor 165 rotates at a regular rotation speed via the control unit 1.

Next, the operation of the PLLs 117 and 119 will be described.

FIG. 2 is a diagram showing a configuration of the PLLs 117 and 119.

In the figure, reproduced data output from the equalizers 113 and 115 is supplied from a terminal 201 to a phase comparator 2.
03 and one terminal of the register 205.

The other terminal of the phase comparator 203 is supplied with a clock output from a VCO 207 described later.

The phase comparator 203 generates a signal having a voltage proportional to the phase difference between these two signals, and outputs the signal to the loop filter 209. The loop filter 209 includes an amplifier 211, resistors 213, 215, a capacitor 217,
Diodes 219 and 2 that limit output to ± 0.7V
21 and suppresses the high-frequency component of the input signal and outputs the same to one input of the adder 225. Note that an analog switch 223 is connected between the input and output terminals of the amplifier 211.

On the other hand, a reference signal having a frequency substantially equal to the frequency of the reproduced data is input to the input terminal 227 from the above-described reference signal generator 121, and is input to a frequency phase comparator (hereinafter referred to as FP).
C) Output to 229. The output of the VCO 207 is added to the other input of the FPC 229, the frequency and the phase are compared, and the comparison result is output to the analog switch 231. An example of the FPC 229 is Motorola MC12040.

The analog switch 231 is closed at a later-described timing. When the analog switch 231 is closed, the output of the FPC 229 is output to the loop filter 245. The loop filter 245 includes an amplifier 233 and a resistor 23.
5, 237 and a capacitor 239, and outputs an output signal as the other input of the adder 225.

The adder 225 adds the two input signals and outputs the result to the VCO 207.

The PLL circuit has a mode (mode A) for adjusting the phase to the reproduction data input to the terminal 201,
There is a mode (mode B) for adjusting the frequency and the phase to the reference signal input to the terminal 227. The mode becomes mode A when the analog switch 223 and the analog switch 231 are open, and the state when the analog switch 223 and the analog switch 231 are closed. Mode B.

In the mode A, the phase error between the reproduced data input to the terminal 201 and the VCO 207 is input to the loop filter 208 and averaged by the loop filter 209, and the phase error between the reproduced data and the VCO 207 is output to the VCO 207. The control signal having such a canceling voltage is VC
This constitutes a PLL circuit to be input to O607. At this time, since the analog switch 231 is open, the output of the amplifier 233 maintains a constant voltage.

In the mode B, the reference signal input from the terminal 227 and the output clock of the VCO 207 are compared by the FPC 229, and a signal indicating the error is input to the loop filter 245. Then, in the loop filter 245, the output signal of the FPC 229 is averaged, and a signal having a voltage that reduces the error is output to the VCO.
This constitutes a feedback loop that is input to the 607. At this time, since the analog switch 223 is closed, the output of the amplifier 209 is kept at zero.

In such a configuration, during normal reproduction,
The output from the minus azimuth head 105 amplified by the reproduction amplifier 109 is supplied to a tracking control circuit (not shown), and the capstan motor 165 is controlled by using a pilot signal component obtained from the reproduction data.
1. A track formed on 1 accurately traces a head having the same azimuth.

At the time of the picture search, the capstan motor 165 is rotated at the number of revolutions corresponding to the picture search, and the reference signal generating circuit 121 outputs the intermediate frequency between the two azimuths indicated by the dashed line in FIG. Is supplied as a reference signal, whereby the frequency of the clock falls within the PLL lock range.

At the time of the index search, the capstan motor 165 is rotated at the number of revolutions corresponding to the index search. However, when the speed becomes 100 times or 200 times, the frequency of the data reproduced from the plus azimuth head and The frequency of the data reproduced from the minus azimuth head differs by several percent, and when the fluctuation of the frequency of the reproduced data by the search is taken into account, the lock range of the PLL is exceeded.
By outputting a signal having the frequency of the minus azimuth reproduction data shown by the solid line in FIG. 7 as a reference signal, a clock accurately phase-synchronized with the data reproduced from the minus azimuth head is obtained, and the data is accurately reproduced. Making it possible.

Hereinafter, the control operation of the CPU 123 during the index search according to the present embodiment will be described with reference to the flowchart of FIG.

First, when a start of an index search is instructed by an operation switch (not shown), the capstan motor 165 is driven to rotate at a rotation speed corresponding to the index search (step S1), and a reference signal is generated. A control signal is output to the detector 121 so as to generate a signal having a frequency corresponding to the minus azimuth head as described above (step S2).

Next, using the reproduced clock obtained from the PLL 117 as described above, ID data is extracted from the reproduced data by the subcode ID detection circuit to detect whether or not the ID has been updated (step S3). ). Here, since the subcode ID detection circuit 125 processes the reproduced data from the minus azimuth head 105, the subcode from the subcode ID detection circuit 125 is often updated.

When the subcode ID is updated, the index flag in the updated subcode is checked. If the flag is set, the index check flag is set, and the capstan motor 165 is controlled to control the tape 10.
1 is stopped.

FIG. 4 shows reproduction envelopes from the respective heads and the PLLs 117 and 1 in the index search according to the present embodiment.
The state of the input voltage of the VCO in 19 is shown.

FIG. 4A shows a reproduction envelope of a minus azimuth head, and FIG. 4B shows a VC in the PLL 117.
Indicates the input voltage of O.

As shown in the figure, while the head 105 is tracing the tape 101, the PLL 117 is in the mode A, and generates a phase-locked clock of the reproduced data. In other periods, the mode is set to mode B,
Generate a clock according to the reference signal.

In this embodiment, since the frequency of the output signal of the reference signal generator 121 is adjusted to the frequency of the data reproduced by the minus azimuth head, the control voltage of the VCO is adjusted to the lock range where the envelope is obtained. Maintained near the center.

FIG. 4C shows the reproduction envelope of the plus head, and FIG. 4D shows the input voltage of the VCO in the PLL 119.

In the case of the plus azimuth head, since the frequency of the reference signal from the reference signal generator 121 is lower than the frequency of the reproduced data, the input voltage of the VCO is set such that the PLL is at the end of the lock range where the envelope is obtained. At or off. This is the operation as designed, and is a result of emphasizing the minus azimuth head.

As described above, in the present embodiment, the frequency of the reference signal output to the PLL is set to the frequency of the data reproduced from the minus azimuth head during the ultra-high speed search such as the index search. Can also generate a clock accurately phase-synchronized with the reproduced data from the minus azimuth head, and can reproduce the data accurately.

In the above-described embodiment, the drum motor 15
The index search was performed while the rotation speed of the drum motor 151 was normal, but the rotation speed of the drum motor 151 was increased in the forward search and decreased in the reverse search to reduce the reproduction data of the minus azimuth head. Can be considered to make the frequency of the normal reproduction equal to the frequency at the time of normal reproduction. Since this method changes the number of revolutions of the drum, the mode transition takes some time, but the PLLs 117 and 119 can be used with the same characteristics as in normal reproduction.

FIG. 5 shows the rotation speed of the drum motor 151 to be set with respect to the search speed and the frequency shift reproduced from each head.

As shown in the flowchart, by controlling the number of revolutions of the drum motor 151 by the CPU 123, the frequency of the reproduction data of the minus azimuth head can be made equal to the frequency at the time of normal reproduction.

FIG. 6 shows a flow of the operation of the CPU 123 for such control.

In FIG. 6, the difference from the operation shown in FIG. 3 is that after step S1, in step S9,
The purpose is to control the drum motor 151 so that the frequency of the reproduction data of the minus azimuth head becomes equal to the frequency at the time of normal reproduction at the search speed.

The index IDs required for the index search are recorded on both the plus azimuth track and the minus azimuth track, and there is no problem if the ID is extracted from only the minus azimuth track.

Further, in the above-described embodiment, the description has been given of the case of the forward search. However, also in the case of the reverse search, the frequency of the reproduction data of the minus azimuth head is similarly used as the frequency of the reference signal of the PLL. Similar effects can be obtained.

In the above-described embodiment, the frequency of the reference signal is adjusted to the frequency of the reproduction data of the minus azimuth head. However, the present invention is not limited to this, and the frequency of the reproduction data from a predetermined head among different azimuth heads is used. It is also possible to control the PLL with a control signal having the following.

[0061]

As is apparent from the above description, according to the present invention, a clock corresponding to only the frequency of reproduced data of a head having a predetermined azimuth angle is generated. Even if the azimuth angle greatly varies, a clock that is at least phase-synchronized with data reproduced from a head having a predetermined azimuth can be generated, thereby preventing all data from becoming unreproducible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a PLL circuit in FIG. 1;

FIG. 3 is a flowchart for explaining the operation of the apparatus of FIG. 1;

FIG. 4 is a diagram for explaining the operation of the circuit of FIG. 2;

FIG. 5 is a diagram for explaining another operation of the device of FIG. 1;

FIG. 6 is a flowchart for explaining another operation of the apparatus of FIG. 1;

FIG. 7 is a view for explaining the operation of the apparatus of FIG. 1;

FIG. 8 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 117 PLL 123 CPU

Claims (7)

[Claims] 1. A reproducing means for tracing a recording medium by using a plurality of rotating heads having different azimuth angles to reproduce data, a generating means for generating a clock phase-synchronized with the reproduced data, A reproducing unit comprising: a control unit that controls a generating operation of the generating unit so as to generate the clock having a frequency corresponding to only a frequency of data reproduced by a predetermined rotary head among the rotary heads. 2. The apparatus according to claim 1, wherein: the first mode in which the recording medium is conveyed at substantially the same speed as when recording the data to reproduce the data; 2. The reproducing apparatus according to claim 1, further comprising: a second mode for reproducing the data by conveying the data at different speeds, wherein the control unit performs the control operation in the second mode. 3. 3. A first loop for generating a clock phase-synchronized with the reproduced data; and a clock for generating a clock having a frequency corresponding to the frequency of data reproduced from the predetermined head. The playback device according to claim 1, further comprising a second loop. 4. The first loop includes a phase comparator for detecting a phase difference between the reproduced data and the clock, a loop filter for filtering an output of the phase comparator, and an output of the loop filter. The reproducing apparatus according to claim 3, further comprising: an oscillator that generates a signal having a frequency corresponding to the clock. 5. The control means according to claim 2, wherein the control signal is a control signal having a frequency corresponding to a frequency of reproduction data of the predetermined head.
A second loop, a phase frequency detector for detecting a phase difference and a frequency error between the clock and the control signal,
The filter according to claim 4, further comprising: a filter that filters an output of the phase frequency detector, and an adder that adds an output of the filter and an output of the loop filter and outputs the result to the oscillator. Playback device. 6. The reproducing apparatus according to claim 3, wherein the first loop and the second loop operate during periods different from each other. 7. A rotary phase generating means for generating a phase detection signal synchronized with a rotation phase of the rotary head, wherein the first loop and the second loop operate in accordance with the phase detection signal. The playback device according to claim 6, wherein: