JPH1041443A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH1041443A
JPH1041443A JP18898196A JP18898196A JPH1041443A JP H1041443 A JPH1041443 A JP H1041443A JP 18898196 A JP18898196 A JP 18898196A JP 18898196 A JP18898196 A JP 18898196A JP H1041443 A JPH1041443 A JP H1041443A
Authority
JP
Japan
Prior art keywords
copper post
thin film
post electrode
disk
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18898196A
Other languages
Japanese (ja)
Inventor
Kazushiro Oishi
和城 大石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Priority to JP18898196A priority Critical patent/JPH1041443A/en
Publication of JPH1041443A publication Critical patent/JPH1041443A/en
Pending legal-status Critical Current

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the thermal contact resistance of a Cu post electrode with a Mo disk. SOLUTION: This device has a flat pressure-welding structure, and is constituted so that sandwiching a silicon element between Cu post electrodes on both its surfaces via respective Mo disks, a pressure is applied across the Cu post electrodes to form electric junctions. In this case, both on a surface 61 of the Cu post electrode and on a surface portion 21 of the Mo disk, such thin films 41 , 42 as Ag and Al ones are disposed respectively by sputtering, depositing, plating and the like. Even when irregularities are present both on the surface 61 of Cu and on the surface 21 of Mo, there is generated no clearance both between the surface 61 and the thin film 41 and between the surface 21 and the thin film 42 . Also, since on a pressure-welding surface (b), the pressure welding of such soft thin film surface as Al and Ag ones to each other is performed, there is generated no clearance on the surface b, either. Therefore, the thermal contact resistance of the Cu post electrode with the Mo disk is made small.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、平型圧接構造の大
電力用半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-power semiconductor device having a flat pressure contact structure.

【0002】[0002]

【従来の技術】図3に電力用半導体装置の平型圧接構造
を示す。同図において、1はシリコン素子、6は銅カソ
ードポスト電極、7は銅アノードポスト電極、8はゲー
ト電極部である。
2. Description of the Related Art FIG. 3 shows a flat type pressure contact structure of a power semiconductor device. In the figure, 1 is a silicon element, 6 is a copper cathode post electrode, 7 is a copper anode post electrode, and 8 is a gate electrode portion.

【0003】銅ポスト電極6,7とセラミックケース1
1でケースを構成している。
[0003] Copper post electrodes 6 and 7 and ceramic case 1
1 constitutes a case.

【0004】一般に、不純物拡散,電極パターン等の形
成を行ったシリコン(Si)素子1の両面に、外部引出
電極及び高熱伝導・応力緩和材としての役割を果すモリ
ブデン(Mo)ディスク2,3を挟み、銅ポスト電極
6,7の両側から圧力をかけて密着させる。この時、銅
とモリブデンとの熱膨張差による応力等を緩和するため
に銀箔4,5を介在させる。
In general, molybdenum (Mo) disks 2 and 3 serving as an external lead electrode and a high heat conduction / stress relieving material are provided on both surfaces of a silicon (Si) element 1 on which impurity diffusion, electrode pattern formation, etc. have been performed. Pressure is applied from both sides of the copper post electrodes 6 and 7 to make them adhere to each other. At this time, silver foils 4 and 5 are interposed in order to reduce stress and the like due to a difference in thermal expansion between copper and molybdenum.

【0005】図4は上記半導体装置の実動作状態におけ
る構造を示す。半導体パッケージ内部は、Si素子1を
銅ポスト電極6,7及びMoディスク2,3で挟んだ構
造である。この半導体パッケージの両側にヒートシンク
(冷却フイン)17,18を取り付けている。
FIG. 4 shows a structure of the semiconductor device in an actual operation state. The inside of the semiconductor package has a structure in which the Si element 1 is sandwiched between copper post electrodes 6 and 7 and Mo disks 2 and 3. Heat sinks (cooling fins) 17 and 18 are attached to both sides of the semiconductor package.

【0006】このヒートシンク17,18は実動作状態
においてSi素子1から発生した熱を外部(周囲)へ逃
がす役割を持つ、また、このヒートシンクはアルミ,銅
等の導電性のあるもので作られ、単に熱を逃がすためで
なく、電極としても使用する。
The heat sinks 17 and 18 have a role of releasing heat generated from the Si element 1 to the outside (surroundings) in an actual operation state. The heat sinks are made of conductive material such as aluminum or copper. It is used not only for releasing heat but also as an electrode.

【0007】[0007]

【発明が解決しようとする課題】図5は素子に電流が流
れることで発生した熱が周囲温度まで伝わる状態を放熱
等価回路として表したものである。ここで、 Tj:素子接合温度、Tc:ケース(Cuポスト電極)
温度、Tf:フイン温度、Ta:周囲温度 Rth(Si)、Rth(Mo)、Rth(Cu)、R
th(Fin):構成部品自身が持つ熱抵抗 Rth(Si−Mo)、Rth(Mo−Cu)、Rth
(Cu−Fin):構成部品間の接触熱抵抗 Rth(Fin−a):フインから周囲の大気に熱が逃
げる時の熱抵抗 熱抵抗Rth…は熱の伝わり難さのことでありこの値が
大きいほど冷却率が悪く、過剰に冷却しないと素子の温
度が定格以上に上昇し破壊に至る。
FIG. 5 shows, as a heat dissipation equivalent circuit, a state in which heat generated by current flowing through the element is transmitted to the ambient temperature. Here, Tj: element junction temperature, Tc: case (Cu post electrode)
Temperature, Tf: Fin temperature, Ta: Ambient temperature Rth (Si), Rth (Mo), Rth (Cu), R
th (Fin): thermal resistance of the component itself Rth (Si-Mo), Rth (Mo-Cu), Rth
(Cu-Fin): thermal contact resistance between components Rth (Fin-a): thermal resistance when heat escapes from the fin to the surrounding air Thermal resistance Rth... The cooling rate is worse as the value is larger, and if not cooled excessively, the temperature of the element rises above the rating, leading to destruction.

【0008】半導体パッケージ内のTj(接合温度)〜
Tc(ケース温度)までの熱抵抗Rth(j−c)につ
いては、この半導体パッケージ材料・構造によって決ま
る。次にTc〜Tfinまでの熱抵抗Rth(c−fi
n)について半導体パッケージと冷却フインとの間に発
生する熱抵抗であり、取り付け方によってはこの値が非
常に大きくなり、熱の逃げが妨げられる場合もある。
[0008] Tj (junction temperature) in the semiconductor package
The thermal resistance Rth (j−c) up to Tc (case temperature) is determined by the semiconductor package material and structure. Next, the thermal resistance Rth (c-fi) from Tc to Tfin
n) is the thermal resistance generated between the semiconductor package and the cooling fin, and this value becomes extremely large depending on the mounting method, so that the heat may be prevented from escaping.

【0009】半導体素子が大口径化・大容量化になるに
つれ素子から発生する熱損失は増大する。従って、半導
体ケースが持つ熱抵抗を下げることは非常に重大な問題
なる。
As semiconductor devices have become larger in diameter and larger in capacity, heat loss generated from the devices increases. Therefore, reducing the thermal resistance of the semiconductor case is a very serious problem.

【0010】現在のケースが持つ熱抵抗値を、構成部品
毎に占めている割合を計算した結果の一例を図6に示
す。この例では構成材料のうちMoディスクと銅ポスト
電極に介在している銀箔は省略したが、このMoディス
ク銅ポストと電極との間に発生する接触抵抗の占める割
合が一番大きく、次いでMoディスク自身、電極とMo
ディスクとの間の接触熱抵抗の割合が大きい。Si素子
自身は素子性能で厚み等が定められるのでこの値は不動
のものである。
FIG. 6 shows an example of the result of calculating the ratio of the thermal resistance of the current case to each component. In this example, the silver foil interposed between the Mo disk and the copper post electrode among the constituent materials was omitted, but the contact resistance generated between the Mo disk copper post and the electrode accounted for the largest proportion, followed by the Mo disk Own electrode and Mo
The ratio of the contact thermal resistance with the disk is large. Since the thickness and the like of the Si element itself are determined by the element performance, this value is immovable.

【0011】[0011]

【表1】 [Table 1]

【0012】表1にMoディスクと銅ポスト電極に介在
している銀箔の有無による熱抵抗への影響を計算した結
果を示す。表中、モデル〔1〕は銀箔が無い状態であ
る。Moディスクと銅ポスト電極との間の接触熱抵抗は
銅材料表面の硬さ、粗さに影響されるが、銀箔を入れた
モデル〔2〕では銅の表面には影響されず、約700%
程度の熱抵抗の低減ができることが得られている。
Table 1 shows the results of calculating the effect on the thermal resistance due to the presence or absence of the silver foil interposed between the Mo disk and the copper post electrode. In the table, model [1] has no silver foil. The contact thermal resistance between the Mo disk and the copper post electrode is affected by the hardness and roughness of the copper material surface, but is not affected by the copper surface in the model [2] including the silver foil, and is approximately 700%
It has been obtained that the thermal resistance can be reduced to a certain degree.

【0013】しかし現状の工程で用いられているよう
に、単純に銀箔を挟むだけでは図7の矢印gで示すよう
に銅、モリブデン表面に存在するミクロな隙間を埋める
ことができない。実際に銅表面の仕上げ精度は(▽▽
▽)であり、約6μmの凹凸がある。実際の銅ポスト電
極は、主にニッケルメッキを用いて表面を被覆(〜5μ
m程度)しており、表面の凹凸は小さくなっていると思
われるが、ニッケル材そのものが硬い材質であり、銀箔
との密着性は悪い。
However, as is used in the current process, it is not possible to fill the micro gaps existing on the copper and molybdenum surfaces as indicated by the arrow g in FIG. 7 simply by sandwiching the silver foil. Actually, the finishing accuracy of the copper surface is (▽▽
▽), with irregularities of about 6 μm. The actual copper post electrode covers the surface mainly using nickel plating (~ 5μ).
m), and the surface irregularities are thought to be small, but the nickel material itself is a hard material and has poor adhesion to silver foil.

【0014】モリブデンディスク表面は鏡面仕上げであ
るが、1μm程度以下の凹凸があるものと考えられる。
また製造途中で表面に傷が付く可能性もあり、かなり隙
間が生じていると考えられる。銀箔は本来柔らかい材質
であり、変形によりある程度の隙間を埋めることができ
るが、完全に密着しない。
Although the surface of the molybdenum disk is mirror-finished, it is considered that the surface has irregularities of about 1 μm or less.
Further, the surface may be damaged during the production, and it is considered that a considerable gap is generated. Silver foil is a soft material by nature and can fill some gaps by deformation, but does not adhere completely.

【0015】接触熱抵抗の増大は以上で説明したミクロ
な隙間があることによって熱の伝わりが悪くなり、結果
的に熱抵抗の増大につながる。
[0015] The increase in contact thermal resistance leads to poor heat transfer due to the presence of the micro gaps described above, resulting in an increase in thermal resistance.

【0016】本発明は、従来のこのような問題点に鑑み
てなされたものであり、その目的とするところは銅ポス
ト電極と、Moディスク,Si素子,冷却フイン間の接
触熱抵抗の少ない大電力用半導体装置を提供することに
ある。
SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and has as its object to provide a copper post electrode and a large heat resistance with low contact thermal resistance between the Mo disk, the Si element, and the cooling fin. An object is to provide a power semiconductor device.

【0017】[0017]

【課題を解決するための手段】本発明は、シリコン素子
の両面にそれぞれモリブデンディスクを介して銅ポスト
電極で挟み圧力をかけて電気的接合を行う半導体装置に
おいて、銅ポスト電極とモリブデンディスクの対向する
表面にそれぞれ高熱伝導で軟質の金属薄膜がコーティン
グする。
SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device in which a copper post electrode is sandwiched between both surfaces of a silicon element and a copper post electrode is applied therebetween to electrically connect the silicon element to the copper post electrode and the molybdenum disk. Each of the surfaces to be coated is coated with a soft metal thin film having high thermal conductivity.

【0018】または、シリコン素子の両面を銅ポスト電
極で挟み圧力をかけて電気的接合を行う半導体装置にお
いて、銅ポスト電極のシリコン素子との圧接面を、複数
の低熱膨張金属材料で順次熱膨張率が低くなるようにク
ラッド化する。
Alternatively, in a semiconductor device in which both surfaces of a silicon element are sandwiched between copper post electrodes and electrical connection is made by applying pressure, the pressure contact surface of the copper post electrode with the silicon element is sequentially thermally expanded with a plurality of low thermal expansion metal materials. Cladding is performed so that the rate becomes low.

【0019】そして、上記銅ポスト電極とその外側に設
けて使用する冷却フインとの対向する表面にもそれぞれ
高熱伝導で軟質の金属の薄膜をコーティングするとよ
い。
Further, the surfaces of the copper post electrodes and the cooling fins provided on the outside thereof and facing each other are preferably coated with a thin film of a soft metal having high thermal conductivity.

【0020】[0020]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

実施の形態1 図3,図4に示した半導体装置において、図1に示すよ
うに、モリブデン(Mo)ディスク2,3と銅ポスト電
極6,7の対向する表面21,31と61,71にそれぞれ
銀又はアルミ等の高熱伝導で軟質の金属をコーティング
し、薄膜41,42,51,52を形成する。
Embodiment 1 In the semiconductor device shown in FIGS. 3 and 4, as shown in FIG. 1, opposing surfaces 2 1 , 3 1 and 6 1 of molybdenum (Mo) disks 2 and 3 and copper post electrodes 6 and 7 are arranged. by coating a soft metal with high thermal conductivity, such as respective silver or aluminum to 71 to form a thin film 4 1, 4 2, 5 1, 5 2.

【0021】この薄膜生成方法としては、スパッタ,蒸
着,メッキ等の手法を使用する。これらの方法を用いる
ことで、Moディスク2,3と薄膜41,42との間の隙
間が矢印aで示すように完全に埋まり、密着する。
As a method for forming the thin film, techniques such as sputtering, vapor deposition, and plating are used. By using these methods, the gaps between the Mo disks 2 and 3 and the thin films 4 1 and 4 2 are completely filled and adhered as indicated by the arrow a.

【0022】また、薄膜の厚さをモリブデンディスクの
表面粗さ以上に規定すれば、表面は完全に銀,アルミ等
の軟材料で被覆されるため、圧接面bは軟質金属同士の
圧接のため完全に密着し、銅ポスト電極に対する熱の伝
わりはMoディスクの表面粗さに影響されなくなる。表
面仕上げは、例えば、表2のように規定する。
If the thickness of the thin film is specified to be equal to or greater than the surface roughness of the molybdenum disk, the surface is completely covered with a soft material such as silver or aluminum. It adheres perfectly and the heat transfer to the copper post electrode is no longer affected by the surface roughness of the Mo disk. The surface finish is defined, for example, as shown in Table 2.

【0023】[0023]

【表2】 [Table 2]

【0024】従来、銅ポスト電極表面に硬質材料のニッ
ケル等でコーティングを行っていたものを、より柔らか
い軟質薄膜を形成されることで、銅ポスト表面粗さに影
響されなくなる。薄膜を形成したMoディスクとの間は
完全に薄膜同士の接触となり完全に密着する。
Conventionally, the surface of a copper post electrode is coated with a hard material such as nickel. By forming a softer soft thin film, the surface of the copper post is no longer affected by the copper post surface roughness. The thin film is completely brought into contact with the Mo disk on which the thin film is formed, so that the Mo disk is completely in close contact.

【0025】以上のように、Moディスク、銅ポスト電
極表面に銀等の薄膜を生成することで銅ポスト側との接
触面は薄膜を介在して接触する。形成された薄膜の平坦
性のために、接触面は薄膜同士が完全に密着され、熱伝
導性は向上する。
As described above, by forming a thin film of silver or the like on the surface of the Mo disk or copper post electrode, the contact surface with the copper post contacts with the thin film interposed therebetween. Due to the flatness of the formed thin film, the thin film is completely adhered to the contact surface, and the thermal conductivity is improved.

【0026】また、シリコン(Si)素子との接触面
は、従来はMoディスクとアルミ電極との接触問題であ
り、Moディスクの表面粗さ、硬さなどにより完全に密
着させることが不可能であった。しかし、軟質薄膜を介
在させることで、薄膜とアルミ電極との接触に変わるこ
とで、薄膜が変形することにより完全に密着させること
ができる。
In addition, the contact surface with the silicon (Si) element has conventionally been a problem of contact between the Mo disk and the aluminum electrode, and it is impossible to bring the Mo disk into complete contact with the surface roughness and hardness of the Mo disk. there were. However, by interposing a soft thin film, the contact between the thin film and the aluminum electrode is changed, so that the thin film is deformed and can be brought into close contact.

【0027】相乗効果として、薄膜による表面被覆を行
うことからMoディスクの表面粗さをある程度緩めるこ
とができる。従来は接触を良くするために接触面を鏡面
仕上げ(▽▽▽以上)仕上げが必要であったが、銀,ア
ルミ等の薄膜で完全に被覆されるため、モリブデンディ
スク表面の凹凸は薄膜により完全に埋まる。従って、表
面仕上げを(▽▽▽)仕上げまたは(▽▽)仕上げまで
落とすことができ、大幅なコストの削減が可能になる。
As a synergistic effect, since the surface is coated with a thin film, the surface roughness of the Mo disk can be reduced to some extent. In the past, the contact surface had to be mirror-finished (more than ▽▽▽) to improve the contact. However, the surface of the molybdenum disk was completely covered with a thin film of silver, aluminum, etc. Buried in Therefore, the surface finish can be reduced to (▽▽▽) finish or (▽▽) finish, and significant cost reduction can be achieved.

【0028】なお、銅ポスト電極6,7において、冷却
フイン17,18との接触面に上記コーティング薄膜を
採用しても同様の効果があり、ケース〜冷却フイン間で
発生する接触熱抵抗を低減させることができる。軟質薄
膜材としては、銀,アルミの他に金,錫,アルミニウム
−金合金,アルミニウム合金(Al−10.2Zn−0.
9Mg−0.4Zr),亜鉛合金(Zn−22Al)な
どが適当である。
In the copper post electrodes 6 and 7, the same effect can be obtained even when the above-mentioned coating thin film is adopted on the contact surfaces with the cooling fins 17 and 18, and the contact thermal resistance generated between the case and the cooling fins is reduced. Can be done. As a soft thin film material, in addition to silver and aluminum, gold, tin, an aluminum-gold alloy, and an aluminum alloy (Al-10.2Zn-0.
9Mg-0.4Zr) and a zinc alloy (Zn-22Al) are suitable.

【0029】実施の形態2 図3,図4に示した平型圧接構造の電力用半導体におい
て、銅ポスト電極6(7)〜銀箔4(5)〜モリブデン
電極2(3)といった順序で圧接を行っている部分を図
2(a)のようにクラッド化(複合化)する。即ち、銅
ポスト電極6(7)の表面に、複数の低熱膨張金属を張
り合わせた構造にして、シリコン素子と圧接される部分
の熱膨張率がシリコンの熱膨張率に近い値となるように
する。
Embodiment 2 In the power semiconductor having the flat pressure contact structure shown in FIGS. 3 and 4, pressure contact is performed in the order of copper post electrode 6 (7) -silver foil 4 (5) -molybdenum electrode 2 (3). The part being performed is clad (composite) as shown in FIG. That is, a structure in which a plurality of low thermal expansion metals are bonded to the surface of the copper post electrode 6 (7) so that the coefficient of thermal expansion of the portion pressed against the silicon element is close to the coefficient of thermal expansion of silicon. .

【0030】図2(b)の実線(イ)で示すようになだ
らかに熱膨張率が変化するのが理想であるが、同図
(a)のように、銅表面61(71)から順に低熱膨張率
となるように、クラッド材CMとして複数の低熱膨張金
属(1〜N)を張り合わせることで、同図(b)の点線
(ロ)で示すように低熱膨張率を階段状に変化させるこ
とができる。
Ideally, the coefficient of thermal expansion changes gently as shown by the solid line (a) in FIG. 2 (b). However, as shown in FIG. 2 (a), from the copper surface 6 1 (7 1 ) By bonding a plurality of low thermal expansion metals (1 to N) as the cladding material CM so as to have a low thermal expansion coefficient in order, as shown by a dotted line (b) in FIG. Can be changed.

【0031】クラッド化の方法は、圧延,爆着等を用
い、完全に密着(接合面は2主の材料が絡み合うように
接合される)させることで、上記接触熱抵抗をなくする
ことができる。
The method of cladding is to completely eliminate the contact thermal resistance by using rolling, explosion bonding, etc., and by bringing them into close contact (the joining surfaces are joined so that the two main materials are entangled). .

【0032】CuとMo/W間の中間材が一種類の場
合、表3の(1)〜(3)の材料が適当である。また、
CuとMo/W間の中間材が2種類又は3種類以上の場
合、表4の(1)のようにモリブデン/銅合金の銅含有
量を変えるか、表4の(2)のように表3の材料を組み
合わせる。
When one kind of intermediate material is used between Cu and Mo / W, the materials (1) to (3) in Table 3 are suitable. Also,
When the number of intermediate materials between Cu and Mo / W is two or three or more, the copper content of the molybdenum / copper alloy is changed as shown in (1) of Table 4 or as shown in (2) of Table 4 Combine 3 ingredients.

【0033】[0033]

【表3】 [Table 3]

【0034】[0034]

【表4】 [Table 4]

【0035】[0035]

【発明の効果】本発明は、上述のとおり構成されている
ので、次に記載する効果を奏する。
Since the present invention is configured as described above, the following effects can be obtained.

【0036】(1)モリブデンディスク、銅ポスト電極
の表面に軟質材料をコーティングすることによって、圧
接時に発生するミクロな隙間を完全に埋めることがで
き、接触抵抗をなくすことができる。
(1) By coating the surface of the molybdenum disk and the copper post electrode with a soft material, it is possible to completely fill the micro gaps generated at the time of pressure welding and to eliminate the contact resistance.

【0037】(2)また銅ポスト電極と冷却フインの圧
接面にも軟質薄膜をコーティングすることによって、ケ
ース,フイン間の接触熱抵抗を減らすことができる。
(2) By coating a soft thin film also on the press contact surface between the copper post electrode and the cooling fin, the contact thermal resistance between the case and the fin can be reduced.

【0038】(3)銅ポスト電極をクラッド化すること
で、銅ポスト電極とシリコン素子との間に介在されてい
た熱緩衝板としてのモリブデンディスクをなくすことが
できる。また、各熱低膨張材、銅との隙間は完全に密着
されているので、接触熱抵抗はなくなる。
(3) By cladding the copper post electrode, a molybdenum disk as a heat buffer plate interposed between the copper post electrode and the silicon element can be eliminated. Further, since the gap between each of the low thermal expansion materials and copper is completely adhered, there is no contact thermal resistance.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施の形態1にかかる銅,モリブデン圧接部の
断面説明図。
FIG. 1 is an explanatory cross-sectional view of a copper and molybdenum pressure contact portion according to a first embodiment;

【図2】実施の形態2にかかるもので、(a)はクラッ
ド化された銅ポスト表面の断面構造説明図、(b)はク
ラッド材の熱膨張率を示す線図。
FIGS. 2A and 2B are explanatory diagrams of a cross-sectional structure of a clad copper post surface according to the second embodiment, and FIG. 2B is a diagram showing a thermal expansion coefficient of a clad material.

【図3】電力用半導体平型圧接構造の断面分解説明図。FIG. 3 is an exploded cross-sectional view of a power semiconductor flat pressure welding structure.

【図4】電力用半導体の圧接状態を示す断面図。FIG. 4 is a cross-sectional view showing a pressure contact state of the power semiconductor.

【図5】電力用半導体の放熱等価回路図。FIG. 5 is a heat dissipation equivalent circuit diagram of the power semiconductor.

【図6】ケース構造材料における熱抵抗の占める割合を
示すグラフ。
FIG. 6 is a graph showing a ratio of a thermal resistance in a case structural material.

【図7】従来例にかかる銅,モリブデン接合面の断面状
況説明図。
FIG. 7 is an explanatory view of a cross-sectional state of a copper-molybdenum bonding surface according to a conventional example.

【符号の説明】[Explanation of symbols]

1…シリコン(Si)素子(ウエハ) 11…アルミカソード電極 12…酸化膜 13…アノード電極 2,3…モリブデン(Mo)ディスク 21…モリブデンディスクの表面 4,5…銀箔 41,42,51,52…コーティングされた銀,アルミ等
の薄膜 6,7…銅ポスト電極 61,71…銅ポ電極の表面 8…ゲート電極部 81…銅ゲートリング 82…ゲートリード線 83…PPS樹脂カップ 11…セラミックケース 12,15…ウエルドリング 13…PPS樹脂リング 14…ゴム 17,18…ヒートシンク(冷却フイン) CM…クラッド材。
1 ... Silicon (Si) element (wafer) 1 1 ... aluminum cathode electrode 1 2 ... oxide layer 1 3: anode electrodes 2 ... surface 4,5 ... silver foil 4 1 of molybdenum (Mo) disk 2 1 ... molybdenum disc, 4 2, 5 1, 5 2 ... coated silver thin 6,7 ... copper post electrode 6 1 of aluminum or the like, 7 1 ... the surface of Dopo electrode 8 ... gate electrode portions 8 1 ... copper gate ring 8 2 ... Gate lead wire 8 3 PPS resin cup 11 Ceramic case 12 15 Weld ring 13 PPS resin ring 14 Rubber 17 18 Heat sink (cooling fin) CM Clad material.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 シリコン素子の両面にそれぞれモリブデ
ンディスクを介して銅ポスト電極で挟み圧力をかけて電
気的接合を行う半導体装置において、 銅ポスト電極とモリブデンディスクの対向する表面にそ
れぞれ高熱伝導で軟質の金属薄膜がコーティングされて
いることを特徴とする半導体装置。
1. A semiconductor device in which both surfaces of a silicon element are electrically sandwiched by a copper post electrode via a molybdenum disk and pressure is applied to the silicon element, wherein the copper post electrode and the surface of the molybdenum disk facing each other are soft and high heat conductive. A semiconductor device characterized by being coated with a metal thin film.
【請求項2】 シリコン素子の両面を銅ポスト電極で挟
み圧力をかけて電気的接合を行う半導体装置において、 銅ポスト電極のシリコン素子との圧接面が、複数の低熱
膨張金属材料で順次熱膨張率が低くなるようにクラッド
化されていることを特徴とする半導体装置。
2. A semiconductor device in which both surfaces of a silicon element are sandwiched between copper post electrodes and pressure is applied to electrically connect the silicon element, wherein a pressure contact surface of the copper post electrode with the silicon element is sequentially thermally expanded with a plurality of low thermal expansion metal materials. A semiconductor device characterized by being clad so as to have a low efficiency.
【請求項3】 請求項1と2のいずれか1つにおいて、 銅ポスト電極の外側に冷却フインが圧接して設けられ、
銅ポスト電極と冷却フインとの対向する表面にはそれぞ
れ高熱伝導で軟質の金属の薄膜がコーティングされてい
ることを特徴とした半導体装置。
3. The cooling fin according to claim 1, wherein a cooling fin is provided on the outer side of the copper post electrode by pressing.
A semiconductor device characterized in that opposite surfaces of a copper post electrode and a cooling fin are coated with a soft metal thin film having high thermal conductivity.
JP18898196A 1996-07-18 1996-07-18 Semiconductor device Pending JPH1041443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18898196A JPH1041443A (en) 1996-07-18 1996-07-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18898196A JPH1041443A (en) 1996-07-18 1996-07-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1041443A true JPH1041443A (en) 1998-02-13

Family

ID=16233310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18898196A Pending JPH1041443A (en) 1996-07-18 1996-07-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH1041443A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066464A (en) * 2004-08-24 2006-03-09 Toyota Industries Corp Semiconductor device
WO2008014163A3 (en) * 2006-07-25 2008-11-06 Honeywell Int Inc Synergistically-modified surfaces and surface profiles for use with thermal interconnect and interface materials, methods of production and uses thereof
JP2019145691A (en) * 2018-02-21 2019-08-29 株式会社豊田中央研究所 Semiconductor device and manufacturing method thereof
CN116364661A (en) * 2023-06-02 2023-06-30 清华大学 Press-fit semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006066464A (en) * 2004-08-24 2006-03-09 Toyota Industries Corp Semiconductor device
WO2008014163A3 (en) * 2006-07-25 2008-11-06 Honeywell Int Inc Synergistically-modified surfaces and surface profiles for use with thermal interconnect and interface materials, methods of production and uses thereof
JP2019145691A (en) * 2018-02-21 2019-08-29 株式会社豊田中央研究所 Semiconductor device and manufacturing method thereof
CN116364661A (en) * 2023-06-02 2023-06-30 清华大学 Press-fit semiconductor device

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