JPH1042252A - Digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost of an entire processor without providing a private memory for interpolation by interpolating data by means of the inter-memory transfer of corresponding data. SOLUTION: The respective memory spaces of memory cells 86A and 86B in a memory 17 comprises video memory VM areas with the capacity of one frame and track memory TM areas storing encoding data. memory cells in the respective areas can be set to write/read modes at every frame. Respective processing blocks 3-11 transfer data between the VM or TM areas through sense amplifiers 87A and 87B in accordance with the processing forms. Namely, an encoding/decoding block 7 reads data from the VM areas and executes an encoding processing, writes data in the TM area at the time of an encoding operation and reads compressed data from the TM area, executes a decoding processing and writes data in the VM area at the decoding operation by transferring data between the VM or TM area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus for performing processing such as encoding and decoding of various data, especially image data.

[0002]

2. Description of the Related Art Hitherto, various devices have been developed for encoding various types of data having an enormous amount of data to reduce the amount of data so that the data can be transmitted at a relatively low transmission rate.

For example, in a digital VTR for recording image data on a recording medium such as a magnetic tape, a 124 Vbp is also required.
Standards have been established for compressing input image data of about s to about one-fifth of about 25 Mbps, recording it on a magnetic tape, and reproducing it.

[0004] In a digital VTR based on such a standard, input data is subjected to DCT conversion and then quantized.
This quantized data is compressed by variable-length encoding, and the quantization step at the time of quantization is varied based on various parameters, or the amount of data after variable-length encoding is performed. Is controlled so that is constant.

[0005] Also, input image data is compressed using predictive coding with motion compensation between frames or fields, and the predicted coded data is further compressed using DCT, quantization and variable length coding as described above. MPEG
Standards have been established, and CD-ROs that comply with the standards
Various devices such as M have been developed.

[0006]

When data is transmitted through a transmission system having a large transmission loss such as a digital VTR or a CD-ROM as described above, error correction and error correction cannot be performed to compensate for the loss. Interpolation is performed for a large loss.

However, in order to perform such interpolation, conventionally, a dedicated memory has to be provided, which causes an increase in the cost of the entire apparatus.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and has as its object to provide a digital signal processing device capable of reducing costs.

For this purpose, the present invention provides a memory means having a first memory section for storing data to be processed, a second memory section for storing processed data, and an interpolation section for performing interpolation. Means for performing interpolation by transferring the corresponding data from the second memory unit to the first memory unit in the memory, thereby providing a digital signal processing apparatus. is there.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 1 is a block diagram showing the basic configuration of an embodiment of the present invention applied to a digital VTR.

In this embodiment, as shown in FIG. 1, various processing blocks are controlled by internal / external CPUs, each accesses a memory at a desired timing, and the memory control unit arbitrates those access requests. To guarantee the operation of the processing block.

Further, each processing block in this embodiment can perform real-time processing of SD-compatible image data and audio data. In this embodiment, such processing units are arranged in parallel and each processing circuit By supplying the image data and the audio data in a divided manner and processing the data, the data amount per frame can be reduced by the SD.
It is configured to be able to process HD-compatible image data and audio data that is twice as large as the image data in real time.

Each processing circuit in the processing unit is
As shown in FIG. 1, a data I / O block 1 for processing data such as input data from a camera, output data to an EVF, and line input / output data.
An image data input / output block 3 for performing processing such as C separation, an audio processing block 5, and an encoding / decoding scheme for performing variable length encoding / decoding on image data using discrete cosine transform.
A decoding block 7, an error correction block 9, a coded data input / output block 11 for converting the coded data into a tape format at the time of recording or a deformatting process at the time of reproduction, and an electromagnetic conversion process at the time of recording / reproduction. These blocks are generally constituted by an electromagnetic conversion processing block 25, and these blocks exchange data with the external memory 17 via the address conversion circuit 13 and the memory interface 15.

The operation of these processing circuits is performed by a system control CPU that controls internal electric system processing.
The predetermined commands supplied via the bus CBS2, and the blocks arranged in parallel under the control of the CPU bus CBS1 and the interface 21 from the external servo CPU and the predetermined commands supplied via the CBS2, Let it be split.

The memory 17 in the present embodiment is an SDRAM (Synchronous-DRAM) capable of performing burst transfer of data in synchronization with the rise of a clock.
This SDRAM is composed of two systems of memory arrays M1 and M2 as shown in FIG.
(2) from the external frequency transmitter 27 having no jitter to the frequency multiplier 29 in the above-mentioned unit.
A clock of 5 MHz is supplied, and 67.5 MHz generated by multiplication there is supplied as a reference clock. Here, the reference clock 67.5 MHz (M
CLK) is H_Sync generated by the frequency transmitter 31.
It is set to an integral multiple (5 times) of 13.5 MHz locked to. Further, a mode controller 82 for setting the read / write mode of the memory array based on the control signal and the address signal from the address conversion circuit 13 and the memory I / F 15 of FIG. Address controller 83 for designating an address in the memory array, shift register 84 for performing serial-parallel conversion, input / output buffer memory 85
It is composed of

Each of the memory arrays M1 and M2 in the memory 17 is a memory cell (DRAM) 8
6A and 86B and sense amplifiers 87A and 87B provided independently of these memory cells. A predetermined amount of data held in these sense amplifiers is burst-transferred in synchronization with a clock to transfer data to and from the outside of the memory. Transfer speed and the operation speed in the internal bank can be set independently, thereby enabling high-speed read / write access as a whole.

Further, as shown in FIG. 2B, the sense amplifiers 87A and 87B in this embodiment are 8 × 64
It has a capacity of (8 × 8) pixels, and can perform burst transfer in units of 8 pixels.

Each memory space of the memory cells 86A and 86B in the memory 17 has a video memory (VM) area having a capacity of one frame and a memory space for storing encoded data of one frame. And a track memory (TM) area having a capacity. The memory cells in each area can be set to a write mode and a read mode for each frame, and each of the processing blocks has a processing mode. Depending on the VM region or T through the sense amplifiers 87A and 87B.
Data is exchanged with the M area.

That is, as shown in FIG. 3, the image data input / output block 3 exchanges data exclusively with the VM area, and the encoding / decoding block 7 has both the VM area and the TM area. In the encoding operation, data is read out from the VM area, and the data is written to the TM area during the encoding operation. In the decoding operation, the data is read out from the TM area and the data is decoded.
Write to M area.

Similarly, the audio processing block 5,
The error correction block 9 and the coded data input / output block 11 exchange data exclusively with the TM area.

The address space in each of the above areas is configured as shown in FIG.

That is, in the VM area, image data (Y, Cr, Cb) before being encoded is written in pixel units, and this image data (in the case of the NTSC system, 720 pixels horizontally × vertically in the frame) 480 pixels) are allocated to 50 super macroblocks (hereinafter, referred to as SMBs) of 5 blocks in the horizontal direction × 10 blocks in the vertical direction, and each SMB is composed of 4 DCT blocks of luminance data and 1 block of chrominance data.
A macro block composed of a DCT block (hereinafter referred to as MB
27) are collected.

[0024]

[Table 1]

Each DCT block is composed of 8 × 8 pixels.

One frame of image data having the number of pixels as described above is subjected to encoding processing in the case of the NTSC system, and thereafter, is subjected to 10 tracks on the magnetic tape (12 tracks in the case of the PAL).
The image data before encoding corresponds to one track of the data of 5 SMBs arranged in the horizontal direction as described above.

Therefore, as addresses when accessing this VM area, h, v, track number Tr, SMB number in each track, and SMB number in each SMB corresponding to the horizontal and vertical directions of each pixel, respectively. MB number,
It is preferable to use the DCT number in each macroblock.

On the other hand, in the TM area, the coded image data, the error correction code, and the like are stored in the ten (PA) areas.
In the case of L, 12 tracks are distributed and recorded, and 149 sync blocks (hereinafter, referred to as SBs) are recorded in an area corresponding to each track.

Similarly, although not shown, audio data, error correction codes, etc., are also independent of the image data area.
It is distributed and recorded on 0 tracks (12 tracks in the case of PAL), and 14 SB is recorded in an area corresponding to each track.

Each SB of the image data / audio data includes synchronous data (hereinafter, referred to as SY) indicating the head of the SB, ID data (hereinafter, referred to as ID) indicating each address and attribute of the signal, and the like. (Image / audio) data and parity.

Therefore, the address for accessing this TM area is the track number Tr, each Tr
, The sync block number (hereinafter referred to as SB) in each
It is preferable to use the symbol number in B (hereinafter, referred to as SMB).

The access of each processing block to the memory 17 as described above is arbitrated and controlled by the address conversion circuit 15.

That is, although not shown, the address conversion circuit 13
Is transmitted from the internal and external CPUs 19 and 23 via the CBS 2 to specify a type of various operation modes such as a reproduction mode and a recording mode, or the mode is directly set by a predetermined bit of an address of each block. The transmitted data is used to perform scheduling related to the priority of data transfer in accordance with these pieces of information, and to perform data transfer between each processing block and the memory 17 in response to an access request (hereinafter referred to as Req) from each of the above blocks. Mediation of

The above-mentioned command is determined by the internal / external CPU detecting an operation mode set by each switch or the like of the apparatus main body, not shown, and includes, for example, an encoding mode, a decoding mode, , VTR and various operation modes such as a special reproduction mode.

The operation mode specified by the command is not limited to the above-mentioned operation mode, and includes various operations such as image synthesis, post-recording, editing of inserts, dubbing, and the like.

The address conversion circuit 13 generates a predetermined address to be described later for each processing block so that addressing can be performed in an optimum data unit according to the processing mode in each processing block and the address space of the memory 17. .

The address generation operation in the address conversion circuit 13 is variably set based on a parameter corresponding to an image type transmitted from the internal and external CPUs 19 and 23. Different addresses are generated according to the image type (size) such as SD or HD, or NTSC or PAL.

On the other hand, each part of each processing circuit is supplied with a required clock, and operates in synchronization with the clock.

These clocks are supplied to the image data input / output block 3 based on synchronization signals HSync and VSync extracted from the input signal, an internal reference clock, and the like.
The first clock (13.5 MHz in this embodiment) supplied to the audio processing block 5 and supplied to the audio processing block 5 to process audio data (not shown). In the example, 48 KHz), a third clock (67.5 MH in this embodiment) supplied to the encoding / decoding block 7, the error correction block 9, the address conversion circuit 13, the memory I / F 15, and the memory 17.
z), a fourth clock for recording / reproducing to / from the recording medium with a clock synchronized with the rotation of the drum supplied from the electromagnetic conversion processing block to the encoded data input / output block 11 (41. 85 MHz), and each processing block performs a processing operation according to the supplied clock.

Hereinafter, the memory control in the interpolation realized by the present invention in the above processing circuit will be described in detail.

FIG. 4A is a configuration diagram showing an operation of interpolating image data that has been lost during reproduction in the system configuration described above. Here, interpolation processing is performed using the compressed data before decoding in the TM area. In the above-described embodiment, the TM area has a configuration in which two frames are allocated. However, in the present embodiment, the interpolation processing from the previous frame is performed, so that the T area for another frame is stored in the empty area of the memory.
Allocate M area. That is, the interpolation process is performed with the TM area configured as three banks. Hereinafter, an operation at the time of reproduction will be described as an example.

A terminal 140 is an input terminal from the coded data input / output block 11 shown in FIG. 1, and a terminal 142 is an input terminal from the error correction block 9 shown in FIG.
As described above, each memory access request is arbitrated by the address conversion circuit 13 in FIG. 1, and an address converted into a real address of the memory, image data before being decoded, and the like are supplied. 144, 146
Are BK0 and B in the frame memory of the TM area described above.
K1 and 148 are memory BK2 for another frame provided for realizing the previous frame interpolation. The write / read access to the three BK areas is controlled by being supplied as BK information from the system control CPU 19 shown in FIG. 1 to each processing block, and being reflected in the upper address. SW150
Is controlled by the system control CPU 19 shown in FIG. 1 in the same manner as described above to supply image data read out from the memory areas BK0, BK1, and BK2 to each processing block as BK information, which is reflected in the upper address. Is controlled by The output from the SW 150 is supplied to an encoding / decoding block via, for example, a terminal 152, and is expanded and written to a predetermined area of a VM area during reproduction.

FIG. 4B is a diagram showing the operation of each processing block during reproduction in the memory configuration. The vertical axis is an address, and within each BK, a track number, a sync block number, and a symbol number in byte data units are assigned. The horizontal axis is time and Fr
ame0 to Frame3 represent a 1/30 second frame time. A solid line 154 indicates a write operation of the reproduction data by the encoded data input / output block, and each BK is accessed by linear addressing. A dotted line 156 indicates a read operation for syndrome calculation by an error correction block with respect to the reproduction data written by the encoded data input / output block. Each BK is accessed by linear dressing delayed one track in time. 158 indicated by a square is a one-track delay from the read operation of the above-mentioned syncdrome calculation, and when an error is detected in the calculation result, the specific block having the error is read and corrected by adding correction data. This shows an operation for writing to a position on the original memory afterwards. In this case, processing of data in one track within one track time is compensated. If there is an error exceeding the error correction capability, an interpolation flag is added to each MB unit, so that the subsequent processing is performed so that some interpolation processing becomes possible.

The hatched area 160 indicates that the encoded / decoded block is delayed from the predetermined BK area by one frame with respect to the compressed image data obtained by performing the error correction processing on the reproduced data before decoding. This figure shows the processing operation of reading and decoding the original image data in units of 5 MB. However, since the even-numbered track 5 MB and the odd-numbered track 5 MB are subjected to the shuffling process in which they are alternately accessed temporally, there are temporally inaccessible tracks as shown in the figure.

Here, F by the encoding / decoding block
When the interpolation flag can be detected in the decoding process of the BK1 area at the time of frame2, the encoding / decoding block is at the same position one frame before by changing only the BK address to one frame before. Interpolation processing is performed by replacing the data with MB data. The above-mentioned system control CPU 19 collectively manages the phase relationship between the addresses of the processing blocks. Table 1 shows the phase relationship of BK in the above processing, in which the coded data and the error correction block are BK0, the normal processing of the coded decoding block is BK2, and the interpolation processing of the coded decoding block is performed in Frame 0 time. Are controlled to access BK1. Hereinafter, even during the time of Frame 1 and the time of Frame 2, the processes are controlled within the same time so that the overwriting of reading / writing does not occur.

The memory access in the above processing is realized by arbitration and address conversion of an access request by the address conversion circuit 13 shown in FIG. 1, and access processing to the main memory by the memory 1 / F15.

Next, the arbitration operation of the memory access request from each block and the output means of the access address and the mode in the above-described address conversion circuit will be described with reference to FIGS. However, for the sake of simplicity, the description will be made on the assumption that the two processing blocks A / B independently access.

FIG. 5A shows a block diagram of the above processing. Jk flip-flops 100 and 102 synchronized with a master clock (hereinafter, referred to as MCLR) transmit access request signals Re from the two processing blocks A / B.
q_A and Req_B are supplied to a K terminal, and an access permission signal Ack_ corresponding to the access request signal is supplied to a J terminal.
A and Ack_B are supplied. Each output of the Jk flip-flop is supplied to a latch 104 with output control. The latch 104 is connected to the memory I / F1 shown in FIG.
The signal indicating that the bus of the memory is dissolved from 5 and the next access request can be accepted (hereinafter referred to as Complete). Controls the output. That is, Compl
Each Req at that time depends on the timing of the et signal.
Is operated to be latched and output. The output on the Req_A side of the latch 104 is supplied to the D flip-flop 106 and the OR gate 112, and the output is
An access permission signal Ack_A for q_A is obtained.

On the other hand, the output on the Req_B side of the latch 104 is supplied to the inverted output on the Req_A side and the OR gate 108, and its output is ORed with the D flip-flop 110.
The signal is supplied to the gate 114 and becomes an access permission signal Ack_B for the output Req_B. Here, the OR gate 108 determines that the priority of the access request signal is Req_A.
This is necessary because Req_B is lower than Req_B.

Addr_A and Addr_B are logical addresses irrespective of the real address of the main memory, and are burst-transferred data (for example, 64 bytes).
Indicates the start address of These logical addresses are supplied to latches 116 and 118, and Ack_A, Ack_A
Either one is output under the control of ck_B. The output address is supplied to a conversion table 120, which converts the address into a real address for memory access according to the state of Ack_A and Ack_B, and writes a mode signal such as a burst length of data to be written / read and accessed in FIG. To the indicated memory I / F 15.

The memory I / F 15 accesses the main memory by incrementing the head real address of the transfer data by the burst length by a counter (not shown).

FIG. 5B shows the timing of the above processing operation.

A and C are access request signals from each block, Req_A and Req_B, and B and D are Req_A and Req_B, respectively.
It is a logical address from each block that changes according to q_A and Req_B. E and F are output signals of the Jk flip-flops 100 and 102, respectively,
_A and Req_B reset it to the “L” level, and Ack_A and Ack_B set it to the “H” level. G is the memory I / F 15 as described above.
This is the timing at which the next access request is accepted by the signal supplied from. That is, at the time when the Complete becomes "L" level, the signals of E and F are latched and the access permission signal Ack_
A and Ack_B are output at low active.

J is an access permission signal Ack_A, Ac
Latches 116 and 11 enabled by k_B
This is the address output from the address 8. K and L are an address converted into a real address output from the conversion table 120 and a mode signal.

In this embodiment, the operation in response to an access request from two blocks has been described. However, the same processing can be performed for N blocks.

[0056]

The present invention has the following effects.

According to the invention relating to the memory control in interpolation, in a system in which a plurality of processing blocks access one main memory in parallel, the writing / reading of each processing block does not compete with each other and the time is shortened. Can be interpolated by the data of the same position block from the previous frame closest to the above, and a good reproduced image can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of the present invention.

FIG. 2 is a configuration diagram of a synchronized DRAM used in the present invention.

FIG. 3 is a view for explaining an access correspondence relationship of each processing block to a memory in FIG. 2;

FIG. 4A is a configuration diagram for realizing an interpolation process according to the present invention. FIG. 3B is a diagram showing a state where each processing block related to the interpolation processing in the present invention accesses a memory.

FIG. 5A is a configuration diagram for arbitrating a plurality of access requests according to the present invention. FIG. 5B is a timing chart in FIG.

Claims (3)

[Claims] 1. A first memory unit for storing data to be processed, and a second memory unit for storing the processed data.
And an interpolation unit for performing interpolation. The interpolation unit executes the interpolation by transferring the corresponding data from the second memory unit to the first memory unit in the memory. A digital signal processing device characterized by the above-mentioned. 2. A first memory unit for writing or reading data at least, a second memory unit for processing the written data, and a third memory unit for storing the processed data. And an interpolation unit for performing interpolation. The interpolation unit executes the interpolation by transferring the corresponding data from the third memory unit to the second memory unit in the memory. A digital signal processing device characterized by the above-mentioned. 3. The digital signal processing device according to claim 1, wherein an SDRAM is used as said memory means.