JPH104355A - Reference voltage generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To finely adjust a generated voltage by providing proper data externally to a resistance string reference voltage generation circuit. SOLUTION: Data are written externally to a resistance cell matrix circuit that is formed by connecting unit resistance cells RC each consisting of a memory element M to which data are written by data signal inputs B1 to Bt and word signal inputs W1 to Wn, of a switch circuit SW open/closed by written data, and of a reference voltage division resistor R connected in series with the switch circuit between an external high level power supply VH and an external low level power supply VL in a matrix shape. Then number of connected reference division resistors R connected between output terminals VOUT1 to VOUTn to control the resistance, and a generated output voltage is finely adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generation circuit, and more particularly to a reference voltage generation circuit suitable for a reference voltage generation circuit of a liquid crystal driver IC that generates a multi-gradation output voltage using a resistor string.

[0002]

2. Description of the Related Art Conventionally, this type of reference voltage generating circuit is disclosed in, for example, a document (S.I.D.94 Digest, 1994, pp. 351-354, SID 94 DIG).
As described in EST, pp. 351-354, May 1994), a liquid crystal driver IC is used for generating multi-gradation output voltages.

FIG. 5 is a diagram showing an example of the configuration of a conventional reference voltage generating circuit of this kind in the form of an equivalent circuit. Referring to FIG. 5, an external power supply input terminal (V0 to V8) for applying an external power supply, a reference division resistor (R1 to R64) for dividing a voltage applied from the external power supply, and a reference division resistance. Output terminals that output the divided voltage (VOUT1 to VOUT
OUT64).

Next, the operation of the conventional reference voltage generating circuit shown in FIG. 5 will be described. FIG. 6 shows a relationship between the output voltage V of the reference voltage generation circuit and the transmittance T of the liquid crystal (“VT”).
(Referred to as "characteristics"). An ideal relationship between the output voltage and the transmittance is a non-linear curve as shown by the broken line in FIG.

The conventional reference voltage generating circuit shown in FIG.
When a voltage is externally applied to the external power supply input terminals V0 to V8, a voltage generated between eight terminals between V0 and V1 to V7 and V8 is connected in series between the terminals and a resistor R1 having the same resistance value is connected. By dividing the voltage into eight at R64, an output voltage of 64 gradations is generated.

The generated voltage is corrected by adjusting the external power supply voltage input to the external power supply input terminals V0 to V8, and the VT characteristic is approximated as shown by the solid line in FIG. .

[0007]

However, the above-mentioned conventional reference voltage generating circuit has the following problems.

The first problem is that it is not possible to finely adjust the generated voltage per unit gray scale, so that a more accurate V-
That is, the T characteristic cannot be approximated.

The reason is that in the conventional reference voltage generating circuit shown in FIG. 5, since the external power supply input terminals are divided by the reference dividing resistors having the same value, the voltage applied between the external power supply input terminals is reduced. This is because only an output voltage obtained by equally dividing the voltage can be generated.

The second problem is that if the resistance value of the reference dividing resistor varies, the desired voltage cannot be obtained because the voltage dividing ratio between the external power supply input terminals fluctuates. That is.

The reason is that in the conventional reference voltage generating circuit shown in FIG. 5, the resistance value of the reference dividing resistor is fixed to a specific value, and the resistance value cannot be freely changed.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to finely adjust a generated voltage per unit gradation and to realize a highly accurate VT characteristic approximation. It is an object of the present invention to provide a reference voltage generating circuit which enables the above.

Another object of the present invention is to provide a reference voltage generating circuit capable of correcting a variation in the resistance value of a reference divided resistor.

[0014]

In order to achieve the above object, a reference voltage generating circuit according to the present invention comprises a reference voltage generating a reference voltage by connecting a reference dividing resistor between a high potential power supply and a low potential power supply. The generation circuit includes a memory element to which data is written by a data signal and a word signal, a switch circuit that opens and closes with the data written to the memory element, and a reference dividing resistor connected in series to the switch circuit. Cell matrix circuit formed by connecting a plurality of unit resistance cells configured in series between the high potential power supply and the low potential power supply in series and in parallel in a matrix, and the resistance cell matrix circuit And a plurality of output terminals for outputting a reference voltage divided by the above.

In the present invention, a resistance cell matrix circuit formed by connecting unit resistance cells formed by a memory element, a switch circuit, and a reference dividing resistor in a matrix between a high potential and a low potential external power supply is provided. The unit resistance cells constituting the resistance cell matrix circuit connect / disconnect a reference divided resistance according to the value of written data. For this reason, the number of connections of the reference dividing resistors can be changed according to externally input data, and the generated voltage can be finely adjusted.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of the first embodiment of the present invention. Referring to FIG. 1, a first embodiment of the present invention relates to a memory element M to which data is selected and written to a data signal input (B1 to Bt) and a word signal input (W1 to Wn); A switch circuit SW whose opening and closing are controlled by the value of data written in M, and a unit resistance cell RC formed by a reference divided resistor R connected in series to the switch circuit SW, and a high-potential external power supply VH And a low-potential external power supply VL, a resistance cell matrix circuit formed by connecting n unit resistance cells RC in series and t in parallel form in a matrix, and a resistance cell matrix circuit And output terminals (VOUT1 to VOUTn) for outputting the divided reference voltages.

Next, the operation of the first embodiment of the present invention will be described.

When data "1" and "0" are written in the memory element M in the cell, the unit resistance cell RC opens and closes the switch circuit SW in accordance with the value of the written data. Between output terminals (VOUT1-VOUT2-VOU
Tn-1−VOUTn) is connected / disconnected.

The unit resistance cells are connected in series in n pieces and in parallel in t pieces.
The resistance cell matrix circuit connected in a matrix form uses data signal inputs (B1 to Bt) and word signal inputs (W1 to Wn) to externally supply data to the memory element M of the unit resistance cell RC. Write data,
The number of resistors R connected between the output terminals can be changed.

That is, by inputting appropriate data from the outside, the resistance value between the output terminals of the resistance cell matrix circuit can be changed, and the generated output voltage can be finely adjusted.

Next, the operation and effect of the embodiment of the present invention will be described. In the embodiment of the present invention, by inputting appropriate data from the outside, the generated voltage per unit gray scale can be finely adjusted, so that a more accurate VT
The characteristics can be approximated.

Further, even if the generated voltage fluctuates due to a variation in the resistance value of the reference divided resistor, etc., the generated voltage can be corrected by inputting data corresponding thereto from the outside.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the above-described first embodiment of the present invention in more detail, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows an example of a configuration using an SRAM (static random access memory) as a memory element by an equivalent circuit.

That is, referring to FIG. 2, unit resistance cell RC includes first and second Pc connected to DC power supply VDD.
h transistors P1 and P2, and gates are word signal input W
1, a first Nch transistor N1 connected between the first Pch transistor P1 and the data signal input B1, a gate having a gate of the second Pch transistor P2, a first Nch transistor N1 and a second And a second Nch transistor N2 connected between the second Pch transistor P2 and the ground. The SRAM is used as a memory element, and the gate is connected to the second Nch transistor P1. The third Nch transistor N3 connected to the connection point between the transistor N2 and the second Pch transistor P2 is used as a switch circuit, and the third Nch transistor N3 is connected in series with a reference dividing resistor R. The unit resistance cells RC are connected in a matrix to form a resistance cell matrix circuit, and are connected to a high-potential external power supply VH. It includes an output terminal connected Vout1~Voutn to a connection point n unit resistive cell RC connected to the end and in series is constituted.

Next, the operation of the reference voltage generating circuit of this embodiment shown in FIG. 2 will be described.

"H" (high level) is applied to the word signal input W1.
There they are entered, the data signal input data that is input from B1 is written in the SRAM unit resistive cell RC 1 _{over 1.}

At this time, when the written data is "0", the second Nch transistor N2 is turned off, the second Pch transistor P2 is turned on, and the drain potential becomes the power supply potential VDD. Since "H" (high level) is input to the gate of the Nch transistor N3 acting as a switch circuit, the Nch transistor N3 is turned on, and the output terminals (VOUT1 -VOUT
2), a reference dividing resistor R is connected. On the other hand, when the written data is "1", the second Nch transistor N2 is turned on, and "L" is input to the gate of the third Nch transistor N3. It becomes OFF state, and between output terminals (VOUT1-VOUT
The reference dividing resistor R is separated from 2).

A resistance cell matrix circuit formed by connecting the unit resistance cells RC in a matrix (ie, n unit resistance cells RC in series in the row direction and t units in parallel in the column direction) is configured to receive data from outside. The resistance value can be controlled by changing the number of resistors R connected between the write and output terminals, and the generated output voltage can be finely adjusted.

A second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a diagram showing an example of a configuration using a DRAM (dynamic random access memory) as a memory element of the unit resistance cell RC by an equivalent circuit.

Referring to FIG. 3, unit resistance cell RC includes a capacitor C having one end connected to ground potential (GND),
The gate is connected to the word signal input W1 and the capacitor C
Of the first Nch transistor N1 connected between the other end of the first Nch transistor and the data signal input B1 is used as a memory element, and the gate is connected to the first Nch transistor N1.
A second Nch transistor N2 connected to a connection point between the second Nc transistor
The transistor N2 is formed by connecting a reference dividing resistor R in series to the transistor N2. The unit resistor cells RC are connected in a matrix to form a resistor cell matrix circuit. The output terminals Vout1 to Vout1 connected to the connection point of the n unit resistance cells RC connected to
Voutn.

The operation of the reference voltage generating circuit of this embodiment shown in FIG. 3 will be described.

When "H" is input to the word signal input W1, the data input from the data signal input B1 is written to the DRAM in the unit resistance cell RC. When the written data is "1", "H" is input to the gate of the Nch transistor N2 used as the switch circuit, so that the Nch transistor N2 is turned on.
A reference dividing resistor R is connected between the output terminals (VOUT1-VOUT2). On the other hand, if the written data is “0”, N
Since "L" is input to the gate of the channel transistor N2, the Nch transistor N2 is turned off, and the resistor R is disconnected from between the output terminals (VOUT1-VOUT2).

A resistance cell matrix circuit formed by connecting the unit resistance RC circuits in a matrix form, similarly to the first embodiment, writes data from the outside and outputs data of R connected between output terminals. By changing the number of connections and controlling the resistance value, the generated output voltage can be finely adjusted.

Next, a second embodiment of the present invention will be described. FIG. 4 is a diagram showing a configuration of the second exemplary embodiment of the present invention.

Referring to FIG. 4, in the second embodiment, in the unit resistance cell RC of the first embodiment described with reference to FIG. 2, data is written in the SRAM type memory element. Instead of a switch circuit that opens and closes according to data and a reference division resistor connected in series to the switch circuit, Nch that also serves as the switch circuit and the reference division resistance
It comprises a transistor NR.

Next, the operation of the circuit shown in FIG. 4 will be described. As in the first embodiment, the word signal input W1 and the data signal input B1 cause the data to be transferred to the unit resistance cell RC.
When the written data is "0", "H" is input to the gate of the Nch transistor NR used as the switch circuit and the reference dividing resistor, so that the Nch transistor NR is turned on. In this state, the Nch transistor NR (ON resistance) is connected between the output terminals (VOUT1-VOUT2). On the other hand, when the written data is "1", "L" is input to the gate of the Nch transistor NR. Therefore, the Nch transistor NR is turned off, and the Nch transistor NR is disconnected from between the output terminals.

Data is externally written into a resistance cell matrix circuit formed by connecting the unit resistance cells RC, and an Nch transistor N connected between output terminals is written.
By changing the number of R connections and controlling the resistance value, the output voltage to be generated can be finely adjusted as in the first embodiment.

[0040]

As described above, according to the present invention,
Since the generated voltage per unit gradation can be finely adjusted, there is an effect that a more accurate approximation of the VT characteristic can be realized. This is because, in the present invention, by inputting desired data from the outside, the resistance value between the output terminals of the resistance cell matrix circuit can be arbitrarily changed.

Further, according to the present invention, the resistance between the output terminals of the resistance cell matrix circuit can be controlled by externally inputting data corresponding to the variation of the generated voltage. There is an advantage that the generated voltage can be corrected even if the generated voltage fluctuates due to variation or the like.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional technique.

FIG. 6 is a diagram showing operating characteristics of a conventional technique.

[Explanation of symbols]

 B1 to Bt Data signal input W1 to Wn Word signal input M Memory element SW Switch circuit R Reference division resistance RC Unit resistance cell VH High potential external power supply VL Low potential external power supply VOUT1 to VOUTn Output terminal VDD DC power supply P1 to P2 Pch Transistor N1 to N3 Nch transistor C Capacitor NR Switch circuit and reference division resistance Nch transistor V0 to V8 External power supply input terminal R1 to R64 Reference division resistance VOUT1 to VOUT64 Output terminal

Claims (4)

[Claims] A unit resistance cell comprising a storage element and a switch for controlling connection / disconnection of a reference divided resistor according to a value of data stored in the storage element is connected to a first power supply and the first power supply. A plurality of power supplies are connected in series between a power supply and a second power supply having a lower potential than the power supply, and a plurality of power supplies are connected in parallel between output lines for extracting a divided voltage between the power supplies or between the power supply and output lines. A reference voltage generation circuit comprising a matrix circuit. 2. A reference voltage generating circuit for generating a reference voltage by connecting a reference dividing resistor between a high potential power supply and a low potential power supply, wherein a memory element to which data is written by a data signal and a word signal is provided. A unit resistance cell including a switch circuit that opens and closes according to data written in the memory element and a reference divided resistor connected in series to the switch circuit, the unit resistance cell including the high-potential power supply and the low-potential power supply. A resistor cell matrix circuit formed by connecting a plurality of resistors in series and in parallel in a matrix, and a plurality of output terminals for outputting a reference voltage divided by the resistor cell matrix circuit. A reference voltage generation circuit, characterized in that: 3. An active device having a unit resistance cell serving as a memory element to which data is written by a data signal and a word signal, a switch circuit that is opened and closed by the data written to the memory element, and a reference dividing resistor. 3. The reference voltage generation circuit according to claim 2, wherein the reference voltage generation circuit is formed by an element. 4. The reference voltage generating circuit according to claim 3, wherein said active element comprises a MOS transistor.