JPH1048357A - Electronic watch - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To sufficiently utilize the electric energy of a power supply even if a power supply that waits for non-flat discharge characteristics is used. SOLUTION: A plurality of power supplies including at least a power supply A and a power supply B having electric energy smaller than the power supply A, wherein at least the power supply B is chargeable and supplies electric energy from the power supply A to the power supply B. An electronic timepiece comprising: means for supplying electric energy from the power supply A to the power supply B; and means for changing a voltage level between the power supply A and the power supply B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply unit in an electronic timepiece such as a quartz timepiece using electric energy as an energy source. In particular, the present invention relates to an improvement in a power supply unit of an electronic timepiece having a power supply in which the discharge characteristics of the power supply are not flat and the voltage changes as the discharge proceeds.

[0002]

2. Description of the Related Art A conventional electronic timepiece, such as a quartz timepiece, which uses electric energy as an energy source, uses a power source having flat discharge characteristics, such as a silver battery, as its power supply. This made full use of the energy of the power supply.

[0003] However, silver batteries are expensive and have a drawback such as a long life of the batteries themselves.

In recent years, alkaline manganese batteries and the like have been used as solutions to these problems, and the life of the batteries themselves has been reduced by using a solar battery as a power source.
Timepieces using high-capacity capacitors as secondary batteries have also been proposed.

[0005]

According to the above technique, the alkaline manganese battery does not have a flat discharge characteristic and has a large amount of energy even after the operation of the timepiece is stopped, so that it cannot be said that the battery characteristic is fully utilized. Is the current situation. 2
In the case of using a high-capacity capacitor as a secondary battery, the duration of time until the stop of the timepiece is naturally determined by the discharge characteristics of the capacitor, which has been a major problem in practical use.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and to make full use of the electric energy of the power supply even if a power supply that waits for non-flat discharge characteristics is used.

[0007]

SUMMARY OF THE INVENTION The present invention has a plurality of power supplies including at least a power supply A and a power supply B having a smaller electric energy than the power supply A, and at least the power supply B is chargeable and is supplied from the power supply A to the power supply B. The means for supplying electric energy from the power supply A to the power supply B has a means for supplying energy and relates to an electronic timepiece including means for changing the voltage level between the power supply A and the power supply B.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings according to an embodiment.

This embodiment is a timepiece using a solar battery as a power generation mechanism and an electric double layer capacitor as a secondary battery as a secondary battery.

FIG. 1 shows the discharge characteristics of the electric double layer capacitor, and FIG. 2 is a block diagram of an embodiment according to the present invention. FIG. 3 is a circuit diagram of a conventional system. Conventionally, in FIG. 3, when the electric power generated by the solar battery 1 is charged to the electric double layer capacitor 12 and charged to the rated voltage or more, the limiter switch 13 is closed to stop charging the capacitor 12. The clock 14 operates using the solar battery 11 or the condenser 12 as a power supply. The diode 15 is connected to the solar battery 11.
Is a backflow prevention diode for preventing current from flowing into the solar battery when the generated electromotive voltage becomes lower than the charging voltage of the capacitor 4. The discharge characteristics of the capacitor 12 after the solar battery 11 has stopped illuminating the light when the capacitor 12 is fully charged are shown by the solid line Vs in FIG.
s2 and a broken line V'ss1. The vertical axis represents the voltage of the capacitor 12, and the horizontal axis represents time. The rated voltage of the capacitor in this embodiment is 1.8V. The operation stop voltage of the clock body is 0.9 V. At this time, the operation of the clock starts at t2 after the solar light stops illuminating.
It will stop in time.

FIG. 2 is a block diagram of an embodiment according to the present invention. The electric power generated by irradiating the solar battery 1 with light is charged into the electric double layer capacitor 4 through the backflow prevention diode 3. At this time, if the generated electromotive voltage (Vssl) of the solar battery 1 becomes higher than the rated voltage, the limiter circuit 2 operates to stop charging the capacitor 4. For example, the rated voltage is the rated voltage of the capacitor 4. The limiter circuit is composed of a constant-voltage diode. When the voltage between VDD and VSS1 exceeds the rated voltage in the drawing, the current is supplied to bypass the charging current, or between VDD and VSS1. , And is configured to bypass the charging current by detecting a reference voltage. The electric power charged in the capacitor 4 is optimally boosted by the multi-stage boosting charging circuit 5 and charged in the capacitor 6. A detailed description of this operation will be described later. The capacitor 6 serves as a power supply for a voltage detection circuit 7 for detecting the voltage VSS1 'of the capacitor 4, a control circuit 8 for causing the boost charging circuit to perform optimum boost charging based on the voltage detection output, and a clock circuit 9.

Next, the operation of this embodiment will be described in detail with reference to FIG. Here, the broken line in FIG. 1 indicates the absolute value of the voltage VSS′1 of the large-capacity capacitor 4, and the solid line indicates the absolute value of the voltage VSS2 of the capacitor 6. A description will be given of a case where light does not shine on the solar battery 1 after the capacitor 4 is fully charged. When the voltage | VSS'1 | of the capacitor 4 is 1.2 V or more, the boost charging circuit 5 operates so that the capacitor 4 and the capacitor 6 have the same voltage. Voltage of capacitor 4 | VSS '
When 1 | is 1.2 V to 0.8 V, the voltage is boosted twice by the boosting charging circuit 5 to charge the capacitor 6. FIG.
This is a section of t3. Therefore, the condenser 6 at this time
Voltage | VSS2 | is 1.8V to 1.2V. The voltage | VSS'1 | of the capacitor 4 is 0.8 V to 0.6 V
In this case, the voltage is boosted twice by the boost charging circuit 5 and charged in the capacitor 6. In FIG. 1, it is a section from t3 to t4. At this time, the voltage | VSS2 |
6 V to 1.2 V.

When the voltage | VSS'1 | of the capacitor 4 is 0.6 V or less, the capacitor 6 is boosted three times by the boost charging circuit 5 and charged. This is after t4 in FIG.

As described above, according to the present embodiment, the voltage | VSS2 | of the capacitor 6, which is the actual power source of the timepiece, is reduced to the operation stop voltage 0.9V by the boost charging means.
By keeping the above, the operable time of the clock is extended from time t2 to time t5 in FIG. In addition, the voltage of the capacitor 4 is conventionally 0.9 V to 1.8 V.
However, according to the present embodiment, the power that can be used between 0.3 V and 1.8 V can be used from 0.3 V to 1.8 V, and effectively uses the energy stored in the capacitor 4.

Next, a multi-stage boosting charging circuit 6, a voltage detecting circuit 7 in the present embodiment. A specific embodiment of the control circuit 8 will be described.

FIG. 4 shows a basic form of the multi-stage boosting charging circuit 6, and FIG. 5 specifically shows the operation thereof.
(A) is a step-up operation, and (B) is a charging operation. The capacitors 4 and 6 in FIGS. 4 and 5 deviate from those in FIG. 2, and the capacitors 21 and 22 are auxiliary capacitors for boosting. Tr1 to Tr7 in FIG. 4 are FETs, and play the role of a switch for boosting the voltage. In FIG. 4, in order to make vsss'1 and vss2 the same potential without boosting, Tr3 and Tr4 may be turned on and the others may be turned off.

FIG. 5A shows this state.
This is an operation at t0 to t1 in FIG. Also, t1 to t
In order to perform the 1.5-time boost charging in Step 3, Tr1, Tr3 and Tr6 are turned on at the time of boosting and the others are turned off, and T
r2, Tr4, Tr5, Tr7 are turned on and others are turned off.

Similarly, in order to perform double boost charging at times t3 and t4, Tr1, Tr3, Tr5 and Tr7 are turned on during boosting and the others are turned off. In order to perform the operation and further perform the triple boosting at t4 to t5, the same operation as the double boosting charging is performed at the time of boosting, and Tr2, Tr4, Tr6 are turned on and the others are turned off at the time of charging. . When each FET is controlled as described above, the state shown in FIG. 5 is obtained, and each boosting charge becomes possible. FIG. 6 shows an embodiment of the multi-stage boosting charging circuit 5 that specifically realizes the above with an electronic circuit. 6, capacitors 4, 6, 21, and 22 and FETs Tr1 to Tr7 are the same as those in FIG. However, Tr5, Tr6, T
r7 is a P-channel FE because the current flows in both directions.
T and N channel FETs are combined. Also, φ
cl is a boost charging clock, which boosts when the logic level of the signal is "L" and performs charging when it is "H".

Therefore, the circuit repeats boost charging in accordance with the cycle of φcl. AmpN, Amp1.5, Amp2, A
mp3 is a signal indicating a boosting factor, and when "H", indicates no boosting, 1.5-fold boosting, 2-fold boosting, and 3-fold boosting, respectively. Also, 61-
Reference numeral 64 denotes a known logic gate, and the ON / OFF timing of the FETs Tr1 to Tr7 is made by these gates, and the operation described with reference to FIGS. 4 and 5 is performed.

Next, FIG. 7 shows a specific example of the voltage detection circuit 7. sp 'is a sampling signal, and when "H", the circuit operates, and when "L", the circuit state is fixed so that current is not consumed. The inside of the broken line is a known constant voltage circuit, and its output voltage is represented as VREG. R1 and R2 are resistors, and have a maximum voltage of 1.8V of | VSS1 |

[0021]

(Equation 1)

Are set so as to satisfy the following. r1,
r2, r3, and R are similarly resistors, and | VS
The potential of the | VM | tap when S′1 | becomes 0.6 V, 1.8 V, and 1.2 V is set to be the same.

One of the three tap potentials is selected by the transmission gate 71 (VREGT),
The data is compared with VM by the comparator 72. Comparator 7
2 is configured to output “H” when VM is lower than the selected tap potential, and to output “L” when the opposite is true and when SP ′ is “L”. Output co
mp is sent to the control circuit 8.

T1.5, T2 and T3 are signals for selecting a transmission gate and are formed by the control circuit 8, and when "H", the transmission gate is turned on.
With the above configuration, VM and VREGT are compared, and the result (comp) and the transmission selection signal (T1.
5, T2, T3), vss'1 is t0 to t in FIG.
5 can be determined. This determination is made in the control circuit 8 described later.

FIG. 8 shows a specific example of the control circuit 8, and FIG.
Is a timing chart. The timing chart shows that the left side of the wavy line indicates that the 1.5 ×
A transition to the double boost control state is shown, and the movement of each signal when shifting from the double boost state to the state without boost is shown on the right side of the wavy line x. In FIG. 8, 91,
94 is a D-type flip-flop that latches data at the falling edge of CL, 92 is a master latch that holds data when CL is "L", 93 is a 2-bit binary counter, and the other are known gates. Here, the operation of this control circuit will be described along the left side of the timing chart wavy line. First, before the sampling pulse SP becomes “H”, the boosting ratio is 1.5 times and the transmission gate selection signal is T1.5 which is “H”. The states are the master latch 92 and the binary counter 93, respectively.
Is remembered. Now, at the same time that the sampling pulse SP is output, a Reset signal is output, the binary counter 93 is reset, and the state returns to the initial state where T3 becomes "H". After that, comparator output comp by CP pulse
T3, T2, and T1.5 are sequentially selected until becomes "L". The voltage of the large-capacity capacitor 4 | vss'1 |
Is between 0.6 V and 0.8 V (t3 in FIG. 1).
7 to t4), as can be understood from the description of FIG. 7, when T2 becomes “H”, the potentials of VM and VREGT are inverted and c
omp becomes “L”. Therefore, this causes vss'1
Can be determined. Because the detection voltage of T3 is 0.6
V, and the detection voltage of T2 is 0.8 V. If the output of the comparator is inverted during this period, | VSS1
Can be defined to be 0.6V to 0.8V. When | VSS'1 | is 1.2 V or more, T
1.5 is “H” and comp remains “H”.
When comp becomes "L", the subsequent CP pulse is prohibited, and the state of the transmission gate selection signal is stored in the binary counter 93. Also, | VSS '
When 1 | is 1.2 V or more, T1.5 is "H" and comp remains "H". Therefore, how many times the voltage should be boosted can be determined based on the contents of the binary counter and the output of comp when the CP pulse has been output. The decision is made by the D-type flip-flop 94, the master latch 92, and some gates, and the operation is performed at the fall of SP.

As described above, according to the present embodiment, the operable time of the timepiece is extended from time t2 to time t5 in FIG. According to the present embodiment, the voltage of the capacitor 2 which can only be used between 0.9 V and 1.8 V can be used between 0.3 V and 1.8 V, and the energy stored in the capacitor 2 can be stored. It is clear that you are using it effectively.

Further, in this embodiment, the booster has three types of booster means of 1.5 times, 2.0 times and 3.0 times in 5 in FIG. However, the present invention is not limited to these three types, and one type or multiple types may be prepared, and various magnifications may be considered. In this embodiment, the voltage is detected by detecting the voltage of the capacitor 4 (1.8,
Of course, a method of detecting the voltage of the capacitor 6 (1.8 V, 1.2 V) (1.8 V, 1.2 V) and comparing the contents of the booster 5 to determine the boost state is also possible. This method has an advantage that the detection voltage may be small.
In addition, the power generation unit 1 is not limited to a solar battery, and may be anything that generates power. In addition, as described above, the effects of the present invention are not lost even when a normal battery is formed by combining 1 and 2.

In FIG. 1, the clock stops when v'ss1 is between 0.3 V and OV, and the oscillation circuit of the clock stops the oscillation. When the oscillation stops, the clock signal for boosting stops being generated, so that the boosting operation also stops. If the solar cell 1 and the charging circuit are connected in this state, even if the solar cell is irradiated with light, current flows only into the charging circuit, and the oscillation circuit does not immediately oscillate. As a result, the booster circuit also operates. You don't need a clock. In order to solve such a problem, when the oscillation of the oscillation circuit stops, the connection between the solar cell and the charging circuit may be disconnected, and the solar cell and the oscillation circuit may be directly connected.

A specific example will be described with reference to the example of FIG.

In FIG. 9, reference numeral 2 denotes a clock circuit. The limiter circuit 2 in FIG. 2 is removed for simplification of description, and the multi-stage booster circuit 5, the voltage detection circuit 7, and the control circuit 8 are simplified as a booster circuit 119 and a logic circuit 118.

Hereinafter, the power supply control will be described with reference to FIG.
First, the secondary battery 1O3 (condenser) is set to a low voltage state (0.3 V or less).

If the oscillation signal 123 of the oscillation circuit 108 is oscillating, the oscillation stop detection circuit 117 detects the stop, the control signal 113 becomes L, the transmission gate 114 is turned on, and the transmission gates 115 and 10
5 becomes OFF.

Therefore, the power supply 120 of the oscillation circuit 108
Are turned off with the boosted power supply 121 by the booster circuit 119 and turned on with the solar cell side power supply 122.
When light is applied to the oscillation circuit 108, the oscillation stop detection circuit 11
7. An oscillating voltage is supplied to the logic circuit 118 to start oscillating. When the oscillation starts, a boosting clock 124 necessary for boosting is generated, and the boosting circuit 119 operates as a secondary battery 1O3.
, And a high voltage is generated in the boost power supply 121.
On the other hand, when the oscillation starts, the transmission gate 114 is turned off and the transmission gate 11 is turned off.
Since the clocks 5 and 105 are turned on, the power supply system of the clock circuit 102 operates the clock circuit 102 by the high voltage obtained by the solar cell 101 charging the secondary battery 1O1 and boosting the voltage of the secondary battery 1O3. That is, even if the voltage of the secondary battery is low, the watch operates immediately.

[0034]

As described above, according to the present invention, in an electronic timepiece having a power supply having a discharge characteristic with a large voltage fluctuation, the electrical time of the electronic timepiece can be minimized by minimizing energy loss.
In other words, electrical energy can be used very effectively. As a result, it is possible to use a capacitor as a power source of a watch with a solar battery that does not require battery replacement, and to dramatically increase the duration thereof. Also, batteries such as alkaline manganese batteries and lithium batteries can be utilized with little energy loss.

[Brief description of the drawings]

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a view for explaining the discharge performance of a capacitor and the effect of the present invention.

FIG. 2 is a block diagram of an embodiment according to the present invention.

FIG. 3 is a diagram showing a conventional example.

FIG. 4 is a diagram showing a basic form of a multi-stage booster circuit.

FIGS. 5A to 5D are diagrams showing specific examples of the operation in FIG. 4; 5 (B) to 5 (D), (A) shows a boosting operation, and (B) shows a charging operation.

FIG. 6 illustrates an embodiment as an electronic circuit.

FIG. 7 is a diagram showing a specific example of a voltage detection circuit.

FIG. 8 is a diagram showing a specific example of a control circuit.

FIG. 9 is a timing chart of a control circuit.

FIG. 10 is a block diagram showing an application example of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Solar battery 2 Limiter circuit 4 Condenser 5 Booster means 9 Watch body

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[Procedure amendment]

[Submission date] May 16, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention] Electronic clock

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric
The present invention relates to a configuration of a power supply unit in an electronic timepiece using energy as an energy source. In particular, the present invention relates to an improvement in a power supply unit of an electronic timepiece having a power supply in which the discharge characteristics of the power supply are not flat and the voltage changes as the discharge proceeds.

[0002]

2. Description of the Related Art A conventional electronic timepiece using electric energy as an energy source, such as a quartz timepiece, uses a power supply having a flat discharge characteristic such as a silver battery in a power supply unit. This
Ri, I had the energy of the power to take full advantage.

[0003] However, silver batteries are expensive, and the batteries themselves are expensive.
The drawback was that the product had a long life .

[0004] In recent years, alkaline manganese batteries and the like have been used as a solution to these problems , and a solar battery is used as a power source in terms of the life of the battery itself.
Watches using high-capacity capacitors as secondary batteries have also been proposed.

[0005]

In the above technique, the alkaline manganese battery does not have a flat discharge characteristic and has a large amount of energy even after the operation of the watch is stopped. It cannot be said that there is. or,
In the case of using a high-capacity capacitor as a secondary battery, the duration of time until the clock stops is naturally determined by the discharge characteristics of the capacitor, which is a major problem for practical use. Was.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and to make full use of the electric energy of the power supply even if a power supply that waits for non-flat discharge characteristics is used.

[0007]

[Means for Solving the Problems ] To solve the above-mentioned problems.
Therefore, the present invention is based on externally applied energy.
Electronic timepiece with a built-in power generation means
The first battery charged by the power generation means via the rectification means.
Capacitor from the first condenser
And a second capacitor for charging the second capacitor.
A clock circuit that uses the terminal voltage of the sensor as a power supply voltage;
Detection for detecting the terminal voltage of the first or second capacitor
Means and energy stored in the first capacitor
And based on the detection voltage of the detection means.
The terminal voltage of the second capacitor exceeds a certain voltage.
And a boosting means for controlling the pressure within a range that does not exist.
Is the difference between the first capacitor and the boosting capacitor.
Switching connection repeatedly at a predetermined clock timing
Charging the second capacitor by
It is characterized by. According to the present invention, provided from outside
A second power generator with built-in power generation means for generating power based on energy
There is a clock circuit that uses the terminal voltage of the capacitor as the power supply voltage.
In electronic timepieces, the first condenser is
More charged through the rectifying means, the second capacitor
Energy is charged from the condenser 1 and the detecting means
Detects the terminal voltage of the first or second capacitor,
The boosting means includes a first capacitor and a boosting capacitor.
Connection is repeatedly switched at a predetermined clock timing
By charging the second capacitor
Boosts the energy charged in the first capacitor
And the second capacitor based on the detection voltage of the detection means.
The control is performed so that the terminal voltage of the sensor does not exceed a certain voltage.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings according to an embodiment.

In this embodiment, a solar power generation mechanism is used.
This is a timepiece that uses an electric double layer capacitor that is a high-capacity capacitor as a secondary battery using batteries .

FIG. 1 shows the discharge characteristics of the electric double layer capacitor, and FIG. 2 is a block diagram of an embodiment according to the present invention. FIG. 3 is a circuit diagram of a conventional system.
You. In FIG. 3, power generation by the solar battery 1
The power is charged to the electric double layer capacitor 12 and
When charged up, the limiter switch 13 closes and
The charging of the capacitor 12 is stopped. Clock body 14 is a saw
The battery 11 or the condenser 12 operates as a power supply. The diode 15 is a backflow prevention diode that prevents current from flowing into the solar battery when the generated electromotive voltage of the solar battery 11 becomes equal to or lower than the charging voltage of the capacitor 4.

The discharge characteristics of the capacitor 12 after the solar battery 11 is no longer exposed to light when the capacitor 12 is fully charged are shown by the solid line V _SS2 and the broken line in FIG.
V _SS ' ₁ . The vertical axis is the voltage of the condenser 12,
The horizontal axis is time. Condenser in this embodiment
Has a rated voltage of 1.8V. In addition, the clock stop operation
The pressure is 0.9V. At this time, the operation of the watch is
It will stop at t ₂ hours after no light hits Lee .

[0012] Figure 2 is a block diagram of one embodiment according to the present invention, light is irradiated occurs solar battery 1
The electric power is transferred to the electric double layer through the backflow prevention diode 3.
The capacitor 4 is charged. At this time, the solar battery
When the generated electromotive voltage ( _VSS1 ) of -1 exceeds the rated voltage,
The miter circuit 2 works to stop charging the capacitor 4.
For example, the rated voltage is the rated voltage of the capacitor 4.
The limiter circuit is composed of a constant voltage diode.
Energize and charge when middle V _{DD -VSS1} exceeds rated voltage
Current bypass or _switch between V _{DD and} V _SS1
And has a configuration to bypass the charging current by detecting a reference voltage .

The electric power charged in the condenser 4 is multi-stage.
Optimum boosting is performed by boosting charging circuit 5 and capacitor
-6. A detailed description of this operation will be described later.
The capacitor 6 serves as a power supply for a voltage detection circuit 7 for detecting the voltage V _SS ′ ₁ of the capacitor 4, a control circuit 8 for causing the boost charging circuit to perform optimal boost charging based on the voltage detection output, and a clock circuit 9. I have.

[0014] The next operation of the present embodiment, with reference to FIG. 1
This will be described in detail. Here, the broken line in FIG.
Shows the absolute value of the voltage V _SS ' ₁ of the capacitor 4 and the solid line
Indicates the absolute value of the voltage V _SS2 of the capacitor 6. Conde
After the sensor 4 is fully charged, the solar battery 1
Explain when you are no longer hit. Electricity of condenser 4
When the voltage | V _SS ' ₁ | is equal to or higher than 1.2 V, the capacitor 4 and the capacitor 6 have the same voltage as the booster charging circuit 5.
Works.

The voltage | V _SS ' ₁ | of the capacitor 4 is equal to 1.2.
When the voltage is between V and 0.8 V, the voltage is doubled by the boosting charging circuit 5
To charge the capacitor 6. In the section of Figure 1t ₁ ~t ₃
is there. Therefore, the voltage of the capacitor 6 at this time | _VSS2
Is 1.8V to 1.2V. Voltage of condenser 4
When | V _SS ' ₁ | is 0.8V to 0.6V, the boost charging circuit 5
The voltage is boosted twice more, and the capacitor 6 is charged. FIG.
In a period of t ₃ ~t _4. The condenser at this time
6 of the voltage | V _SS2 | becomes 1.6V~1.2V. Conde
When the voltage | V _SS ' ₁ |
Charge the capacitor 6 by boosting it three times by the electric circuit 5
You. A t ₄ later in FIG. 1.

As described above, according to the present embodiment, the voltage | _VSS2 | of the capacitor 6, which is the actual power source of the timepiece, is reduced to 0.9 V or more by the boost charging means.
The clock operable time is shown in FIG.
It is extended from t ₂ hours to t ₅ hours Te. Also, conden
Speaking of the voltage of the circuit 4, it was between 0.9V and 1.8V
Although it could not be used, according to the present embodiment, 0.3 V
To 1.8V, and the energy stored in the condenser 4
We use energy effectively .

Next, the multi-stage boost charging circuit in the present embodiment
6, specific embodiments of the voltage detection circuit 7 and the control circuit 8 will be described.

FIG . 4 shows a basic form of the multi-stage boost charging circuit 6.
FIG. 5 specifically shows the operation.
(A) is a step-up operation, and (B) is a charging operation. FIG. 4, FIG.
The condensers 4 and 6 of FIG. 5 are those of FIG.
The circuits 21 and 22 are auxiliary capacitors for boosting. Ma
And, T _r1 through T _r7 in FIG. 4 is a FET, and performs a boosting
Plays the role of a switch. In FIG.
To make V _SS ' ₁ and V _{SS2 the} same potential, _{Tr 3} and
_Tr4 may be turned on and the others may be turned off.

[0019] shows this state is FIG. 5 (A), the
Is an operation in t ₀ ~t ₁ in Figure 1. In addition, the t ₁ ~t ₃
In order to perform the 1.5-time boost charging, the voltage T _r1 at the time of boosting,
Turn on _Tr3 and _Tr6 , _turn off others, and charge _Tr2 , _Tr4 , T
Turn on _r5 and _Tr7 and _turn off others.

[0020] carried out in the same manner as in t _3, t ₄ at 2-fold step-up charge
In order, the other is ON the boosting time _{T r1, T r3, T r5} , T r7
OFF, when charging, the same operation as when charging 1.5 times boost
No rows, for further t ₄ ~t ₅ o'clock triple boosting is
At the time of boosting, the same operation as during boosting at the time of double boost charging is performed.
There, turning OFF the other ON the T _r2, T _r4, T _r6 at the time of charging. When each FET is controlled as described above, the state shown in FIG. 5 is obtained, and each boosting charge becomes possible.

The above-described multi-stage assembling specifically realized by an electronic circuit
One embodiment of the pressure charging circuit 5 is shown in FIG. Figure 6
Condenser 4,6,21,22 Te and the FET-T _r1 ~T
_r7 is the same as in FIG. Where T _r5 , T _r6 , T
_r7 is P-channel FET because current flows in both directions
And an N-channel FET. Also,φ _CL
Is a boost charge clock, and the logic level of the signal is "L"
At this time, boosting is performed, and at "H", charging is performed. Follow
Thus, the circuit repeats boost charging in accordance with the cycle of φ _CL .

AmpN, Amp1.5, Amp2, Amp
Reference numeral 3 denotes a signal indicating a boosting factor.
No boost, 1.5 times boost, 2 times boost, 3 times boost,
The signal is formed by the control circuit 8. Also, 61 to 64
A known logic gates, T _r1 by these gates
The ON and OFF timings of the FETs up to Tr7 are _generated , and the operation described with reference to FIGS. 4 and 5 is performed.

Next, FIG. 7 shows a specific example of the voltage detection circuit 7.
You. SP 'is a sampling signal and a circuit when "H"
Operates, and when "L", the circuit
Fix the state. The inside of the broken line is a known constant voltage circuit,
The output voltage is represented as V _REG . R ₁ and R ₂ are resistors
With | V _SS ' ₁ | maximum voltage of 1.8V,

(Equation 1) Is set to satisfy. r ₁ , r ₂ , r ₃ , R
Are also resistors, and | V _SS ' ₁ | is 0.6 V,
The potential of the | V _M | tap at 1.8 V and 1.2 V is set to be the same.

[0024] The three-tap potentials, one by transmission gates 71 is selected (V _REGT), con
It is compared with the V _M in separator 72. Comparator 72
, Rather than tap the potential V _M is selected if a low potential
"H" is output, and when the opposite is true and SP 'is "L"
Is configured to output “L”, and its output Co
mp is sent to the control circuit 8.

T _1.5 , T ₂ and T ₃ are transmission gears.
A signal for selecting a signal, which is formed by the control circuit 8 and is "H".
The transmission gate to ON. Configuration above
By comparing V _M and V _REGT , the result (Comp)
And the transmission selection signals (T _1.5 , T ₂ , T ₃ )
V _{SS '1} in state becomes possible to determine whether to present in any of the t ₀ ~t ₅ of FIG. This determination is made by a control circuit 8 described later.
Perform at

FIG. 8 shows a specific example of the control circuit 8, and FIG.
Is a timing chart. Timing chart
Is doubled from the 1.5x boost control state on the left side of the wavy line
A transition to the boost control state is shown, and the movement of each signal when shifting from the double boost state to the state without boost is shown on the right side of the wavy line X. 8, 91, 9
Reference numeral 4 denotes a D-type flip-flop for latching data at the falling edge of CL, reference numeral 92 denotes a master latch which holds data when the CL is "L", reference numeral 93 denotes a 2-bit binary counter, and others are known gates.

Here, on the left side of the wavy line of the timing chart,
Next, the operation of this control circuit will be described. First, sample
The state before the switching pulse SP becomes “H” is the boost ratio.
1.5 times, the transmission gate selection signal is T _1.5
"H", and the state of each
Is stored in the binary counter 93. Now, simultaneously with the output of the sampling pulse SP, Reset
When a signal is output, the binary counter 93 is reset and T ₃
Returns to the initial state in which is set to “H”. Thereafter, until the comparator output Comp becomes “L” due to the CP pulse,
T ₃ , T ₂ , and T _1.5 are selected.

Now, the voltage of the large-capacity capacitor 4 | V _SS ' ₁ |
There will have to allow between 0.6V~0.8V (t ₃ in FIG. 1
t during _4), as can be seen from the description of Figure 7, T ₂ is "H"
When the potential of V _M and V _REGT are reversed, Comp becomes
It becomes "L". Therefore, this determines the range of V _SS ' ₁
it can. Because the detection voltage of T ₃ is 0.6 V, the detection voltage of T ₂
Since the detection voltage is 0.8V, the comparator
If the output is inverted, | V _SS ' ₁ | becomes 0.6V to 0.8V
It can be specified that Also, | V _SS ' ₁ |
When the voltage is 1.2 V or more, T _1.5 is “H” and Comp is also
It remains at "H". When Comp becomes "L", subsequent CP pulses are prohibited, and the state of the transmission gate selection signal is stored in the binary counter 93.

When | V _SS ' ₁ | is 1.2 V or more
Is that _T1.5 is "H" and Comp remains "H"
You. Therefore, when the CP pulse ends, the binary
Depending on the contents of the counter and the output of Comp , how many times the voltage should be boosted can be determined. The decision is made by the D-type flip-flop 94, the master latch 92, and some gates, and the operation is performed at the fall of SP.

As described above, according to the present embodiment ,
T ₅ hours t ₂ hours 1 uptime in total or
Stretched out. In terms of the voltage of the capacitor 4,
The one that could only be used between 0.9V and 1.8V
According to the embodiment, it can be used from 0.3V to 1.8V.
It is clear that the energy stored in Denser 4 is being used effectively.

In the present embodiment, the booster in FIG.
5, 1.5 times, 2.0 times, and 3.0 times booster
Means, which is connected to an electric signal by the voltage detection unit 12.
The present invention is limited to these three types.
Not only one kind but also many kinds
Various magnifications are also conceivable.

In this embodiment, the voltage is detected by a capacitor.
-4 is detected (1.8, 1.2, 0.8, 0.8).
6V) detects the voltage of the capacitor 6 (1.8V,
1.2V) to determine the boost state compared to the contents of the booster 5
A method of course is also possible. This method requires less detection voltage.
There is a merit that there is no need. The power generation unit 1 is a saw.
Anything can be used as long as it generates electricity as well as a battery . In addition, as described above, the effects of the present invention are not lost even when a normal battery is formed by combining 1 and 2.

In FIG. 1, the clock stops when V _SS '1 is between 0.3 V and 0 V , and the oscillation circuit of the clock stops the oscillation. When the oscillation stops, the clock signal for boosting stops being generated, so that the boosting operation also stops. If the solar cell 1 and the charging circuit are connected in this state, even if light is irradiated on the solar cell, current flows only into the charging circuit and the oscillation circuit oscillates immediately .
Can not Rukoto, as a result, the step-up circuit and clock is required because it does not operate. In order to solve such a problem, when the oscillation of the oscillation circuit stops, the connection between the solar cell and the charging circuit may be disconnected, and the solar cell and the oscillation circuit may be directly connected.

A specific example will be described with reference to the example of FIG.

In FIG. 10, reference numeral 102 denotes a clock circuit. The limiter circuit 2 in FIG. 2 is removed for simplification of description, and the multi-stage booster circuit 5, the voltage detection circuit 7, and the control circuit 8 are simplified as a booster circuit 119 and a logic circuit 118.

The power supply control will be described below with reference to FIG.
You. First, the secondary battery 103 (condenser) is in a low voltage state
(0.3 V or less).

Assuming that the oscillation signal 123 of the oscillation circuit 108 is oscillating, the oscillation stop detection circuit 117 detects the stop, the control signal 113 becomes L, the transmission gate 114 is turned on, and the transmission gates 115 and 10 are turned on.
5 becomes OFF.

[0038] Therefore, the power supply of the oscillation circuit 108 120
Are turned off with the boosted power supply 121 by the booster circuit 119 and turned on with the solar cell side power supply 122.
When light is applied to the oscillation circuit 108, the oscillation stop detection circuit 11
7. An oscillating voltage is supplied to the logic circuit 118 to start oscillating. When oscillation starts, the boost clock required for boost
124 is generated, and the booster circuit 119
, And a high voltage is generated in the boost power supply 121.

On the other hand, since the transmission gate 114 is turned OFF and the transmission gates 115 and 105 are turned ON by the start of oscillation, the clock circuit 10
In the second power supply system, the solar battery 101 charges the secondary battery 103
Then , the clock circuit 102 operates by the high voltage obtained by boosting the secondary battery 103 . That is, even if the voltage of the secondary battery is low, the watch operates immediately.

[0040]

As described above , according to the present invention,
Power generators that generate electricity based on energy provided from outside
The terminal voltage of the second capacitor is set as the power supply voltage
In an electronic timepiece having a clock circuit,
The sensor is charged by the power generation means through the rectification means,
Energy from condenser 2 and condenser 1
Is charged, and the detecting means is connected to the first or second capacitor.
The terminal voltage is detected, and the boosting means boosts the voltage with the first capacitor.
The connection with the capacitor for the voltage
To the second capacitor by repeatedly switching
Charging the first capacitor by charging
Energy, and based on the detection voltage of the detection means.
And the terminal voltage of the second capacitor does not exceed a certain voltage.
Wait for non-flat discharge characteristics
Even if a power supply is used, the electric energy of the power supply is sufficient
Can be used. That is, its electrical et an electronic timepiece having a power supply with a large discharge characteristics of the variation of the voltage
Energy loss can be minimized, in other words, electrical energy can be used very effectively . This
For example, by using a capacitor as a power source for a watch with a solar battery that does not require battery replacement, it is possible to dramatically extend the duration thereof. In addition, alkaline manganese batteries and lithium batteries
Such a battery of Umm battery can be utilized also energy loss is also reduced.

[Brief description of the drawings]

[1] Effect illustration by discharge electric characteristics and the present invention of a capacitor.

FIG. 2 is a block diagram of an embodiment according to the present invention.

FIG. 3 is a diagram showing a conventional example.

FIG. 4 is a diagram showing a basic form of a multi-stage booster circuit.

FIGS. 5A to 5D are diagrams showing specific examples of the operation in FIG. 4; 5 (B) to 5 (D), (A) shows a boosting operation, and (B) shows a charging operation.

FIG. 6 illustrates an embodiment as an electronic circuit.

FIG. 7 is a diagram showing a specific example of a voltage detection circuit.

FIG. 8 is a diagram showing a specific example of a control circuit.

FIG. 9 is a timing chart of a control circuit.

FIG. 10 is a block diagram showing an application example of the present invention.

[Description of Signs] 1 Solar battery 2 Limiter circuit 4 Capacitor 5 Boosting means 9 Watch body

Claims (1)

[Claims] 1. A power supply comprising at least a power supply A and a power supply B having a smaller electric energy than the power supply A, wherein at least the power supply B is chargeable and supplies electric energy from the power supply A to the power supply B. An electronic timepiece comprising: means for supplying electric energy from the power supply A to the power supply B; and means for changing a voltage level between the power supply A and the power supply B.