JPH1051004A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the effect due to a size error in high resistance regions in the case that there exists an essential alignment error. SOLUTION: The device has an active layer having two source regions 105, 108 and a drain region 107 and has high resistance regions 113, 114 adjacent to the drain region 107. Through the configuration above, even when there is any error caused in the size of the high resistance regions 113, 114, the effect of the size error that is caused when the polarity of a signal voltage applied to the source regions 105, 108 is inverted is reduced. That is, the symmetry of the path from the source to the drain and from the drain to the source is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a structure of a thin film transistor. In particular, the present invention relates to a thin film transistor having excellent symmetry of operation with respect to a signal whose polarity is inverted.

[0002]

2. Description of the Related Art Conventionally, thin film transistors formed on a glass substrate or a quartz substrate have been known. The thin film transistor can be used for a liquid crystal display device and various integrated circuits.

FIG. 4 shows a thin-film transistor having a general configuration as viewed from above.

In FIG. 4, reference numeral 11 denotes a source contact, and reference numeral 12 denotes a source region. Reference numeral 15 denotes a drain contact, and reference numeral 14 denotes a drain region. Also one
3 is a channel formation region. Reference numeral 18 denotes a gate electrode disposed in a channel formation region via a gate insulating film (not shown).

[0005] Reference numerals 16 and 17 denote low-concentration impurity regions arranged adjacent to the channel forming region 13. The low-concentration impurity region contains an impurity imparting a conductivity type at a lower concentration than the source and drain regions.

Generally, the lightly doped region 17 on the drain region side is called an LDD (lightly doped drain) region.

The reason why the low concentration impurity region is provided is to reduce the OFF electric current and suppress the deterioration by relaxing the high electric field formed between the channel region and the drain region.

[0008]

Generally, a thin film transistor handles a signal of a high frequency (frequency in the MHz band or higher). Depending on the operation mode, an operation may be required in which the polarity of the voltage applied between the source and the drain is inverted at a predetermined cycle.

When such an operation of inverting the polarity is performed (referred to as an inversion operation), the roles of the source region 12 and the drain region 14 in the configuration shown in FIG. Become. Hereinafter, for convenience, 12 is defined as a source region and 14 is defined as a drain region.

In order to form the low-concentration impurity regions 15 and 16, a method of selectively varying the amount of impurity ions implanted into the active layer using a resist mask is used.

In this case, the dimensions of the low-concentration impurity regions 15 and 16 are slightly different due to a deviation in mask alignment accuracy in the photolithography process. If the substrate area is small, this deviation is negligible, but in an active matrix type liquid crystal display device or the like having a large area, the deviation of the above dimensions is on the order of μm.

Generally, the dimensions of the low concentration impurity region in FIG.
It is about 1-2 μm. Therefore, the low concentration impurity region 16
17 and 17 are greatly affected by the mask alignment accuracy.

In such a case, the dimensions of the low-concentration impurity regions 15 and 16 differ greatly from each other.

As a result, the resistances of the low-concentration impurity regions are different from each other, and the symmetry of operation when the signal voltage applied to the source region 12 is inverted is broken.

For example, the thin film transistor shown in FIG.
Channel type. It is also assumed that only 16 low-concentration impurity regions exist. (It is assumed that 15 low-concentration impurity regions do not exist)

That is, it is assumed that the resistance between the source / channel and the resistance between the drain / channel are largely different.

In this situation, consider a state where the potential of the source region 12 is lower than the ground level (or a predetermined constant potential). In this case, electrons serving as carriers move from the source region 12 to the drain region 14 by the ON operation. (Operating state A)

On the other hand, consider the case where the polarity of the signal voltage supplied to the source region 12 is inverted with respect to the operation state A. In this state, electrons serving as carriers move from the drain region 14 to the source region 12 by the ON operation. (Operating state B)

In the inverted operation state B, the roles of the source region 12 and the drain region 14 are reversed with respect to the operation state A.

In this case, it is assumed that the low concentration impurity region 16 is arranged only on the drain region side. Therefore, the operating impedance of the thin film transistor differs between the operation state A and the operation state B.

This is because the path of the moving carrier is different in the two operating states. That is,
In the operation state A, carriers (electrons) enter the channel region 13 from the source region 12 (in this case, the region 16 is set to be absent), and further pass through the low-concentration impurity region 17. The path to the drain region 14 is moved.

On the other hand, in the operating state B, carriers (electrons) flow from the drain region 14 to the low-concentration impurity region 1.
7, the channel region 13 and the drain region 1
Move the route to 2.

In an insulated gate field effect transistor, whether a high resistance region such as a low concentration impurity region is on the carrier inflow side or outflow side with respect to the channel depends on the operating state. Make a big difference.

Therefore, in such a case, the operating state of the thin film transistor becomes different because the polarity of the signal voltage supplied to the source region 12 is inverted. This is because the low concentration impurity region is arranged only on the drain region 14 side. (Here is such a setting)

This phenomenon is caused by the low concentration impurity regions 16 and 17
This also occurs when the dimensions of are different.

Such a situation becomes a problem when the same information is handled and the operation is performed with the polarity of the signal inverted.

The above problem also occurs due to the inevitable misalignment of the mask.

An object of the invention disclosed in this specification is to provide a technique for suppressing the collapse of the symmetry of the operation of the thin film transistor caused by the misalignment of the mask.

[0029]

One of the inventions disclosed in the present specification includes two source regions 105 and 108, two channel regions 115 and 116, as shown in FIG. An active layer in which one drain region 107 and two high-resistance regions 113 and 114 disposed between the channel region and the respective drain regions are formed. 112
, And a common drive signal is supplied to the two channel regions from the gate electrodes 103 and 104.

In the above structure, the high-resistance region is a low-concentration impurity region doped with an impurity imparting a conductivity type at a lower concentration than the source and drain regions, or an intrinsic or substantially intrinsic region without doping. It is composed with. That is, the high-resistance region is defined as a region having a higher sheet resistance (lower conductivity) than the source and drain regions.

The number of high resistance regions is not limited to two, and may be arranged on the source region side. That is, a high resistance region may be provided between the channel region 115 and the source region 105 and between the channel region 116 and the source region 108.

The invention disclosed in this specification is based on the high resistance region 1
It is assumed that 13 and 114 are formed by a self-manufacturing process using a mask. Accordingly, individual products (individual products utilizing the invention disclosed herein)
Are caused by misalignment at the time of mask alignment.
The dimensions of the two high-resistance regions indicated by and 114 are different from each other. Especially when the board area becomes large,
That becomes apparent.

The dimensions of the process area are defined as follows.
It is defined as being on a line connecting the source region and the drain region.

In another embodiment of the present invention, two source regions 115 and 116 are provided as shown in FIG.
, One drain region 107 and the source region 10
It is characterized by having two paths from 5 and 108 to the drain region 107, and a plurality of high resistance regions 113 and 114 formed in each of the paths.

In the above configuration, even when the mask is misaligned during the formation of the high-resistance region and the size is misaligned, the sum of the dimensions of the individual high-resistance regions is constant or substantially constant.

For example, if the size of the high-resistance region 113 increases due to misalignment during mask alignment, the high-resistance region 11
The size of 4 becomes smaller. If the misalignment at the time of mask alignment is in the opposite direction, the size relationship is also reversed. The sum of the high resistance regions 113 and 114 is constant irrespective of the misalignment of the mask (although the misalignment is of course limited).

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, by sharing two source regions 105 and 108 and providing two paths from each source region to a drain region 107, high resistance regions 113 and 114 are provided. , The symmetry of operation due to inversion of the polarity of the signal voltage to the source region can be maintained.

In other words, even if the dimensions of the high resistance regions 113 and 114 are large due to misalignment at the time of mask alignment, the other is small, and conversely, one is small and the other is large. The symmetry of the path connecting the source region and the drain region can be maintained. In other words, the path from the source region to the drain region and the path from the drain region to the source region can be made the same regardless of the misalignment of the mask when forming the high-resistance region.

Thus, even when the polarity of the signal voltage applied to the source region is reversed, the symmetry of the operation can be maintained.

[0040]

【Example】

[Embodiment 1] FIG. 1 is a top view of a schematic configuration of this embodiment.

The configuration shown in FIG.
5 and 108. The two source regions 105 and 108 are commonly connected by a wiring 112 via contacts 106 and 109.

Reference numerals 103 and 104 denote gate electrodes, which are shared by the extended portion 101. 102
Is a contact portion to the common gate electrode 101.

A channel region 115 is formed below the gate electrode 103, and a channel region 116 is formed below the gate electrode 104.

Reference numeral 107 denotes a drain region. A pattern indicated by 110 extends from the drain region 107, and a drain electrode is formed at a contact portion indicated by 111.

Sources 113 and 114 represent the source /
This is a high-resistance region (low-concentration impurity region) doped with an impurity that imparts a conductivity type at a lower concentration than the drain region.

In the thin film transistor having the structure shown in FIG. 1, even if the formation position of the high resistance region (here, the low concentration impurity region) is shifted, asymmetry does not appear in the operation of the thin film transistor during the inversion operation due to the influence. Become.

When the formation positions of the high-resistance regions 113 and 114 are shifted, the following two conditions are considered.

(State A) The size of the region 113 is larger than the predetermined size, and the size of the region 114 is smaller than the predetermined size.

(State B) The area of the area 113 becomes smaller than the predetermined size, and the area of the area 114 becomes larger than the predetermined size.

In the thin film transistor shown in FIG.
Even when the polarity of the signal voltage supplied to the source wiring 112 is inverted, in the above-described states (A) and (B),
Operational symmetry is preserved.

This is because the path from the source line 112 to the drain region 110 and the path from the drain region 110 to the source line 1
This is because the path to No. 12 is the same in the states (A) and (B).

As described above, by employing the structure shown in this embodiment, even when the dimensional symmetry of the high resistance regions 113 and 114 is shifted, the operation symmetry can be maintained. .

Hereinafter, a manufacturing process of the thin film transistor shown in FIG. 1 will be described. FIGS. 2A to 2F show a manufacturing process of a cross section cut along the line AA 'in FIG. First, a silicon oxide film is formed on a glass substrate (or a quartz substrate) 201 as a base film (not shown).
A film is formed to a thickness of 2,000 mm by a sputtering method.

Next, an amorphous silicon film (not shown) is formed to a thickness of 500 ° by a plasma CVD method, and the amorphous silicon film is crystallized by irradiating a laser beam. Obtain a membrane.

After obtaining the crystalline silicon film, an active layer indicated by 202 is formed by patterning. In this active layer, a source / drain region, a channel forming region, and a high-resistance region are formed later.

After the formation of the active layer 202, a silicon oxide film is formed as a gate insulating film 203 by a plasma CVD method.

Further, a metal film (not shown) for forming a gate electrode is formed by a sputtering method. Here, a molybdenum silicide film having a thickness of 4000 mm is used as the metal film. As the metal film, an aluminum film, a tantalum film, and various silicide materials can be used. Further, a silicon film having one conductivity type can be used instead of the metal film.

After a metal film (not shown) is formed, patterning is performed to form patterns 103 and 104. FIG. 1 shows a state in which this pattern is viewed from above. Thus, the state shown in FIG. 2A is obtained.

Next, resist masks 204 and 205 are arranged. This resist mask is used to form a low-concentration impurity region functioning as a high-resistance region.

After the resist masks 204 and 205 are arranged, P (phosphorus) doping is performed by a plasma doping method. In this step, 206, 208 and 21
Light doping is performed on the region of 0. Also, 207
And 209 are not doped. Thus, the state shown in FIG. 2B is obtained.

In this embodiment, an example is shown in which P doping is performed to obtain an N-channel type thin film transistor. However, if a P-channel type thin film transistor is obtained, B (boron) doping is performed.

Next, the resist masks 204 and 205 are removed, and P doping is performed again. In this step, FIG.
P doping (light doping) is performed at a lower dose than in the step shown in FIG. As a result, source regions 105 and 108 are formed. Also,
A drain region 107 is formed.

Further, low concentration impurity regions 113 and 114 are formed. Also, channel regions 115 and 116 are defined.

Here, low concentration impurity regions 113 and 114
Is doped with P at a lower concentration than the source regions indicated by 105 and 108. These low-concentration impurity regions function as high-resistance regions.

If this light doping is not performed, the regions 113 and 114 can be used as offset gate regions.

In this embodiment, the high resistance region is formed between the channel region and the drain region. However, if the shape of the mask arranged in the step (B) is changed, A high-resistance region can be provided between the source region and the channel region.

Thus, the state shown in FIG. 2C is obtained. Next, a silicon nitride film 213 and a resin film 214 are used as interlayer insulating films.
Are laminated. Thus, the state shown in FIG. 2D is obtained.

Next, as shown in FIG. 3A, contact holes 106 and 109 are formed. Then, source electrodes 215 and 216 (extending to become source wirings) formed of a stacked film of a titanium film, an aluminum film, and a titanium film are formed.

Source electrodes 215 and 216 extend to source line 112 shown in FIG. That is, the source electrode 21
5 and 216 are commonly connected.

After obtaining the state shown in FIG.
In the hydrogen atmosphere for 1 hour. Thus, a thin film transistor is completed.

Embodiment 2 The invention disclosed in this specification is
It can be used for an active matrix type liquid crystal display panel. Hereinafter, examples of various devices using an active matrix type liquid crystal panel will be described.

FIG. 5A shows a photographing apparatus called a digital still camera, an electronic camera, or a video movie capable of handling moving images.

This device has a function of electronically storing an image taken by a CCD camera (or a suitable photographing means) arranged in the camera section 2002. Then, the captured image is displayed on the liquid crystal display panel 20 disposed on the main body 2001.
03 is provided. The operation of the device is performed by operation buttons 2004. Note that there are two types of liquid crystal panels, one that performs display by irradiating light from a backlight, and the other type, which is a reflective type that performs display by reflecting light from the outside.

FIG. 5B shows a portable personal computer (information processing device). This device is
Openable / closable cover (lid) 21 attached to main body 2101
02 is provided with a liquid crystal display panel 2104, and various information can be input from a keyboard 2103, and various arithmetic operations can be performed.

FIG. 5C shows an example in which a flat panel display is used in a car navigation system (information processing device). The car navigation system includes an antenna unit 2304 and a liquid crystal display panel 230
2 is provided.

Switching of various information required for navigation is performed by operation buttons 2303. Generally, the operation is performed by a remote control device (not shown).

FIG. 5D shows an example of a projection type image display device. In the figure, light emitted from a light source 2402 is optically modulated by a liquid crystal display panel 2403 to form an image. The image is reflected on mirrors 2404 and 2405 and projected on screen 2406.

FIG. 5E shows an example in which a display device called a viewfinder is provided in a main body 2501 of a video camera (photographing device).

The viewfinder is roughly composed of a liquid crystal display panel 2502 and an eyepiece 2503 on which an image is displayed.

The video camera shown in FIG. 5E is operated by the operation buttons 2504 and the tape holder 250 is operated.
The image is recorded on the magnetic tape stored in the storage unit 5. An image captured by a camera (not shown) is displayed on a liquid crystal display panel 2502. The display device 2502 includes
The image recorded on the magnetic tape is displayed.

[0081]

By utilizing the invention disclosed in this specification, the polarity inversion operation which occurs due to mask alignment misalignment which is inevitably generated in the process of manufacturing a thin film transistor having a high resistance region. Can solve the problem of the unbalance operation of the thin film transistor.

[Brief description of the drawings]

FIG. 1 is a diagram showing a state where a thin film transistor of an example is viewed from above.

FIG. 2 is a view showing a cross-section manufacturing step cut along AA ′ in FIG. 1;

FIG. 3 is a view showing a cross-section manufacturing step taken along line AA ′ in FIG.

FIG. 4 is a diagram showing a state where a conventional thin film transistor is viewed from above.

FIG. 5 is a diagram showing an outline of a device using the invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Common gate electrode 102 Contact with gate electrode 103 Gate electrode 104 Gate electrode 105 Source region 106 Contact of source region (contact opening position) 107 Drain region 108 Source region 109 Contact of source region (contact opening position) 110 Drain Pattern extending from region 111 Contact to drain region (contact opening position) 112 Source wiring 113 High resistance region (low concentration impurity region) 114 High resistance region (low concentration impurity region) 115 Channel region 116 Channel region

Claims (7)

[Claims] 1. An active element comprising: two source regions; two channel regions; one drain region; and two high-resistance regions disposed between the channel region and each drain region. A semiconductor device having a layer, wherein the two source regions are connected by a wiring, and a common drive signal is supplied to the two channel regions. 2. The semiconductor device according to claim 1, wherein dimensions of the two high resistance regions are different from each other. 3. The semiconductor device according to claim 1, wherein the dimensions of the two high-resistance regions are different from each other due to a deviation at the time of mask alignment. 4. The device according to claim 1, wherein the two channel regions and the two high-resistance regions are formed between two source regions and on a line connecting the two source regions. Characteristic semiconductor device. 5. A semiconductor device comprising: two source regions; one drain region; two routes from the source region to the drain region; and a plurality of high-resistance regions formed on each of the routes. A semiconductor device characterized by the above-mentioned. 6. The semiconductor device according to claim 5, wherein the sum of the dimensions of the plurality of high-resistance regions is constant or substantially constant irrespective of a deviation at the time of mask alignment. 7. The semiconductor device according to claim 5, wherein the two high-resistance regions are formed between two source regions and on a line connecting the two source regions.