JPH1051005A5 - - Google Patents
Info
- Publication number
- JPH1051005A5 JPH1051005A5 JP1996219314A JP21931496A JPH1051005A5 JP H1051005 A5 JPH1051005 A5 JP H1051005A5 JP 1996219314 A JP1996219314 A JP 1996219314A JP 21931496 A JP21931496 A JP 21931496A JP H1051005 A5 JPH1051005 A5 JP H1051005A5
- Authority
- JP
- Japan
- Prior art keywords
- active layer
- film
- thermal oxide
- oxide film
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Description
【００６６】
まず、基板としては耐熱性の高い石英基板４０１を用意する。勿論、シリコン基板やＳＯＩ構造を有するＳＩＭＯＸ基板等であっても構わない。そして、バッファ層となる酸化珪素膜４０２、結晶性珪素膜４０３を形成する。結晶性珪素膜４０３の形成方法は実施例１に従えば良いが、次の熱酸化処理により膜厚が減少するので、それを考慮して多めに成膜しておく必要がある。[0066]
First, a highly heat-resistant quartz substrate 401 is prepared as the substrate. Of course, a silicon substrate or a SIMOX substrate having an SOI structure may also be used. Then, a silicon oxide film 402 and a crystalline silicon film 403 are formed to serve as buffer layers. The method for forming the crystalline silicon film 403 may be the same as in Example 1, but since the film thickness will be reduced by the subsequent thermal oxidation process, it is necessary to form a larger film in consideration of this.
Claims (4)
前記活性層を覆うゲイト絶縁膜と、
前記ゲイト絶縁膜上に形成されたゲイト電極と、
を少なくとも有する半導体装置において、
前記ゲイト絶縁膜は少なくともその一部に前記活性層を熱酸化して得られる熱酸化膜を有し、
前記熱酸化膜は前記活性層の主表面のみに接して形成されていることを特徴とする半導体装置。an active layer formed on an insulating substrate;
a gate insulating film covering the active layer;
a gate electrode formed on the gate insulating film;
In a semiconductor device having at least
the gate insulating film has, at least in a part thereof, a thermal oxide film obtained by thermally oxidizing the active layer,
The semiconductor device is characterized in that the thermal oxide film is formed in contact only with the main surface of the active layer.
前記活性層を覆うゲイト絶縁膜と、
前記ゲイト絶縁膜上に形成されたゲイト電極と、
を少なくとも有する半導体装置において、
前記ゲイト絶縁膜は少なくともその一部に前記活性層を熱酸化して得られる熱酸化膜を有し、
前記活性層の主表面には前記熱酸化膜が接しており、前記活性層の側面には前記熱酸化膜以外の絶縁膜が接していることを特徴とする半導体装置。an active layer formed on an insulating substrate;
a gate insulating film covering the active layer;
a gate electrode formed on the gate insulating film;
In a semiconductor device having at least
the gate insulating film has, at least in a part thereof, a thermal oxide film obtained by thermally oxidizing the active layer,
The semiconductor device is characterized in that the thermal oxide film is in contact with a main surface of the active layer, and an insulating film other than the thermal oxide film is in contact with a side surface of the active layer.
前記結晶性珪素膜に対して熱酸化処理を施すことにより表面に熱酸化膜を形成し、
前記熱酸化膜を残したまま前記結晶性珪素膜をパターニングして活性層を形成し、
ゲイト絶縁膜を形成する半導体装置の作製方法において、
前記ゲイト絶縁膜を形成するときに前記活性層の主表面には前記熱酸化膜が残存していることを特徴とする半導体装置の作製方法。A crystalline silicon film is formed on an insulating substrate;
a thermal oxidation treatment is performed on the crystalline silicon film to form a thermal oxide film on the surface;
patterning the crystalline silicon film while leaving the thermal oxide film to form an active layer;
1. A method for manufacturing a semiconductor device in which a gate insulating film is formed,
a thermal oxide film remaining on the main surface of the active layer when the gate insulating film is formed;
前記結晶性珪素膜に対して熱酸化処理を施すことにより表面に熱酸化膜を形成し、
前記熱酸化膜を残したまま前記結晶性珪素膜をパターニングして活性層を形成する半導体装置の作製方法において、
前記熱酸化膜をそのままゲイト絶縁膜として用いることを特徴とする半導体装置の作製方法。A crystalline silicon film is formed on an insulating substrate;
a thermal oxidation treatment is performed on the crystalline silicon film to form a thermal oxide film on the surface;
A method for manufacturing a semiconductor device, comprising the steps of: patterning the crystalline silicon film while leaving the thermal oxide film; and forming an active layer;
A method for manufacturing a semiconductor device, characterized in that the thermal oxide film is used as it is as a gate insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21931496A JPH1051005A (en) | 1996-08-01 | 1996-08-01 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21931496A JPH1051005A (en) | 1996-08-01 | 1996-08-01 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1051005A JPH1051005A (en) | 1998-02-20 |
| JPH1051005A5 true JPH1051005A5 (en) | 2004-08-12 |
Family
ID=16733551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21931496A Withdrawn JPH1051005A (en) | 1996-08-01 | 1996-08-01 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1051005A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5998838A (en) | 1997-03-03 | 1999-12-07 | Nec Corporation | Thin film transistor |
| JP4030193B2 (en) | 1998-07-16 | 2008-01-09 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP3643067B2 (en) | 2001-10-11 | 2005-04-27 | 株式会社半導体エネルギー研究所 | Method for designing semiconductor display device |
-
1996
- 1996-08-01 JP JP21931496A patent/JPH1051005A/en not_active Withdrawn
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH1041482A5 (en) | ||
| JPH10189966A5 (en) | ||
| JP2666293B2 (en) | Method for manufacturing MOS transistor | |
| JPS62205664A (en) | Manufacture of thin film transistor | |
| JPH0748491B2 (en) | Method for manufacturing integrated circuit semiconductor device | |
| JPH11354441A5 (en) | ||
| JP2001036078A5 (en) | ||
| JPS5951153B2 (en) | Manufacturing method of semiconductor device | |
| JP2000133590A5 (en) | Manufacturing method of semiconductor devices | |
| JP2568854B2 (en) | Thin film transistor and method of manufacturing the same | |
| JPS6419770A (en) | Semiconductor device | |
| JP3611143B2 (en) | Bonded wafer and manufacturing method thereof | |
| JPS58155767A (en) | Manufacture of metal oxide semiconductor type semiconductor device | |
| JP2945023B2 (en) | Method for manufacturing thin film transistor | |
| JPH01100973A (en) | Manufacture of semiconductor device | |
| JPH02100382A (en) | Field-effect type superconducting transistor and manufacture thereof | |
| JPH11177105A5 (en) | ||
| JPH1064817A5 (en) | ||
| JP2623633B2 (en) | Method for manufacturing semiconductor device | |
| JPS6057968A (en) | Manufacture of mos transistor | |
| JPS6387750A (en) | Manufacture of semiconductor device | |
| JPH02246120A (en) | Manufacturing method of thin film transistor | |
| JPH02209777A (en) | Forming method for tunnel junction element | |
| JPS6081838A (en) | Semiconductor integrated circuit | |
| JPH01287964A (en) | Manufacture of semiconductor device |