JPH1051302A - PLL circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To limit the oscillation range of an oscillator to a suitable range without increasing the master clock frequency to prevent side lock. SOLUTION: Permission and non-permission control (EC) of a change in oscillation frequency (for example, an operation of changing a frequency division ratio) according to error information in an oscillation unit is performed, whereby a frequency signal CKp generated by the oscillation unit is obtained. Limit the frequency range. That is, the oscillation range is limited by not always directly following the change in the frequency division ratio with the error information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, a digital PLL (Phase Locked Loop) circuit capable of obtaining an oscillation frequency signal (clock) synchronized with an input signal.

[0002]

2. Description of the Related Art For example, when reproducing digital data recorded on a recording medium such as an optical disk, a magneto-optical disk, or a magnetic tape, bits are extracted to extract (decode) reproduced data from information read from the recording medium. Clock (so-called bit clock signal) for
Is required. In order to generate such a clock synchronized with the read information, a PLL circuit is generally used.

[0003] Conventionally, PLL circuits have often been formed as analog circuits, but in recent years, digitization of PLL circuits has been advanced. The digital PLL circuit is
This is realized by digitizing the phase error detection unit, the error signal filtering unit, and the clock oscillation circuit unit.

FIG. 5 shows an example of a digital PLL circuit.
In this example, EFM (8-), which is a modulation method adopted in CD (compact disk) and MD (mini disk), is used.
It is assumed that the circuit is a PLL circuit that obtains a clock synchronized with the 14-modulated signal. That is, in a CD or MD reproducing apparatus, from the EFM signal extracted from the disc,
This is a circuit for generating a reproduction clock for the decoding.

[0005] This digital PLL circuit comprises an edge detector 8.
1, phase comparator 82, low-pass filter 83, oscillator 9
It has 0. As the oscillator 90, a limiter 91,
It comprises a counter 92, a decoder 93, and a 分 -minute period 94. The master clock MCK is supplied to the edge detector 81, the phase comparator 82, and the counter 92.
The output of the oscillator 90 is used as a reproduction clock CKp. This reproduction clock CKp is used as a comparison reference signal in the phase comparator 82 and is used as a processing clock for the low-pass filter 83 (digital filter).

[0006] The EFM signal is input to an edge detector 81, and edge timing is extracted. Then, the edge timing detection signal is compared with the phase of the reproduced clock CKp in the phase comparator 82, and phase error information is output. The phase error information is input to the oscillator 90 after being subjected to band limiting processing by the low-pass filter 83.

The oscillator 90 is configured to obtain a reproduced clock CKp synchronized with the EFM signal by changing the frequency division ratio according to the input phase error information. The phase error information is first input to the limiter 91 and is limited to a value of ± 1. That is, the value of the phase error information is “1”.
It will be limited to either "0" or "-1". The output of the limiter 91 becomes the load data of the counter 92.

The counter 92 loads the output of the limiter 91 in response to the load signal LD, and counts up based on the master clock MCK. The next-stage decoder 93 is configured to output “1” when the value of the counter 92 becomes “3”. The "1" output of the decoder 93 is a load signal LD for the counter 92.

The operation of the counter 92 and the decoder 93 will be described with reference to FIG. FIG. 6A shows the master clock MC.
6B shows the output of the limiter 91 at the load timing, FIG. 6C shows the count value of the counter 92, and FIG.
(D) shows the output of the decoder 93.

The output of the decoder 93 becomes "1" when the value of the counter 92 becomes "3", and this becomes the load signal LD. Therefore, the counter 92 outputs the output of the limiter 91 as the next value of "3". Will be done. If the output of the limiter 91 is “0”, the counter 92
Are "0" and "1" based on the master clock MCK.
"2" and "3" are counted up. When the value of the counter 92 becomes "3", the output of the decoder 93 becomes "1", so that the output of the limiter 91 is loaded as the next value of the counter 92.

When the output "1" of the limiter 91 is loaded, the counter 92 counts up to "1", "2", and "3". When the output is "3", the output of the decoder 93 is "1". Becomes When the output “−1” of the limiter 91 is loaded, the counter 92 sets “−1” and “0”.
"1""2""3" count up, "3"
In this case, the output of the decoder 93 becomes "1".

Therefore, as seen from the output of the decoder 93, as shown at the bottom of FIG. 6, when the load value (limiter output) is "0", the dividing ratio is 4, and when the load value is "1", the dividing ratio is 4. When the dividing ratio is 3 and the load value is “−1”, each dividing operation with the dividing ratio of 5 is realized.

FIG. 7 shows the operation of varying the frequency division ratio. T1-T
Numeral 30 indicates the timing on the time axis. As the limiter input, the phase error information from the low-pass filter 83 is shown as a value after the limit. The limiter output is a value serving as load data of the counter 92. In this case, the limiter output has the same value as the value of the upper limiter input. As the limiter input (phase error information) changes at each timing as shown in the figure, the frequency division ratio changes accordingly as shown at the bottom.

The output of the decoder 93 on which the frequency division ratio variable operation has been performed is frequency-divided by a 1/2 frequency divider 94, and
When the pulse duty is set to 50%, the reproduction clock CKp is used. That is, the reproduction clock CKp is E
When the frequency division ratio is varied according to the phase error of the FM signal, the frequency signal is generated so as to converge to a frequency signal synchronized with the EFM signal.

[0015]

The window of the EFM signal is set to 3T to 11T (the continuous length of 0 or 1 is limited to 3 to 11). In the case of such a signal, A condition in which the PLL circuit locks to a frequency different from the frequency to be locked (side lock) easily occurs. In order to prevent side lock, it is necessary to limit the oscillation range of the oscillator.

In the case of an oscillator whose frequency division ratio changes within the range of the frequency division ratio 3 to the frequency division ratio 5, the frequency of the reproduced clock CKp is limited to MCK / 3 to MCK / 10. . Since the master clock MCK / 8 has the center frequency, if this MCK / 8 is fc, the oscillator 9
The oscillation range of 0 is 0.8 fc to 1.33 fc. However, in practice, such an oscillation range is too wide from the viewpoint of prevention of side lock, and the situation is such that side lock easily occurs.

To narrow the oscillation range, the frequency division ratio at the center frequency is larger than "4" in the above example, for example, "8".
For example, "16" or "32" may be used. However, for this purpose, the frequency of the master clock MCK needs to be extremely high, and there is a problem that operation becomes difficult and power consumption increases.

[0018]

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a PLL circuit capable of limiting the oscillation range of an oscillator to a suitable range without increasing the master clock frequency and preventing side lock. The purpose is to provide.

For this reason, in the PLL circuit, an error detecting means for detecting error information with respect to the input signal, and a frequency synchronized with the input signal by changing the oscillation frequency according to the error information, for example, by changing the dividing ratio. An oscillating means capable of generating a signal, and a change in an oscillating frequency according to error information in the oscillating means (for example, an operation for changing a dividing ratio)
Oscillating frequency range limiting means capable of limiting the frequency range of the frequency signal generated by the oscillating means by controlling permission and non-permission of the oscillating means. That is, the oscillation range is limited by not always directly following the change in the frequency division ratio with the error information.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described.
A PLL circuit mounted on a mini-disc reproducing apparatus will be described as an example. 2. Description of the Related Art A mini disc reproducing apparatus is known as an audio data reproducing apparatus using a recordable magneto-optical disc called a mini disc or a read-only optical disc.

FIG. 1 is a schematic block diagram of a reproducing apparatus. Disk 1 on which audio data is recorded (a magneto-optical disk or an optical disk called a mini disk)
Is rotationally driven by a spindle motor 2. The optical head 3 performs a reproducing operation by irradiating the rotating disk 1 with laser light and detecting the reflected light.

To this end, the optical head 3 is equipped with a laser diode as a laser output means, an optical system including a polarizing beam splitter and an objective lens, and a detector for detecting reflected light. The objective lens 3a is 2
It is held by a shaft mechanism 4 so as to be displaceable in the radial direction of the disk and in the direction of coming into contact with and separating from the disk. The entire optical head 3 can be moved in the disk radial direction by a sled mechanism 5.

The information detected from the magneto-optical disk 1 by the optical head 3 by the reproducing operation is supplied to the RF amplifier 7. The RF amplifier 7 calculates the reproduced RF signal, tracking error signal, focus error signal, groove information (absolute position information recorded as a pre-groove (wobbling groove) on the magneto-optical disk 1) and the like by performing an arithmetic process on the supplied information. Extract.

The extracted reproduction RF signal is binarized by the binarization circuit 6 to form a pulse train as an EFM signal, which is supplied to the EFM / CIRC decoder 8. The EFM signal is also supplied to the PLL circuit 10, and the PLL circuit 10
In the circuit 10, the reproduced clock CKp synchronized with the EFM signal
Generate The reproduced clock CKp is EFM / CIR
The signal is supplied to the C decoder 8 and serves as a reference clock for decoding the EFM signal.

The groove information extracted by the RF amplifier 7 is supplied to an address decoder 10. The address decoder 10 generates address data (absolute position information) and an address bit clock from the groove information,
/ CIRC decoder 8. This absolute position information is supplied to a system controller 11 constituted by a microcomputer. The address and other subcode information recorded as data are EF
The M signal is extracted when it is decoded by the EFM / CIRC decoder 8, and its address information and subcode data used for control operations are also supplied to the system controller 11 and used for various control operations.

The tracking error signal and the focus error signal extracted by the RF amplifier 7 are supplied to a servo circuit 9. The servo circuit 9 generates various servo drive signals based on the supplied tracking error signal, focus error signal, track jump command and access command from the system controller 11, rotation speed detection information of the spindle motor 2, and the like. The focus and tracking control is performed by controlling the thread mechanism 5. Also, the spindle motor 2 is controlled to a constant linear velocity (CLV) based on the CLV servo signal from the EFM / CIRC decoder 8.
Rotation control. In some cases, rotation speed information of the spindle motor 2 may be obtained to control the rotation to a constant angular speed (CAV).

The EFM signal is supplied to the EFM / CIRC decoder 8
After decoding processing such as EFM demodulation, error correction decoding, and sector decoding, the data is temporarily written into the buffer memory 13 under the control of the memory controller 12.
As the buffer memory 13, a 1-Mbit D-RAM or a 4-Mbit or 16-Mbit D-RAM is used. The reading of data from the magneto-optical disk 1 by the optical head 3 and the transfer of reproduced data in the system from the optical head 3 to the buffer memory 13 are performed at high speed and intermittently.

The data written in the buffer memory 13 is continuously read at a low rate and supplied to the audio compression decoder 14. In the mini-disc system, recorded data is subjected to audio compression processing to reduce the data amount to about 1/5. Therefore, during reproduction, the audio compression decoder 14 reverses the compression processing during recording. Is decompressed to obtain a digital audio signal of the original data amount.

The reproduced data subjected to the decoding processing for the audio compression processing is converted into an analog audio signal by the D / A converter 15 and output from the output terminal 16 as, for example, L, R analog audio signals.

The system controller 11 is a part for controlling the entire reproducing apparatus, and controls the operation of each unit with respect to the reproducing operation as described above. The operation unit 19 is provided with a key for user operation, and the operation information is supplied to the system controller 11. The system controller 11 performs operations such as reproduction, stop, and search according to the operation information. The display unit 20 is configured by, for example, a liquid crystal display, and
Under the control of 1, the operation state, mode, reproduction time information and the like are displayed.

The oscillator 21 has a crystal master clock M
Generate CK. The master clock MCK is supplied to the system controller 11 and other necessary parts and used for operation processing.

FIG. 2 shows the configuration of the PLL circuit 10 of this embodiment mounted on such a mini-disc reproducing apparatus. This P
The LL circuit 10 has a digital circuit configuration including an edge detector 31, a phase comparator 32, a low-pass filter 33, and an oscillator 34.

The master clock MCK is supplied to the edge detector 31, the phase comparator 32, and the oscillator 34. Also, the output of the oscillator 34 becomes the reproduced clock CKp,
The recovered clock CKp is used as a comparison reference signal in the phase comparator 32 and the low-pass filter 33
(Digital filter) processing clock.

The EFM signal output from the binarization processing section 6 is input to an edge detection section 31 in the PLL circuit 10, and the edge timing is extracted. Then, the edge timing detection signal is compared with the phase of the reproduction clock CKp in the phase comparator 32, and phase error information is output. The phase error information is band-limited by a low-pass filter 33 and then input to an oscillator 34.

The oscillator 34 is a so-called NCO (Number C)
ontrolled oscillator), and by changing the frequency division ratio according to the input phase error information, EFM
The playback clock CKp synchronized with the signal is obtained.

As shown in FIG. 3, the oscillator 34 basically includes a limiter 41, a counter 42, a decoder 43,
/ Min period 44. Apart from these basic NCO components, an n-stage shift register 45 (in this example, four-stage shift registers 45-1 to 45-45)
-4), and a gate circuit 46 is provided.

First, as the operation of the components as the basic NCO, the frequency division ratio is varied according to the phase error information, and the oscillation frequency (reproduced clock CKp) changes. The phase error information from the low-pass filter 33 is first input to the limiter 41 and is limited to a value of ± 1. That is,
The value of the phase error information is limited to one of "1", "0", and "-1". The output of the limiter 41 becomes the load data of the counter 42.

The counter 42 loads the output of the limiter 41 in response to the load signal LD, and counts up based on the master clock MCK. The next-stage decoder 43 is configured to output “1” when the value of the counter 42 becomes “3”. The "1" output of the decoder 43 is a load signal LD for the counter 42.

Since the operations of the counter 42 and the decoder 43 are the same as the operations described with reference to FIG. 6, the duplicate description will be avoided here. However, when viewed from the output of the decoder 43, the load value of the counter 42 (limiter output ) Is "0", the dividing ratio is 4, the dividing value is 3 when the load value is "1", and the dividing ratio is 5 when the load value is "-1". Is done.

The output of the decoder 43 on which the frequency division ratio variable operation has been performed is frequency-divided by a 1/2 frequency divider 44, and
When the pulse duty is set to 50%, the reproduction clock CKp is used. That is, the reproduction clock CKp is E
When the frequency division ratio is varied according to the phase error of the FM signal, the frequency signal is generated so as to converge to a frequency signal synchronized with the EFM signal.

In this embodiment, however, the shift register 45 and the gate circuit 46 generate the change permission signal EC,
The operation of the limiter 41 is controlled by the change permission signal EC. That is, when the change permission signal EC = “0”, the output value of the limiter 41 holds the previous value regardless of the input value at that time (that is, the phase error information), and the output value change is prohibited. Become. And the change permission signal E
Only when C = “1”, the output of the limiter 41 becomes one of “1”, “0”, and “−1” according to the input phase error information.

The change permission signal EC is output from the limiter output =
The signal becomes "1" when it becomes "0" four or more times in succession. That is, the output of the limiter 41 is supplied to the shift register 45. Since the output of the decoder 43 is used as the shift clock of the shift register 45,
Each of the registers 45-1 to 45-4 holds the limiter output value (load value of the counter 42) for the past four timings. Q of each of the registers 45-1 to 45-4
Since the output is inverted and input to the gate circuit 46 having an AND gate configuration, the Q output of each of the registers 45-1 to 45-4, that is, the values held in the registers 45-1 to 45-4 are all "0". , The change permission signal EC becomes “1”. This means that the output of the limiter 41 is allowed to be changed in the range of +1 to −1 when the output of the limiter = “0” continues four times or more.

Further, the change permission signal EC becomes "1",
At the next timing after the change is permitted, the change permission signal EC =
When it becomes “0”, the change of the output value of the limiter 41 is prohibited, and the output value of the limiter 41 is cleared to “0”.

After the operation of the limiter 41 is controlled by the change permission signal EC, the oscillator 3 of this embodiment is controlled.
FIG. 4 shows the operation of changing the frequency division ratio at step S4. Note that FIG. 4 has the same configuration as that of FIG. 7 described above, and T1 to T30 indicate timings on the time axis. As the limiter input, the phase error information from the low-pass filter 33 is shown as a value after the limit (in the case of this example,
Actually, it does not always output the limited value.) The limiter output is a value serving as load data of the counter 42. An arrow EC in the figure indicates a timing at which the change permission signal EC becomes "1". Limiter input value (phase error information) for easy comparison
Were made the same as in the example of FIG.

In this case, the limiter input is "1" four times continuously at the time points T1 to T4.
Since C is “0”, a change in the limiter output is not permitted, and the limiter output (= load data of the counter 42) is “0”. Therefore, during this period, the oscillator 34 is in the operating state with the dividing ratio of 4.

Since "load value = 0" has continued four times up to the time T4, the change permission signal EC = "1", and
Assuming that limiter input = “1” at five points, limiter output (load value) = “1” because change of limiter output is permitted. As a result, the frequency division ratio at time T5 becomes “3”. Limiter output at T5 =
When the value becomes "1", the value held in the register 45-1 becomes "1", and the change permission signal EC becomes "0".
At time 6, the limiter output (load value) becomes “0”.

Thereafter, until the time T9, the change permission signal EC =
Since it does not become "1", the limiter output remains "0" regardless of the phase error information. However, at time T10, the change permission signal EC becomes "1" and the limiter output becomes "1" according to the phase error information "-1". It becomes “−1” and the counter 42 displays “−”.
1 "is loaded.

By such an operation, the frequency division ratio changes as shown in the figure. Comparing this with FIG. 7, the limiter output becomes "0" four times or more as in this example. If does not continue, it can be seen that the load value of the counter 42 is not changed, and that the change in the frequency division ratio is considerably limited.

Now, assuming that the value of the phase error information, which is the limiter input, is always at a level corresponding to “−1”, the change of the frequency division ratio is “4” → “4” → “4”. →
"4" → "5" → "4" → "4" → "4" → "4" →
"5" → "4" → "4" → ... In other words, the frequency division ratio becomes "5" only once every five times, and the frequency division operation is performed at other times. Considering the average frequency division ratio in this case, (4 ×
4 + 5) /5=4.2. Assuming that the center frequency = fc, the frequency as the reproduction clock CKp is (4/4.
2) xfc = 0.952fc.

Similarly, considering the case where the value of the phase error information, which is the limiter input, is always at a level corresponding to “1”, the change of the frequency division ratio is “4” → “4” → “4”. →
"4" → "3" → "4" → "4" → "4" → "4" →
"3" → "4" → "4" → ... In other words, the frequency division ratio becomes "3" only once in five times, and the frequency division operation is performed at other times. Considering the average frequency division ratio in this case, (4 ×
4 + 3) /5=3.8. The frequency as the reproduction clock CKp is (4 / 3.8) × fc = 1.052fc.

Therefore, in the case of the present embodiment, the oscillation frequency range of the oscillator 34 is 0.952 fc to 1.052 fc, and the oscillation frequency range of the oscillator 90 of FIG.
The range is much more limited than 1.33fc. That is, in the case of this example, even if the frequency of the master clock MCK is not increased, the oscillation frequency range can be limited to such an extent that the side lock can be effectively prevented.

In the above example, the shift register 45 is set to 4
When the limiter output becomes "0" four times in a row, the change permission signal EC is set to "1". However, when the shift register 45 has a five-stage configuration, the limiter is made five times in a row. When the output becomes "0", the change permission signal EC =
It will be "1". That is, the larger the value of “n” of the shift register 45 having the n-stage configuration, the narrower the oscillation frequency range can be limited. When the value of “n” is dynamically changed, the oscillation frequency range can be set more finely. of course,
If the limiter output “0” is continuous three times, control may be performed such that the change permission signal EC is set to “1” twice to permit the change of the load value twice. Of course, similar control is possible without using a shift register.

In the above example, the master clock MCK
The digital PLL circuit has a configuration in which the period of the reproduction clock CKp changes in units of one wave.
The present invention is also applicable to a digital PLL circuit in which the period of the reproduction clock CKp changes in units of K half-waves.

In this embodiment, the digital PLL circuit is mounted on a mini disk reproducing device. However, the digital PLL circuit of the present invention is mounted on various devices such as a CD reproducing device, a CD-ROM reproducing device, and a tape reproducing device. Digital P
This is suitable as an LL circuit.

[0055]

As described above, according to the digital P of the present invention,
The LL circuit restricts the frequency range of the frequency signal generated by the oscillating means by controlling permission and non-permission of a change in the oscillating frequency according to the error information in the oscillating means (for example, an operation of changing the frequency division ratio). I am trying to do it. As a result, the oscillation frequency range can be limited without increasing the master clock frequency, whereby the occurrence of side lock can be effectively prevented.

In particular, even when the frequency ratio between the master clock frequency and the oscillation output frequency is not so different, it is possible to easily limit the oscillation frequency range and thereby prevent the side lock. Furthermore, since it is not necessary to increase the master clock frequency, the configuration is very advantageous in terms of the operation speed limit and the reduction of power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram of a reproducing apparatus equipped with a digital PLL circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a digital PLL circuit according to the embodiment;

FIG. 3 is a block diagram of an oscillator of the digital PLL circuit according to the embodiment.

FIG. 4 is an explanatory diagram of a change in a frequency division ratio of the oscillator according to the embodiment.

FIG. 5 is a block diagram of a conventional digital PLL circuit.

FIG. 6 is an explanatory diagram of a frequency division ratio variable operation of the digital PLL circuit.

FIG. 7 is an explanatory diagram of a transition of a frequency division ratio of a conventional oscillator.

[Explanation of symbols]

6 Binarization circuit, 8 EFM / CIRC decoder 10
Digital PLL circuit, 11 system controller,
12 memory controller, 13 buffer memory, 1
4 audio compression decoder, 31 edge detector, 32 phase comparator, 33 low-pass filter, 34 oscillator, 41
Limiter, 42 counter, 43 decoder, 44 1
/ 2 min period, 45 shift register, 46 gate circuit

Claims (3)

[Claims] 1. A PLL circuit for generating a frequency signal synchronized with an input signal, comprising: an error detecting means for detecting error information for the input signal; and changing an oscillation frequency according to the error information detected by the error detecting means. An oscillating means capable of generating a frequency signal synchronized with the input signal, and permitting and rejecting control of an oscillating frequency change operation in the oscillating means in accordance with error information, whereby the oscillation And an oscillation frequency range limiting means capable of limiting a frequency range of a frequency signal generated by the means. 2. The oscillating means is formed so as to generate a frequency signal synchronized with the input signal by changing a dividing ratio according to error information detected by the error detecting means. The range limiting unit is configured to limit and control the frequency range of the frequency signal generated by the oscillating unit by controlling permission and non-permission of a change in the frequency division ratio of the oscillating unit according to the error information. The PLL circuit according to claim 1, wherein 3. The oscillating frequency range limiting means according to claim 1, wherein said oscillating frequency range limiting means determines the frequency division ratio according to the error information only when a state in which the specific frequency dividing ratio is within a variable range of the frequency dividing ratio continues for a predetermined period or more. 3. The PLL circuit according to claim 2, wherein a change is permitted.