JPH1051776A - Image coding device - Google Patents

Abstract

(57) Abstract: An object of the present invention is to provide an image encoding device capable of high-speed processing with a small-scale circuit that performs appropriate encoding over the entire screen while maintaining an appropriate amount of data for each predetermined period. SOLUTION: A bit shift circuit 29 includes a quantization circuit 2
8a is converted into a plurality of types of predetermined bit numbers m
Shift by 1 to m4, and output a plurality of shift data in parallel. The code amount calculation means 61 calculates a data amount when a plurality of shift data are subjected to variable length coding for one screen, and outputs a plurality of data amount information b1 to b4. The scaling coefficient update circuit 42 outputs the coefficient k2 obtained by updating the initial coefficient k1 according to the data amount information b1 to b4 to the encoding means 62. The encoding unit 62 performs encoding using the coefficient k2 so that the encoded data amount is less than the desired data amount and close to the desired data amount.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus, and more particularly to an image coding apparatus for quantizing transformed data obtained by transforming image information into a frequency domain and performing variable length encoding on the quantized data. It is about.

[0002]

2. Description of the Related Art In recent years, with the development of multimedia,
Digital processing of images, especially high-efficiency coding technology for compressing image data, has attracted attention, and JPEG has been established as an international standard organization for coding color still images.
(Joint Photographic Expert Group) has adopted the DCT coding method as an international standard.

[0003] An outline of a basic system of this type of coding system will be briefly described below. FIG. 4 is a block diagram for explaining a schematic configuration of a conventional image encoding device using the DCT method. Tables 1 to 3 are diagrams for explaining the processing of the encoding method shown in FIG. A digital image signal to be encoded is input to an input terminal 2. The image signal input to the input terminal 2 is input to an 8 × 8 blocking circuit 4 where it is two-dimensionally divided into pixel blocks consisting of (8 × 8) pixels. The blocking circuit 4 sends an image signal to the subsequent stage in units of this pixel block. DC
The T circuit 6 performs a discrete cosine transform (DCT) on the image signal received from the blocking circuit 4 and outputs an (8 × 8) data matrix for the frequency domain. That is, the pixel block composed of the image data B _{11 to} B ₈₈ as shown in Table 1 is converted by the DCT circuit 6 into D _{11 to} D ₈₈ as shown in Table 2.
It is converted to a data matrix consisting of ₈₈ .

[0004]

[Table 1]

[0005]

[Table 2]

Here, D ₁₁ is the direct current (D
C) component, that is, the average value of this pixel block. If the remaining AC components D _{12 to} D ₈₈ are generally expressed as AC components D _ij , the higher the subscripts i and j, the higher the frequency components.

[0007] The data matrix output from the DCT circuit 6 is input to the quantization circuit 8. On the other hand, the quantization matrix generation circuit 18 generates quantization matrix W ₁₁ to _W-88 shown in Table 3, which means the weighting of the quantization step size for each DCT coefficient D ₁₁ to D _88. The scaling coefficient generation circuit 16 generates a coefficient k. The quantization matrix W ₁₁ to _W-88 and the coefficient k is input to the multiplier 20. The multiplier 20 calculates (W _ij × k), and the quantizing step of the quantizing circuit 8 is based on the outputs Q ₁₁ to Q _{11 of the} multiplier 20.
It is determined according to Q _88. Here, W _ij represents the quantization matrices W _{11 to} W ₈₈ , and the coefficient k is a positive value, and the image quality and the amount of generated data are controlled by the value of the coefficient k.

[0008]

[Table 3]

In practice, the quantization circuit 8 uses D _ij / Q _ij
Is calculated and output. The output of the quantization circuit 8 is R
And _{11 ~R 88.} The quantized transform data R _{11 to} R _11
Reference numeral ₈₈ denotes a zigzag conversion circuit 10 which sends out the low frequency components in order. That is, the zigzag conversion circuit 10, R ₁₁ to R
₈₈ is R ₁₁ , R ₁₂ , R ₂₁ , R ₃₁ , R ₂₂ , R ₁₃ , R ₁₄ , R
₂₃ , _R32 , _R41 ... _R85 , _R86 , _R77 , _R68 , _R78 ,
Variable-length coding in the order of R ₈₇ and R ₈₈ (hereinafter referred to as VLC)
It is supplied to the circuit 12. In VLC circuit 12, for example, calculates a predicted value between pixel blocks located near about DC component R _11, Huffman encodes the prediction error between the predicted value. Further, the alternating current (AC) component R ₁₂ to R ₈₈ encodes while scanning from the low-frequency components as described above and in zigzag to the high-frequency component, significant coefficients quantized output is not zero classified group by the value . A group identification number assigned to the group being classified,
The quantized output sandwiched between the immediately preceding significant coefficient and the run length of the invalid coefficient having a value of 0 is paired to perform Huffman coding, and then an equal length code indicating which value in the group is added. . Generally, the high-frequency components of an image have a low probability of appearance,
The latter half of _Rij after zigzag scanning often becomes all zeros. Therefore, a very high compression ratio can be expected for the variable length code obtained in this way. The reason why the code length after variable length coding becomes shorter as the number of DCT coefficients in the high frequency region that becomes zero becomes larger is due to the mechanism of coding AC coefficients. That is, the coding of the AC coefficient is performed by a variable length coding of a combination of a significant coefficient (an AC coefficient having a non-zero value) and a run length of an invalid coefficient (an AC coefficient having a zero value) preceding the significant coefficient. By increasing the quantization count value (by dividing by a large value) and increasing the invalid coefficients so that the invalid coefficients are continuous, the coefficients can be collectively converted into one code, and the code amount is reduced. Decrease. Where the coefficient k
Is increased, the probability that R _ij becomes 0 increases, and the total number of bits nb of the encoded data decreases. The relationship between the coefficient k and the total number of bits nb is a simple decreasing function.

By the way, when an image is compressed and encoded,
In general, the total number of bits tends to increase for a fine picture, and to decrease for a smooth image. For this reason, the total number of bits after data compression changes for each image, and in applications such as digital electronic still cameras, there is an inconvenience that the capacity of a recording medium for recording images may be insufficient. Therefore, as shown in FIG. 5, there is a type in which a buffer memory is provided in the output unit and the total number of bits nb for each image is constant regardless of the picture. That is, the buffer memory 13 _replaces the output Q _ij of the multiplier 20 that determines the quantization step in FIG. 4 with the encoding characteristic (quantization step size) according to the use state of the buffer memory 13.
Is given to the quantization circuit 8. Therefore, a buffer memory 13 that stores the output of the VLC circuit 12 is provided instead of the scaling coefficient generation circuit 16, the quantization matrix generation circuit 18, and the multiplier 20. However, in this image encoding device, since the quantization step size is sequentially changed in accordance with the use state of the buffer memory 13, it is not possible to make an optimal adjustment over the entire screen. For example, when image data of a picture whose upper half is flat and whose lower half is fine is input, unnecessary bits are assigned to encode the image data of the upper half of the screen, and the lower half of the image data of the image data is input. Sufficient bits cannot be allocated for encoding, and image quality deteriorates.

On the other hand, an image coding apparatus in which quantization is repeated using a plurality of quantization step sizes until a desired data amount is reached, and the total number of bits nb is suppressed to less than a desired value nb0, is shown in FIG. This will be described with reference to FIG. FIGS. 6 and 7 are connected by a dashed line indicated by reference numeral 70 in the figure. In the image encoding apparatus shown in FIGS. 6 and 7, the digital image signal to be encoded, which is input to the input terminal 20, is input to the 8 × 8 blocking circuit 22, where It is divided two-dimensionally into pixel blocks consisting of (8 × 8) pixels. The DCT circuit 24 performs a discrete cosine transform on the image signal received from the blocking circuit 22, and outputs an (8 × 8) data matrix for the frequency domain. The data matrix output from the DCT circuit 24 is zigzag-converted by a zigzag conversion circuit 26. On the other hand, the quantization matrix generation circuit 3
2, the quantization matrix W ₁₁ to _W-88 shown in Table 3 were generated, scaled initial coefficient generating circuit 38 generates the coefficient k1. The quantization matrix W ₁₁ to _W-88 and the coefficient k1
Is input to the multiplier 34a.

The multiplier 34a calculates (W _ij × k), and the quantization step of the quantization circuit 28a is performed by the multiplier 3a.
It is determined according to the output Q ₁₁ to Q ₈₈ of 4a. actually,
In the quantization circuit 28a, D _ij / Q _ij is calculated and output. The output of the quantization circuit 28a and R ₁₁ to R _88. The VLC circuit 36a performs Huffman coding on the output of the quantization circuit 28a, and adds an equal length code indicating which value in the group. Next, the code amount calculation circuit 40a
Calculates the total number of bits b1 by accumulating the variable-length code data output from the VLC circuit 36a for one screen. The coefficient calculation circuit 41a generates a coefficient k2 different from the initial coefficient k1 based on the calculation result of the code amount calculation circuit 40. The multiplier 34b, the coefficients k2 and quantization matrix W ₁₁ to W-
_The outputs Qa _{11 to} Qa ₈₈ are supplied to the quantization circuit 28b by using ₈₈ . The coefficient calculation circuits 41a to 41c compare the total code amounts b1 to b3 in one frame period obtained by the code amount calculation circuits 40a to 40c with a desired code amount, and update the scaling coefficient values to k2 to k4. . Specifically, for example, in the coefficient operation circuit 41a, if the total code amount b1 when quantized using the initial coefficient k1 is larger than a desired code amount, the scaling coefficient k2 is updated to a value larger than k1. If the total code amount b1 when quantized using the initial coefficient k1 is smaller than the desired code amount, the scaling coefficient k2 is updated to a value smaller than the coefficient k1. This is because, in general, the larger the quantization count value, the more DCT coefficients in the high frequency region become zero, and as a result, the code length after variable length coding becomes shorter. .

The output of the zigzag conversion circuit 26 is given to the quantization circuit 28b with a delay of one screen by a delay circuit 30a. The quantization circuit 28b includes a multiplier 34b
Using the output Qa ₁₁ ~Qa _88, quantizes the output of the delay circuit 30a. VLC circuit 36b and code amount calculation circuit 4
0b uses the output of the quantization circuit 28b, and uses a VLC circuit 36a, a code amount calculation circuit 40a, and a coefficient calculation circuit 41a.
Similarly to the above, the total number of bits b2 accumulated for one screen is obtained, and a coefficient k3 is generated. Similarly, the delay circuit 30b, the quantization circuit 28c, the VLC circuit 36c, and the code amount calculation circuit 4
0c and the coefficient calculation circuit 41c calculate the total number of bits b3 and the coefficient k4 using the coefficient k3. Further, the delay circuit 30c
, The quantization circuit 28d, the VLC circuit 36d, and the code amount calculation circuit 40d obtain the total bit number b4. Delay circuit 30b
30d also delays the input data by one screen, similarly to the delay circuit 30a. The first generated coefficient k1 and the obtained coefficients k2 to k4 are respectively provided by the delay circuits 43a to 43a.
At 43d, the delay is delayed by four to one screen and input to the coefficient selector 47 all at once. The outputs b1 to b4 of the code amount calculation circuits 40a to 40d are 3 to 4 respectively.
The data is delayed by 0 screen and input to the coefficient determination circuit 45 all at once. The coefficient determination circuit 45 determines which of the coefficients k1 to k4 to use based on the total number of bits b1 to b4, and the coefficient selector 47 determines the coefficient k1 to k4 based on the determination result of the coefficient determination circuit 45. The selection is performed, and the selected coefficient is output to the multiplier 34e as the coefficient k5.

In such a conventional image coding apparatus, when the total number of bits nb is larger than the target value nb0, the scaling is increased by increasing the scaling coefficient k to reduce the total number of bits nb. Conversely, when the total number of bits nb is smaller than the target value, the scaling factor k is reduced and quantization is performed to increase the total number of bits nb. By repeating the quantization with the scaling coefficient changed, the output data amount finally converges to the target value. However, this method requires a large number of quantization circuits for obtaining an optimum scaling coefficient and a large number of frame period delay circuits for time difference compensation.

[0015]

As described above, the conventional image coding apparatus described above, when the output rate is kept constant by sequentially changing the coding characteristics according to the use amount of the output buffer, can be applied to the entire screen. There has been a problem that the optimum encoding cannot be performed and the image quality deteriorates. Further, when a method of changing the scaling coefficient and repeating the quantization to keep the output rate constant is employed, there is a problem that the circuit scale is significantly increased. The present invention has been made in order to solve the above-described problems, and performs optimal encoding over the entire screen, and sets a data amount for each predetermined period to a value less than a desired data amount and close to the desired data amount. It is an object of the present invention to provide an image encoding device suitable for high-speed processing by a small-scale circuit.

[0016]

According to a first aspect of the present invention, there is provided an image encoding apparatus comprising: a first image encoding apparatus that converts image information into a frequency domain;
Parallelizing means for outputting in parallel the converted data and the second converted data delayed by a predetermined time with respect to the first converted data, and a quantizer for quantizing the first converted data using an initial value of the control coefficient. Means for shifting the data quantized by the first quantizing means by a plurality of types of predetermined number of bits, and outputting a plurality of pieces of shifted data in parallel; Code amount calculating means for calculating the data amount at the time of conversion for the predetermined time and outputting a plurality of data amount information; and for bringing the data amount closer to a desired data amount according to the plurality of data amount information. A coefficient updating means for updating a control coefficient for controlling a quantization step on a screen basis to an optimum value from an initial value, and quantizing and encoding the second transformed data using a control coefficient output from the coefficient updating means. Constructed and a coding means for outputting a variable length code obtained by.

An image coding apparatus according to a second aspect of the present invention comprises:
In the image encoding device according to the invention, a scaling initial coefficient generation circuit that generates an initial value of the control coefficient, and a delay circuit that delays the initial value of the control coefficient output from the scaling initial coefficient generation circuit by the predetermined time. In addition, it is configured.

An image coding apparatus according to a third aspect of the present invention comprises:
Alternatively, in the image encoding apparatus according to the second aspect, the predetermined time includes a time corresponding to one screen, and the coefficient updating unit is smaller than a desired data amount from the plurality of data amount information, and Data amount information closest to the desired data amount is detected, and when the closest data amount information is obtained, the control coefficient is changed to a value corresponding to the number of bits shifted by the shift means.

An image coding apparatus according to a fourth aspect of the present invention is the
In the image encoding apparatus according to the invention, the code amount calculation unit performs grouping of the DC coefficient difference value and grouping of the AC coefficient, and converts the difference DC coefficient into a variable-length code using the code table for the difference DC coefficient. And a variable-length coding circuit for converting the AC coefficient into a variable-length code using the AC coefficient code table, and accumulating the code length of the variable-length code output from the variable-length coding circuit for one screen. And a code amount calculation circuit for obtaining the total number of bits.

An image coding apparatus according to a fifth aspect of the present invention has a third
In the image coding apparatus according to the invention, the code amount calculating means performs a grouping of DC coefficient difference values and a grouping of AC coefficients, and calculates a code length from a result of the grouping. A code amount calculation circuit for accumulating the code length of the variable length code output from the code length calculation circuit for one screen to obtain the total number of bits.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, an image encoding device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of an image encoding device according to Embodiment 1. The digital image signal to be encoded, which is input to the input terminal 20 of the image encoding device, is input to the 8 × 8 blocking circuit 22. Here, two-dimensionally (8
× 8) The image is divided into pixel blocks composed of pixels. The blocking circuit 22 sends an image signal to the subsequent stage in units of the pixel blocks. The DCT circuit 24 performs a discrete cosine transform on the image signal received from the blocking circuit 22, and outputs an (8 × 8) data matrix for the frequency domain. That is, a pixel block composed of image data B _{11 to} B ₈₈ as shown in Table 1 is converted into a data matrix composed of D _{11 to} D ₈₈ as shown in Table 2 by the DCT circuit 24 and supplied to the zigzag conversion circuit 26. Is done.

The zigzag conversion circuit 26 performs the same operation as the zigzag conversion circuit 10 shown in FIG. 4, and converts the data matrices D _{11 to} D ₈₈ subjected to discrete cosine conversion into D ₁₁ , D ₁₂ , D ₂₁ ,
_{D 31, D 22, D 13} , D 14, D 23, D 32, D 41 ... D 85, D
_86, D _77, D _68, and outputs in the order of _{D 78, D 87, D 88} .

The quantization matrix generation circuit 32 generates the above-described quantization matrices W _{11 to} W ₈₈ . However, in the image encoding device according to the first embodiment, each of the quantization circuits 28a to 28a
The 8b, because data already zigzag scanning is input, the quantization matrix W ₁₁ to _W-88 is also generated in an order corresponding to the zigzag scanning, a multiplier 34a, is supplied to 34b. The multiplier k is supplied with the coefficient k1 as the initial value of the control coefficient from the scaling initial coefficient generation circuit 38, and calculates (W _ij × k1) to the quantization circuit a.
Is input to Thus, in the quantization circuit 28a, quantized data R1 ₁₁ ~ by the control coefficient k1
R1 ₈₈ is obtained. The quantized data R1 ₁₁ to R
₁₈₈ is input to the bit shift circuit 29. The bit shift circuit 29, the quantized data R1 ₁₁ ~R1 _88, shifted to the right by the number of bits m1, m2, m3, m4 predetermined respectively.

The number of bits m1 to m4 to be shifted in the bit shift circuit 29 depends on the application in which the image encoding apparatus is used, for example, the type of image to be processed,
The number of bits to be shifted needs to be set differently depending on the capacity of the storage device and storage device of the compressed image. For example, in the first embodiment, the number of bits to be shifted is −4.
Although the range of ~ 4 has been mentioned, it may be better to take other values depending on the application. Therefore, an experiment may be performed in advance on the system side to determine an optimum value according to the application, and this may be set as a default value so that it can be appropriately changed at the time of execution.
Here, Tables 4 to 7 show examples of the Huffman code table in the JPEG encoding method.

[0025]

[Table 4]

[0026]

[Table 5]

[0027]

[Table 6]

[0028]

[Table 7]

Among the quantized DCT coefficients, DC components (DC coefficients) are grouped according to Table 4, and a group number is determined. The group number is subjected to variable length coding according to a code table as shown in Table 5. The codeword determined in this way and each DC in the same group
The coded data is obtained by linking the additional coefficient for distinguishing the T coefficient with the additional bit. For example, if the quantized DC coefficient difference value is “5”, the group number “3” is assigned according to Table 4, and the additional bit is “101”. From Table 5, the code word of group number 3 is “100”. Therefore, the encoded data in this case is “1001”
01 ". Among the quantized DCT coefficients, AC components (AC coefficients) are grouped according to Table 6, and a group number is determined. A significant coefficient whose quantized output is not 0 is the group number. A variable length encoding is performed by a code table as shown in Table 7 for a set of a null coefficient and a run length of an invalid coefficient sandwiched between the immediately preceding significant coefficient and a null output.
Coded data obtained by concatenating the code word determined in this way and additional bits for distinguishing each DCT coefficient in the same group is used.

For example, if the quantized AC coefficient value is "2"
If the run length of the invalid coefficient is “1”, the group number “2” is assigned according to Table 6, and the additional bit is “1”.
According to Table 7, the codeword of the run number 1 and the group number 2 is “11011.” Therefore, the encoded data in this case is “1101110.” The encoding is performed by such a mechanism. Therefore, in the case of the DC coefficient, when the group number is determined, the encoded data amount (the number of bits of the codeword +
The number of additional bits) is uniquely determined. In the case of the AC coefficient, when the combination of the run length of the invalid coefficient and the group number is determined, the encoded data amount is uniquely determined. In any case, when calculating the total number of bits (sum of the amount of encoded data), D
The CT coefficient value itself is not important and the group number (and A
What is necessary is just to know the run length of the invalid coefficient of the C coefficient). In the first embodiment, the number of bits (m1, m2, m3, m4) shifted by the bit shift circuit 29 is 4,
Values of 3, 2, 1, 0, -1, -2, -3, -4 can be taken. When the number of bits shifted by the bit shift circuit 29 is 4, 3, 2, or 1, the quantized output is multiplied by 1/16, 1/8, 1/4, or 1/2, respectively. . That is, the scaling factor is set to 16
The same quantized output as when multiplying by 8, 8, 4 or 2 times is obtained, and the group numbers are also the same.

When the number of bits shifted by the bit shift circuit 29 is -4, -3, -2 or -1, the quantized output is multiplied by 16 times, 8 times, 4 times or 2 times, respectively. In this case, the scaling factors are 1 /
Although the same quantized output is not always obtained when the multiplication is performed by 16 times, 1/8 times, 1/4 times or 1/2 times, the group numbers are the same. When the number of bits shifted by the bit shift circuit 29 is 0, a quantized output is obtained as it is. This corresponds to a quantized output when the scaling coefficient is used as it is.

As described above, the bit shift circuit 29 provides substantially the same effect as the case where quantization is performed by changing the scaling factor in various ways and using different quantization step sizes in a plurality of quantizers. Can be

The bit shift circuit 29 outputs m
The data shifted right by 1, m2, m3, and m4 bits are input in parallel to the VLC circuits 36a to 36d, where variable length coding is performed. The outputs of the VLC circuits 36a to 36d are input to code amount calculation circuits 40a to 40d, and the variable length code data is accumulated for one screen to obtain the total bit numbers b1 to b4. The total bit numbers b1 to b4 are calculated by the coefficient update circuit 42.
Is input to Here, the VLC circuits 36a to 36d and the code amount calculation circuits 40a to 40d perform entropy coding of a plurality of shift data and assign and assign a variable length code to obtain a data amount corresponding to each shift data. The code amount calculation means 61 for calculating the data amount at the time of the calculation on a fraction basis is configured. The delay circuit 44 delays the initial coefficient k1 output from the initial coefficient generation circuit 38 by one screen (frame) period. Accordingly, the total bit numbers b1 to b4 corresponding to the initial coefficient k1 and the initial coefficient k1 are input to the coefficient updating circuit 42 at the same timing. The coefficient updating circuit 42 detects information that is less than the desired total bit number nb0 and is closest to nb0 among the total bit numbers b1 to b4. The bit shift amount of the information in the bit shift circuit 29 is m
In this case, the initial coefficient k1 is shifted to the left by m bits and output as the control coefficient k2.

On the other hand, the delay circuit 30 is a circuit for delaying the output of the zigzag conversion circuit 26 by one screen (frame) period. The control coefficient k2 output from the coefficient update circuit 42 is input to the multiplier 34b at the timing when the conversion data for one screen used to obtain the control coefficient k2 is input to the quantization circuit 28b. Here, the node that branches the output of the zigzag conversion circuit 26 and the delay circuit 30 branch the conversion data obtained by converting the image information into the frequency domain into two conversion data having a delay of one screen with respect to each other. The parallelizing means 60 for outputting in parallel is constituted. In the multiplier 34b, (W _ij
× k2) is calculated and input to the quantization circuit 28b. That is, the quantization circuit 28b performs final quantization on the same screen. This quantized data is VL
It is supplied to the C circuit 36e. The VLC circuit 36e performs actual variable-length encoding, and outputs encoded data from the output terminal 50. This multiplier 34b, quantization circuit 28b and V
The LC circuit 36e quantizes the converted data output from the delay circuit 30 using the control coefficient k2 output from the scaling coefficient updating circuit 42, and outputs a variable length code obtained by coding the converted data by entropy coding. 62
Is configured.

According to the above-described configuration, only the single quantization circuit 28a needs to be used when obtaining the optimum value of the control coefficient k, and the processing can be performed at extremely high speed with a small-scale circuit. The total number of bits nb after encoding is less than the desired total number of bits nb0 and extremely close to nb0.

Embodiment 2 In the image encoding apparatus according to the first embodiment, the VLC circuits 36a to 36d perform variable-length encoding. However, it is not necessary to perform actual encoding when calculating the total number of bits. To code length calculation circuits 37a to 37d for calculating only the encoded data amount
It is also possible to adopt a configuration replaced with FIG. 2 is a block diagram showing a configuration of an image encoding device according to Embodiment 2 of the present invention. The code length calculation circuits 37a to 37d
Each of the conversion data shifted right by m1 to m4 bits by the bit shift circuit 29 is input, and the input conversion data is grouped into DC coefficient difference values and AC coefficients to calculate a code length. The image encoding device according to the second embodiment includes code length calculation circuits 37a to 37a.
Since 7d is used, the circuit configuration is simplified as compared with the case where the image coding apparatus according to the first embodiment uses the VLC circuits 36a to 36d.

Embodiment 3 The image coding apparatus according to the first embodiment calculates the quantization value in the quantization circuit 28a by multiplying the initial coefficient k1 by the quantization matrix W, but deletes the multiplier 34a as the initial coefficient k1 = 1. It is also possible to adopt a configuration in which the quantization circuit 28a performs quantization using the value of the quantization matrix as it is. For example, if the image encoding apparatus according to the first embodiment performs encoding under the condition that the coefficient k1 = 4, the multiplier 34a multiplies the quantization matrix W by the coefficient k1, and the quantization circuit 28a
, The respective values of the quantization matrix W are 4
The value is multiplied. That is, the DCT coefficients after the zigzag transformation are divided by the respective elements W ₁₁ × 4, W ₁₂ × 4,... Of the quantization matrix. Here, in order to obtain the same result as that of the image encoding device of the first embodiment in which the coefficient k1 = 4, the image encoding device of the third embodiment at this time uses the bit shift circuit 2
At 9, the image is right-shifted by two bits more than the image coding apparatus of the first embodiment. In the bit shift circuit 29,
Shifting right by two bits is equivalent to dividing by four. As a result, the circuit size can be reduced by eliminating the multiplier 34a from the image encoding device according to the first embodiment. This is shown in FIG. FIG. 3 shows Embodiment 3 of the present invention.
1 is a block diagram illustrating a configuration of an image encoding device according to.

Note that the image coding apparatus according to the first embodiment
If the value of the coefficient k1 is not a power of 2, the same result cannot be obtained by the image encoding device of the third embodiment. However, both the image coding apparatus according to the first embodiment and the image coding apparatus according to the third embodiment aim at optimizing the scaling coefficient of the quantization matrix according to the image. Since the final quantization is performed by the quantization circuit 28b using the multiplied value, the same effect can be obtained for the purpose of optimizing the data amount. In each of the above embodiments, the scaling coefficient update circuit 42 is configured to generate a control coefficient to obtain data amount information closest to a desired data amount.
The control coefficient may be set so that data amount information slightly exceeding the desired data amount but closest to the desired data amount may be obtained, and the same effects as those of the above embodiments can be obtained.

Further, in each of the above embodiments, the data amount for one screen is calculated to calculate the data amount after the variable length coding. For example, the data amount may be smaller or larger than one screen. From there, the data amount for one screen may be estimated, and the same effect as in the above embodiment can be obtained.

[0040]

As described above, according to the image encoding apparatus of the first aspect, the first means is provided by the shift means.
, The data output by the quantizing means is shifted by a predetermined number of bits of a plurality of types, and a plurality of shifted data can be obtained without using a multiplier or the like, even though the first quantizing means is one. Since the encoding means is configured to perform code conversion using an appropriate control coefficient with a delay of a predetermined time and output a variable length code, perform optimal encoding over the entire screen,
In addition, there is an effect that processing for optimizing the data amount for each predetermined period can be performed at high speed by a small-scale circuit.

According to the image coding apparatus of the present invention, since the initial value of the control coefficient output from the scaling initial coefficient generation circuit is delayed by the delay circuit for the predetermined time, There is an effect that encoding can be performed with delay and processing can be performed at high speed.

According to the image coding apparatus of the third aspect of the present invention, when the control coefficient updated by the coefficient updating means is used, the data amount of one screen after the encoding is always smaller than the desired data amount. In addition, there is an effect that an image encoding device that can be easily handled can be obtained.

According to the image coding apparatus of the fourth aspect, there is an effect that the code amount calculating means can be easily realized by using the conventional variable length coding circuit and code amount calculation circuit.

According to the image coding apparatus of the present invention, the code length calculating circuit performs grouping of DC coefficient difference values and grouping of AC coefficients, and calculates a code length from the grouping result. However, since the difference DC coefficient or AC coefficient is not converted into a variable length code, the circuit scale of the image encoding device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image encoding device according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram showing a configuration of an image encoding device according to Embodiment 2 of the present invention.

FIG. 3 is a block diagram showing a configuration of an image encoding device according to Embodiment 3 of the present invention.

FIG. 4 is a block diagram illustrating a first example of a configuration of a conventional image encoding device.

FIG. 5 is a block diagram illustrating a second example of the configuration of a conventional image encoding device.

FIG. 6 is a block diagram illustrating a third example of the configuration of a conventional image encoding device.

FIG. 7 is a block diagram illustrating a third example of the configuration of a conventional image encoding device.

[Explanation of symbols]

22 8 × 8 block circuit, 24 DCT circuit, 26
Zigzag conversion circuit, 28a, 28b quantization circuit, 2
9-bit shift circuit, 30, 44 delay circuit, 32
Quantization matrix generation circuit, 34a, 34b multiplier, 36a-36e variable length coding circuit, 37a-37
d code length calculation circuit, 38 scaling initial coefficient generation circuit, 40a to 40d code amount calculation circuit, 42 scaling coefficient update circuit, 60 parallelizing means, 61, 63
Code amount calculation means, 62 coding means.

Claims (5)

[Claims] 1. parallelizing means for outputting in parallel first converted data obtained by converting image information into a frequency domain and second converted data delayed by a predetermined time with respect to the first converted data; Quantizing means for quantizing the first transformed data using an initial value of a coefficient; and shifting the data quantized by the first quantizing means by a plurality of types of predetermined number of bits to obtain a plurality of shifted data. Shift means for outputting a plurality of pieces of shift amount data in parallel, code amount calculating means for calculating a data amount when the plurality of pieces of shift data are variable-length encoded for the predetermined time, and outputting a plurality of pieces of data amount information, A coefficient updating unit that updates a control coefficient that controls a quantization step on a screen basis in order to bring the data amount closer to a desired data amount to an optimal value from an initial value, according to the data amount information of Do Using said control coefficients second
Encoding means for quantizing the converted data and outputting a variable-length code obtained by encoding. 2. The apparatus according to claim 1, further comprising: a scaling initial coefficient generating circuit for generating an initial value of the control coefficient; and a delay circuit for delaying the initial value of the control coefficient output from the scaling initial coefficient generating circuit for the predetermined time. Item 7. The image encoding device according to Item 1. 3. The method according to claim 2, wherein the predetermined time includes a time corresponding to one screen, and wherein the coefficient updating unit determines that the desired data amount is smaller than a desired data amount among the plurality of data amount information. The control coefficient is changed to a value corresponding to the number of bits shifted by the shift means when the closest data amount information is obtained and the closest data amount information is obtained. Image encoding device. 4. The code amount calculating means performs grouping of DC coefficient difference values and grouping of AC coefficients, and converts a difference DC coefficient into a variable length code using a code table for a difference DC coefficient. A variable-length encoding circuit that converts AC coefficients into a variable-length code using a coefficient code table; and accumulates the code length of the variable-length code output from the variable-length encoding circuit for one screen to obtain total bits. 4. The image encoding apparatus according to claim 3, further comprising a code amount calculation circuit for calculating the number. 5. A code length calculation circuit for performing grouping of DC coefficient difference values and grouping of AC coefficients, and calculating a code length from a result of the grouping; 4. The image coding apparatus according to claim 3, further comprising: a code amount calculating circuit for accumulating the code length of the variable length code output from the one screen for one screen to obtain a total bit number.