JPH1051804A - Synchronization determination circuit and television receiver - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To improve the standard / non-standard signal judgment operation. SOLUTION: The horizontal synchronization pulse Hsync is n times (where n ≧
Oscillator 10 for generating clock CLK having oscillation frequency of 2)
A frequency divider 11 that is reset by the vertical synchronization pulse Vsync and counts the period of the vertical synchronization pulse Vsync based on the clock CLK; a determination unit Jad1 that detects the vertical synchronization pulse Vsync at the timing of the count pulse P525a; Vsync or a count pulse P525b or a count pulse having the same period as the vertical synchronization pulse Vsync
Reset by a reset pulse P575 corresponding to P525b and a vertical synchronization pulse V based on the clock CLK.
A frequency divider 19 for counting the cycle of sync, a judging unit Jad2 for detecting the vertical synchronizing pulse Vsync according to the count pulse P525b, and a judging unit judging unit Jad1 or Jad2 to judge whether the signal is a standard signal. The frequency divider 19 is reset by a count pulse P525b or a reset pulse P575 when the determination by the determination unit 18 is a standard signal, and is reset by a vertical synchronization pulse Vsync when the determination is a non-standard signal. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization judging circuit and a synchronization judging circuit for judging whether an input video signal is a standard signal or a non-standard signal formed by a proper television system. The present invention relates to a television receiver provided.

[0002]

2. Description of the Related Art At present, for example, a television receiver can receive broadcast radio waves transmitted from a broadcast station and select and view a broadcast program with a tuner. It is possible to watch a movie or the like reproduced in such as. Also, recently, a game device has been connected as an external input device, and a video of dedicated game software can be projected on a screen and played.

When viewing software such as a movie or the like normally reproduced from a broadcast program or a video deck selected by a tuner,
These video signals are, for example, NTSC (National Televis).
ionSystem Committee ・ ・ ・ horizontal synchronization frequency 15.73
4KHz, 262.5 horizontal scanning lines) method and PAL
(Phase Alternation by Line) method or the like is input as a standard signal. Also, during special playback (fast forward / rewind search, still picture playback, etc.) by a video deck or the like, the vertical synchronization signal and the horizontal synchronization signal of the video signal have a different cycle relationship depending on the model, and are different from the standard signal as non-standard signals. Is entered. Further, video signals output from the game device are also input as non-standard signals (for example, 262 horizontal scanning lines, 263 lines, etc.) generated by the various game devices themselves.

In the case of a standard signal input as a received signal, for example, noise is superimposed in some form on the broadcast radio wave, or in a weak electric field area, the vertical synchronizing signal is temporarily lost and the synchronizing performance deteriorates. In some cases. Therefore, when the lack of the vertical synchronization signal is detected in the standard signal, it is considered that the interpolation processing is performed by making a prediction from the vertical synchronization signals before and after that. As a result, the vertical synchronization becomes stable, and a good image can be obtained. On the other hand, for example, a video signal supplied from a game device is a non-standard signal, but a synchronization signal is supplied at a predetermined cycle (for example, 262 horizontal scanning lines, 263 lines) without being lost. Therefore, for the input video signal,
In this case, there is no need to perform interpolation processing. Therefore, 262.
When there is no vertical synchronization signal in five periods, it is necessary to determine whether there is a missing in the standard signal or a non-standard signal with a different vertical synchronization period.

FIG. 7 shows a configuration example of a synchronization determination circuit in a deflection control unit applied to, for example, an NTSC television receiver as a conventional example. Horizontal sync signal HSync extracted by a video signal processing system (not shown)
(About 15.734 kHz in the case of the NTSC system) is supplied to an oscillator 30 constituted by, for example, a PLL or the like. The oscillator 30 is configured to oscillate using the horizontal synchronization signal HSync as a reference clock.
Clock with n times frequency (where n is a natural number) with respect to Sync
Generate CLK. Here, as an example, it is assumed that n = 2 and a clock CLK having a frequency twice as high as the horizontal synchronization signal HSync is generated. Therefore, the clock CLK is 31.
It will be output at a frequency of 468 kHz.

The clock CLK is, for example, a flip-flop 3
31j are supplied as clocks for counting to a frequency divider 31 configured as a 10-bit counter. The count output (output from the output terminal Q of each flip-flop 31a to 31j) output from the frequency divider 31 is output to the timing generator 32.
The timing generator 32 outputs, for example, 5
It is configured to output a count pulse P525 that goes low at the timing of 25 counts, for example, a reset pulse R492 that goes low at the timing of 492 counts. An OR circuit 33 is provided at the input stage of the frequency divider 31 so that the reset is performed at the falling edge of the vertical synchronization pulse Vsync or the reset pulse R492 which becomes L level at the timing of the vertical synchronization signal. Thus, as shown in FIGS. 8A and 8B, for example, a dead zone can be provided up to the 492th count with respect to the vertical synchronization pulse Vsync. Therefore, the vertical synchronization pulse V
Even when noises N, N... are superimposed on sync, the frequency divider 31 can be synchronized with the correct vertical synchronization pulse Vsync without being affected by the noise N.

The flip-flops 34 and 35 are provided so as to constitute a determination unit for determining whether or not the input signal is a standard signal based on the cycle of the vertical synchronization pulse Vsync. Is supplied. Further, the count pulse P525 output from the timing generator 32 is supplied to the clock terminal, while the count pulse P525r whose phase has been inverted is supplied to the clock terminal of the flip-flop 35 via the inverter Inv. Become. Accordingly, the output levels of the output terminals Q1 and Q2 of the flip-flops 34 and 35 are determined at the falling timing of the count pulses P525 and P525r, respectively.
As described later, the vertical synchronizing pulse V together with the AND circuit 36 is used.
The presence or absence of sync can be determined.

Since the "0" period after the frequency divider 31 is reset is always shorter than the period of one clock, the 525th clock, that is, the count pulse P525 rises earlier than the vertical synchronization pulse Vsync of the standard signal. Therefore, the count pulse P525 and the inverted count pulse P525r with respect to the vertical synchronization pulse Vsync schematically shown in FIG. 9A are shown in FIGS. 9B and 9C, respectively. Flip-flop 3 at the timing of the arrow
The trigger signals are 4, 35. Therefore, at the time of the normal vertical synchronizing signal Vsync, the output terminal Q1 outputs an H level signal and the inverted output terminal Q2 at the timing of each of the falling points A and B.
Also outputs the H level. Then, the output of the AND circuit 36 becomes H level, and in this case, it is determined that the signal is a standard signal.

As shown in FIGS. 9D, 9E and 9F, the vertical synchronizing signal Vsync and the count pulse P525 are used.
Are not coincident with each other, the output terminal Q1
Outputs an H level and the inverted output terminal Q2 outputs an L level. In this case, since the output of the AND circuit 36 is at the L level, it is determined that the signal is a non-standard signal in this case. The result of this determination is supplied to a synchronous interpolation processing system (not shown).
When nc is missing, interpolation processing is performed.

Thus, even when a video signal having a large amount of noise N is input, if it can be determined that the signal is a standard signal, the frequency divider 31 sets a dead band up to, for example, 262 counts with respect to the vertical synchronization pulse Vsync. With the provision, control can be performed so that the image screen is not disturbed even in a weak electric field.

Also, as shown in FIG.
It is also considered to provide, for example, a 3-bit up / down counter 37 as an integrating means in Jad3. If the count value output from the up / down counter 37 is, for example, 4 (“100” in binary notation) or more, it is determined that the signal is a standard signal, and thus the lack of the vertical synchronization pulse Vsync and the superposition of noise are performed. And so on. Note that the bit width of the up / down counter 37 affects the time constant of transition when making a decision on a standard / non-standard signal, but does not affect the overall operation.

In the example shown in FIG. 1, a frequency divider 31 for measuring the vertical synchronization pulse Vsync, a frequency divider 38 for generating the timing of vertical deflection, and a timing generator 39 are provided individually. Further, the reset is performed at the falling edge of the vertical synchronization pulse Vsync or the reset pulse R488. As a result, 4 pulses are applied to the vertical synchronization pulse Vsync.
A dead zone can be provided up to the 88th count. Therefore, even when noise is superimposed on the vertical synchronizing pulse Vsync, the noise is not affected by this noise and the frequency divider 3
1 can be synchronized with the correct vertical synchronization pulse Vsync.

Up / down counter (3 bits) 37
Is supplied with the output level of the AND circuit 36, and a reset pulse R491 which becomes L level at the timing of 491 counts is supplied from the timing generator 32,
At the timing of this reset pulse R491, the AND circuit 36
Counts up when the output level of the
In the case of L level, countdown is performed. When the count value reaches a predetermined level, it is determined that the signal is a standard signal.
W3 is switched. Here, for example, when the count value is 4 or more (100 in binary notation), for example, it is determined that the signal is a standard signal, the switch SW3 is connected to the contact b, and it is determined that the signal is a non-standard signal. In this case, control is performed to connect to the contact a side.

The frequency divider 38 is configured as a 10-bit counter by flip-flops 38a, 38b,..., 38j, like the frequency divider 31, and a clock CLK output from the oscillator 30 is supplied as a counting clock. . The count output (output of the output terminal Q of each of the flip-flops 38a to 38j) output from the frequency divider 38 is output to the timing generator 39. Timing generator 39
Becomes L level according to the count output. It is configured to output a reset pulse R525 (525 count), a reset pulse R492 (492 count), and a reset pulse R575 (575 count) for running the frequency divider 38 by itself. If the up / down counter 37 determines that the signal is a standard signal, it is reset by a reset pulse R525 supplied via a switch SW3 and runs on its own.
Reset by sync.

The reset pulse R492 and the vertical synchronizing pulse Vsy
nc is supplied to the OR circuit 40. This is to make the dead zone up to the 492th count the same as in the case described above with reference to FIG. Further, the output level of the OR circuit 40 is supplied to the AND circuit 41 together with the reset pulse R575.
For example, if the normal vertical sync pulse Vsync is apparently lost due to channel switching or the like, the frequency divider 31 continues counting to measure the vertical sync pulse Vsync of the next cycle, but the frequency divider 38 outputs the vertical sync pulse Vsync. In order to generate the deflection timing, it is necessary to reset itself and start counting again. Therefore, by providing the AND circuit 41, when the vertical synchronization pulse Vsync is lost, the reset pulse R575 is used to reset itself at the 575th count, for example.

By configuring the synchronization determination circuit in this manner, when the determination unit Jad3 determines that the signal is a standard signal, the switch SW3 is connected to the terminal b and the reset pulse R525 is supplied to the frequency divider 38. It is supplied and self-propelled. Thereby, the reset can be performed at a predetermined cycle regardless of the lack of the vertical synchronization signal pulse Vsync or the superposition of noise, and the frequency divider 38 and the vertical synchronization pulse Vsync can be synchronized. If the determination unit Jad3 determines that the signal is a non-standard signal, the switch S
W3 is connected to the terminal a, and the output of the AND circuit 41 is supplied to the frequency divider 38 as a reset pulse. As a result, it becomes possible to generate the vertical deflection timing by resetting the frequency divider 38 by itself as described above. That is, even when the synchronization of the first frequency divider 31 for detecting the lack of the vertical synchronization signal is disturbed, the synchronization of the frequency divider 38 for forming the vertical synchronization signal is not disturbed, and the timing generation unit 39 is not disturbed. Can output the timing of vertical deflection.

FIG. 11 is a diagram showing the output timing of each signal when a part of the vertical synchronizing signal is missing.
11A shows a clock CLK, FIG. 11B shows a vertical synchronization pulse Vsync, FIG. 11C shows a count pulse P525, and FIG.
11D shows the output level of the AND circuit 36, FIG. 11E shows the reset pulse R490, FIG. 11F shows the output level of the up / down counter 37, and FIG.
R525 is shown. In these figures, the missing timing of the vertical synchronization pulse Vsync is indicated by a broken line, and the noise N superimposed on the vertical synchronization pulse Vsync is indicated by a chain line.

As described above, the count value of the up / down counter 37 (FIG. 11F) changes at the timing when the reset pulse R490 (FIG. 11E) is supplied, as shown in FIG. 11D. As shown, the count-up is performed when the output of the AND circuit 36 is at the H level, and the count-down is performed when the output is at the L level. Thus, for example, FIG.
As shown by a broken line in FIG.
When the sync is lost, the frequency divider 31 continues counting without being reset, so that the reset pulse R490 is not output as shown in FIG. Therefore,
As shown in FIG. 11F, the output of the up / down counter 37 does not change and the count value up to that point is held.

When the reset pulse R490 is supplied at the timing when the output of the AND circuit 36 is at L level due to the lack of the vertical synchronization pulse Vsync, the up / down counter 37 counts down and the count value becomes 6. Since the count value is 4 or more as described above, the determination that the signal is a standard signal is held.
Further, when the noise N1 is superimposed after, for example, 492 counts, the frequency divider 31 is reset at this timing. Therefore, the subsequently input vertical synchronization pulse Vsync1 enters a dead zone, and is ignored despite being input. That is, for example, resetting before 525 counts may result in the count pulse P525 not being output at the timing of the vertical synchronization pulse. However, even in such a case, the countdown is performed by the up / down counter 37, but if the count value is “4” or more, it is determined that the signal is a standard signal. That is, in this case, when the vertical synchronization pulse Vsync is not input continuously at a predetermined cycle, for example, four times or more due to lack or noise N, it is determined that the signal is a non-standard signal.

[0020]

By the way, in the synchronization determination circuit shown in FIG. 10, when a part of the vertical synchronization pulse Vsync is missing or the vertical synchronization pulse Vsync on which the noise N is superimposed is input, It is always determined that the signal is a non-standard signal. Further, in this state, the frequency divider 31
Is reset by the vertical synchronization pulse Vsy.
Synchronization between nc and the frequency divider 31 may be disturbed.

FIG. 12 is a diagram showing the output timing of each signal when the synchronization is disturbed due to partial omission of the vertical synchronizing pulse Vsync or superimposition of noise. FIG. 12A shows the vertical synchronizing pulse Vsync, and FIG. ) Is the count pulse P525,
FIG. 12C shows the output level of the AND circuit 36, and FIG.
12D shows the reset pulse R490, and FIG. 12E shows the output level of the up / down counter 37.

As shown by broken lines at timings C and D in FIG. 12A, the noises N2 and N3 are lost until the next vertical synchronization pulse Vsync is input after the vertical synchronization pulse Vsync is lost. Is superimposed, the frequency divider 31 is reset at this timing, and the vertical synchronization pulse Vsync2 input in the next cycle is ignored by the dead zone even though it is input. Therefore, if the lack of the vertical synchronization pulse Vsync and the superposition of the noise N are repeated, the synchronization between the vertical synchronization pulse Vsync and the frequency divider 31 is disturbed, and as shown in FIG. The output of the AND circuit 36 goes low at the output timing of the reset pulse P490 (12 (d)) even though the solid line is input at a predetermined cycle (FIG. 12 (c)).

Therefore, the normal vertical synchronization pulse Vsync
12 cannot be measured correctly by the frequency divider 31, and the up / down counter 37 continues to count down as shown in FIG. 12 (e), and eventually determines that the signal is not a standard signal. . As described above, when the lack of the vertical synchronization pulse Vsync and the superposition of the noise N are repeated and the normal vertical synchronization pulse Vsync cannot be measured, the normal synchronization pulse Vsync and the frequency divider 31 are not synchronized until the synchronization between them becomes stable. The determination that the signal is a standard signal continues. Therefore, for example, the vertical synchronization pulse Vsy is generated by a weak electric field or the like.
Even in the case where nc is missing, interpolation processing and the like are not performed, so that there is a problem that an image out of synchronization is displayed.

[0024]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has an oscillation frequency of n times (where n.gtoreq.2) a horizontal synchronization pulse extracted from an input video signal. Oscillating means for generating a clock, first frequency dividing means reset by a vertical synchronizing pulse extracted from the video signal and counting the period of the vertical synchronizing pulse based on the clock, and the first frequency dividing means Timing generating means for outputting a first count pulse having the same cycle as the vertical synchronization pulse in accordance with the count output of the first and second determination means for detecting the presence or absence of the vertical synchronization pulse at the timing of the first count pulse And a second count pulse having the same cycle as the vertical sync pulse or the vertical sync pulse, or a reset corresponding to the second count pulse. A second frequency divider that is reset by a pulse and counts the period of the vertical synchronization pulse based on the clock; and the second count pulse and the reset pulse in response to a count output of the second frequency divider , A second determining means for detecting the presence or absence of the vertical synchronization pulse at the timing of the second count pulse, and the video based on the determination results of the first and second determining means. A third determination unit that determines whether the signal is a standard signal or a non-standard signal, wherein the second frequency division unit determines whether the result of the third determination unit is a standard signal. Is reset by the second count pulse or the reset pulse, and when the determination result is a non-standard signal, the synchronization determination circuit is reset by the vertical synchronization pulse. To configure. Also,
A television receiver is configured with this synchronization determination circuit.

According to the present invention, when the second frequency dividing means is a standard signal, it is reset by the second count pulse and runs by itself, so that the second frequency dividing means is affected by the lack of the vertical synchronizing pulse and the superposition of noise. Never. Therefore, the second determination means determines that the signal is a non-standard signal in the field where the vertical synchronization pulse is missing, but determines that the signal is the standard signal if the vertical synchronization pulse is input to the next field. become able to. As a result, the synchronization performance can be improved without being affected by the missing or noise of the vertical synchronization pulse.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiment of the present invention will be described below with reference to an example in which the present invention is applied to, for example, an NTSC television receiver. FIG. 1 is a diagram showing some circuit blocks of the video system of the television receiver of the present embodiment. The tuner 1 includes, for example, a BS tuner, a CS tuner, a U / V tuner, and the like, and selects a broadcast wave received by the antenna A. The received signal selected by the tuner 1 is supplied to a video signal processing unit 3 via an intermediate frequency amplifier (VIF) 2 and a switch SW. Switch SW is tuner 1
And the external input device (for example, an AV (Audio Visual) device such as a VCR, a laser disk player, etc., or a game device, etc., which are not shown). ) Is selected and supplied to the video signal processing unit 3.

The video signal supply unit 3 performs various kinds of signal processing such as separation of color signals, formation of color difference signals, and extraction of synchronization signals, and supplies video signals of RGB colors to the CRT 4. The synchronization signal extracted here is supplied to the control unit 5. The control unit 5 generates an operation clock synchronized with a horizontal scanning cycle for synchronizing various signal processings in the above-described functional circuits from the input synchronization signal. Also, a command output from a remote commander RC provided with various operation keys, selection keys, and the like is input via the light receiving unit 6 to control channel selection of the tuner 1, switch the switch SW, or output the video signal processing unit 3. , And various image quality adjustments.

The deflection control section 7 forms a horizontal deflection signal H at the timing of the horizontal cycle based on the operation clock output from the control section 5 to which the synchronization information of the video signal is inputted, and attaches it to the neck of the CRT 4. To the deflection yoke 8. In addition, the video signal currently selected by the switch SW is, for example, a broadcast program selected by the tuner 1 or a normal reproduction supplied from an external input device such as a video deck connected to the external input terminal t1 or t2. It is determined whether the signal is a standard signal such as a video, a special playback image supplied from an external input device connected to the external input terminal t1 or t2, or a non-standard signal supplied from a game device. Is configured to do so.

When the video signal currently selected by the deflection processing unit 7 is determined to be a standard signal, the synchronous interpolation processing unit 9 generates a missing signal due to a weak electric field or the like every 262.5 horizontal scanning lines. When there is no vertical synchronization signal, interpolation processing is performed by estimating the vertical synchronization signal before and after the vertical synchronization signal, and the vertical synchronization signal is generated at a predetermined timing.

In this way, even when a vertical synchronizing signal, for example, every 262.5 horizontal scanning lines in the standard signal is missing, a vertical synchronizing signal can be generated by the interpolation processing. When a non-standard signal having no vertical synchronization signal is selected for every five signals, the interpolation processing can not be performed.

Next, the synchronization determination circuit in the deflection controller 7 will be described in detail with reference to FIG. 2, the oscillator 10, the frequency dividers 11, 19, and the timing generators 12, 20 correspond to the oscillator 30, the frequency dividers 31, 38, and the timing generators 32, 39 described above with reference to FIG. . In the present embodiment, the frequency divider 11 that measures the cycle of the vertical synchronization pulse Vsync and the first determination unit that determines the presence or absence of the vertical synchronization pulse Vsync according to the timing of the timing generation unit 12 include flip-flops 14 and 15. ,
The inverter Inv1 and the AND circuit 16 constitute a determination unit Jad1. The vertical synchronizing pulse Vsy generated by the flip-flops 14 and 15, the inverter Inv1, and the AND circuit 16 is used.
The detection of nc is performed in the same manner as in the case described above with reference to FIG. That is, when the vertical synchronization pulse Vsync is detected, the output of the AND circuit 16 becomes H level.

Further, the flip-flops 21 and 22, the inverter Inv2, and the AND circuit 23 detect the presence or absence of the vertical synchronizing pulse Vsync at the timing of the frequency divider 19 for controlling the vertical deflection timing and the timing generator 20. The judging unit Jad2 is configured as the judging means. The operation of detecting the vertical synchronization pulse Vsync is the same as that of the judging unit jad1. The determination unit Jad2 is configured to detect the presence / absence of the vertical synchronization pulse Vsync at this timing based on the count pulse P525b which becomes the L level at the timing of 525 counts output from the timing generation unit 20. The output levels of the judging unit Jad1 and the judging unit Jad2 are configured as third determining means via an OR circuit 17 provided at a subsequent stage, and include, for example, 3 bits for determining a standard / non-standard signal. Is supplied to the up / down counter 18. That is, the output level of the OR circuit 17 becomes the count control output of the up / down counter 18. In addition,
In the present embodiment, the up / down counter is composed of 3 bits, but the number of bits is not limited to this.

An example in which a standard / non-standard signal is determined by the synchronization determination circuit shown in FIG. 2 will be described below with reference to a timing chart shown in FIG. 3A is a clock CLK, FIG. 3B is a vertical synchronizing pulse Vsync, FIG. 3C is a count pulse P525a output from the timing generator 12, and FIG. 3D is an up / down counter. FIG. 3E shows an output level of the AND circuit 16, FIG. 3F shows a count pulse P525b output from the timing generator 20, FIG.
3 (g) schematically shows the output level of the AND circuit 23, FIG. 3 (h) schematically shows the output level of the OR circuit 17, and FIG. 3 (i) schematically shows the count output level of the up / down counter 18.

The initial value of the up / down counter 18 is, for example, 0, and the clock CLK vertical synchronization pulse Vsyn
When c starts to be input, counting up is started. Then, as shown in FIG. 3 (f), if the count value is, for example, "4" or less and it is determined that the signal is a non-standard signal, the switch SW1 is switched to the contact a to switch the OR circuit. 24, the frequency divider 19 is reset by the vertical synchronization pulse Vsync via the AND circuit 25. The vertical synchronization pulse Vsync corresponds to superposition of noise by providing a dead zone up to 492 counts by the reset pulse R492 supplied to the OR circuit 24.
5, the frequency divider 19 is provided at the timing of 575 counts even when the vertical synchronization pulse Vsync is lost.
Can be reset. When it is determined that the signal is a standard signal by counting up the up / down counter 18, the switch SW1 is connected to the contact b, and the frequency divider 19 is switched to the contact b after the point A, and the count pulse P525b is output. Reset and run by itself.

By the way, as shown in FIG. 3B, a part of the vertical synchronization pulse Vsync is lost (shown by a broken line) due to, for example, a weak electric field or the like, and the vertical synchronization pulse Vsync of the next missing period is further lost. If the noise N (indicated by the alternate long and short dash line) is superimposed during this period, the frequency divider 11 is reset by the noise N and starts counting again. When the next vertical synchronization pulse Vsync1 (488 counts after reset) is input, the vertical synchronization pulse Vsy is generated from the noise N.
Since the period up to nc1 is measured, the count pulse
P525a is not output (FIG. 3 (c)), and the output level of the AND circuit 16 becomes L level as shown in FIG. 3 (e). Therefore, the determination unit Jad1 determines that the signal is a non-standard signal.

On the other hand, the judgment unit Jad2 performs the same judgment as the judgment unit Jad1, but at this timing, the count value of the up / down counter 18 is set to, for example, "4".
Since it has been determined that the signal is a standard signal,
The frequency divider 18 runs by the count pulse P525b shown in FIG.

If the up / down counter 18 determines that the signal is a standard signal and the frequency divider 19 is running, the count pulse P525b (FIG. 3F) and the vertical synchronization pulse Vsync (FIG. 3B) ) Are in phase,
As shown by the broken line in FIG. 3B, when a part of the vertical synchronization pulse Vsync is missing, the determination unit Jad2 also determines that the signal is a non-standard signal similarly to the determination unit Jad1.
The output of the AND circuit 23 goes low. Therefore, the output of the OR circuit 16 also becomes L level, and the up / down counter 18 counts down.

However, in the next field, the judgment section
In Jad2, the count signal P525b determines that the signal is a standard signal, and the AND circuit 23 outputs an L signal.
The level is output. Therefore, since it is different from the judgment (non-standard signal) of the judging unit Jad1, the OR circuit 17 takes the OR of the AND circuit 16 and the AND circuit 23 to judge that the signal is a standard signal, and counts the OR output. The control level is supplied to the up / down counter 18. Thus, the up / down counter 18 counts up.

As described above, the OR of the judgment results of the judgment units Jad1 and Jad2 is taken, and the up / down counter 18
By performing the count-up / down, the vertical synchronization pulse Vsync can be determined at a more accurate cycle even when the lack of the vertical synchronization pulse Vsync and the superposition of noise occur.

By the way, as described above,
If the count value of the down counter 18 determines that the signal is a non-standard signal, and the switch SW1 is connected to the contact b, and the apparent vertical synchronization pulse Vsync is missing due to channel switching or the like, the frequency divider 19 The reset is performed by the reset pulse R575 output from the timing generator 20.

FIG. 4 schematically shows a timing chart of each signal in this case. FIG. 4A shows a vertical synchronization pulse Vsync, FIG. 4B shows a count pulse P525a, and FIG.
4C shows the reset pulse R575, FIG. 4D shows the reset pulse R492, and FIG. 4E shows the count pulse P525b. For example, as shown in FIG.
The vertical synchronization pulse Vsync indicated by the broken line in FIG.
If it shifts to the point, the timing at which the frequency divider 11 is reset shifts to the point A accordingly, so that the cycle of outputting the count pulse P525a also shifts as shown in FIG. 3B. . When the vertical synchronization pulse Vsync is shifted, the frequency divider 19 is reset by the reset pulse R575 (point B) shown in FIG. 3C, and the count pulse P525b is changed to the state shown in FIG. ), The data is output at point C, which is the 525th count from point B. Therefore, the cycle of the count pulse P525a and the count pulse P525b may be disturbed, and an error may occur in the determination between the determination unit Jad1 and the determination unit Jad2.

Therefore, for example, as shown in FIG. 5 as another embodiment, an AND circuit 26 for inputting the output level of the judging unit Jad2 and the output level of the up / down counter 18 is provided. The judgment of the judging unit Jad2 is made valid only when the judgment is a standard signal, that is, only when the frequency divider 19 is self-running. As a result, as shown in FIG. 4, when the up / down counter 18 determines that the signal is a non-standard signal, only the determination of the determination unit Jad1 can be validated. Can be prevented from being erroneously determined as a standard / non-standard signal.

The up / down counter 18 may be given a weight so that, for example, when the output of the OR circuit 17 is at the H level, the count is increased by 2, for example, and when the output of the OR circuit 17 is at the L level, the count is decreased by, for example, 2 counts.

Further, in FIG. 2, the judgment unit Jad1 and the judgment unit Jad2
An OR circuit 16 is provided at the subsequent stage to control the count of the up / down counter 18. However, for example, as shown in FIG. 6, it is possible to select the output levels of the judgment unit Jad1 and the judgment unit Jad2. A switch SW2 that can be provided may be provided, and the switching control of the switch SW2 may be controlled according to the determination result of the up / down counter 18.
That is, when the up / down counter 18 determines that the signal is a standard signal and the frequency divider 19 is self-running, it switches to the contact b and ignores the determination of the determination unit Jad1 and only the determination unit Jad2 performs the determination. Make a decision. If the signal is a non-standard signal, the signal is switched to the contact a side to enable only the determination of the determination unit Jad1. Also in this case, it is possible to prevent a malfunction when the up / down counter 18 determines that the signal is a non-standard signal.

Although the above embodiment has been described with reference to an NTSC television receiver as an example, the present invention can be applied to other television systems such as a PAL system and a SECAM system. is there.

[0046]

As described above, according to the present invention, when the second frequency dividing means is a standard signal, it is reset by the second count pulse and runs by itself. , It is possible to detect the presence or absence of a vertical synchronization pulse at a predetermined cycle without being affected by the superposition of the vertical synchronization pulse. Therefore, the second determination means determines that the signal is a non-standard signal in the field where the vertical synchronization pulse is missing, but determines that the signal is the standard signal if the vertical synchronization pulse is input to the next field. become able to. As a result, even when synchronization is disturbed due to lack of a vertical synchronization pulse or superposition of noise, more accurate synchronization determination can be performed. Therefore, according to the present invention, when a missing vertical synchronization pulse occurs, interpolation processing is performed, so that a good synchronized image can be displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a part of a television receiver according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a synchronization determination circuit in the deflection control unit shown in FIG.

FIG. 3 is a diagram illustrating timings of signal waveforms in respective units of the synchronization determination circuit illustrated in FIG. 2;

FIG. 4 is a diagram showing the timing of each signal waveform when the phase of a vertical synchronization pulse changes when it is determined that the signal is an asynchronous signal.

FIG. 5 is a diagram illustrating a modification of the present embodiment.

FIG. 6 is a diagram illustrating a modification of the present embodiment.

FIG. 7 is a diagram illustrating a synchronization determination circuit in a deflection control unit of a conventional television receiver.

FIG. 8 is a diagram illustrating a dead zone for noise superimposed on a vertical synchronization pulse.

FIG. 9 is a diagram illustrating timings of a vertical synchronization pulse and a count pulse.

FIG. 10 is a diagram illustrating an example in which a frequency divider that outputs a vertical deflection timing and a timing generator are separately provided for the synchronization determination circuit illustrated in FIG. 7;

11 is a diagram illustrating timings of signal waveforms of respective units of the synchronization determination circuit illustrated in FIG.

FIG. 12 is a diagram illustrating an example of a case where a conventional synchronization determination circuit makes an erroneous determination due to a missing vertical synchronization pulse and superimposition of noise.

[Explanation of symbols]

3 video signal processing unit, 7 deflection control unit, 10 oscillator,
11, 19 frequency divider, 12, 20 timing generator,
Jad1, Jad2 judgment part, 18, up-down counter, S
W1, SW2 switch, Vsync vertical sync pulse, H
sync Horizontal sync pulse, P525a, P525b count pulse

Claims (4)

[Claims] 1. A synchronization determination circuit for determining from a vertical synchronization pulse of an input video signal whether the video signal is a standard signal conforming to a normal television system or a non-standard signal, An oscillating means for generating a clock having an oscillation frequency of n times (where n ≧ 2) the horizontal synchronization pulse extracted from the video signal; and a vertical synchronization pulse extracted from the video signal and resetting based on the clock. A first frequency divider that counts a cycle of the synchronization pulse; a timing generator that outputs a first count pulse having the same cycle as the vertical synchronization pulse in accordance with a count output of the first frequency divider; First determining means for detecting the presence or absence of the vertical synchronization pulse at the timing of a first count pulse; and A second count pulse having the same cycle as the pulse, or a second frequency divider that is reset by a reset pulse corresponding to the second count pulse and counts the cycle of the vertical synchronization pulse based on the clock. Timing generating means for outputting the second count pulse and the reset pulse in accordance with the count output of the second frequency dividing means; and detecting the presence or absence of the vertical synchronization pulse at the timing of the second count pulse. The second determination means, the first, comprising a third determination means to determine whether the video signal is a standard signal or a non-standard signal based on the determination result of the second determination means, The second frequency dividing means resets with the second count pulse or the reset pulse when the result of the determination by the third determining means is a standard signal. Are bets, when the determination result is non-standard signal is the synchronization determination circuit, characterized in that as being reset by the vertical sync pulse. 2. The synchronization judgment circuit according to claim 1, wherein the judgment by said second judgment means is made valid only when the judgment result is a standard signal. 3. A synchronization judging circuit for judging from a vertical synchronizing pulse of an input video signal whether the video signal is a standard signal or a non-standard signal in a normal television system. In the television receiver, the synchronization determination circuit includes: an oscillating unit that generates a clock having an oscillation frequency that is n times (where n ≧ 2) a horizontal synchronization pulse extracted from the video signal; A first frequency divider that is reset by a synchronization pulse and counts a period of the vertical synchronization pulse based on the clock; and a second frequency divider having the same period as the vertical synchronization pulse according to a count output of the first frequency divider. Timing generating means for outputting one count pulse; and a first detecting means for detecting the presence or absence of the vertical synchronization pulse at the timing of the first count pulse. The vertical synchronization pulse, or a second count pulse having the same period as the vertical synchronization pulse, or a reset pulse corresponding to the second count pulse, and resetting the vertical synchronization pulse based on the clock. A second frequency divider for counting a pulse period; a timing generator for outputting the second count pulse and the reset pulse in accordance with a count output of the second frequency divider; A second determination unit that detects the presence or absence of the vertical synchronization pulse at a pulse timing; and the video signal is a standard signal or a non-standard signal based on a determination result of the first and second determination units. A third determining means for making a determination as to whether the second frequency dividing means is a standard signal when the determination result of the third determining means is a standard signal. A television receiver, wherein the television receiver is reset by a second reset pulse, and is reset by the vertical synchronization pulse when the determination result is a non-standard signal. 4. The television receiver according to claim 3, wherein the determination by the second determination unit is made valid only when the determination result is a standard signal.