JPH1051978A - Power supply backup circuit - Google Patents

Power supply backup circuit

Info

Publication number
JPH1051978A
JPH1051978A JP8206828A JP20682896A JPH1051978A JP H1051978 A JPH1051978 A JP H1051978A JP 8206828 A JP8206828 A JP 8206828A JP 20682896 A JP20682896 A JP 20682896A JP H1051978 A JPH1051978 A JP H1051978A
Authority
JP
Japan
Prior art keywords
memory
power supply
diode
voltage
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8206828A
Other languages
Japanese (ja)
Inventor
Norihiro Hayashi
宣弘 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Okuma Corp
Original Assignee
Okuma Machinery Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Okuma Machinery Works Ltd filed Critical Okuma Machinery Works Ltd
Priority to JP8206828A priority Critical patent/JPH1051978A/en
Publication of JPH1051978A publication Critical patent/JPH1051978A/en
Pending legal-status Critical Current

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  • Stand-By Power Supply Arrangements (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent the malfunction and destruction of a memory, by controlling the voltage difference produced between the voltage of a control signal outputted to the memory from a logic circuit and the power supply voltage of the memory, within the tolerance of the input terminal voltage of the memory, by connecting a diode in parallel with a backup means for the memory. SOLUTION: A diode 10 is a reverse-current preventing diode which is connected in parallel with diodes 8 and 9, connects a power source 1 for device to a memory 3, and prevents an electric current from flowing to the power source 1 and a logic circuit 2 with the purpose of preventing the consumption of a large-capacitance capacitor 5 and a primary battery 4. Since the power source 1 is connected to the memory 3 by means of the diode 10 when the power supply is not interrupted, the forward voltage drops by the amount of one diode. Therefore, the voltage difference produced between the voltage of a control signal outputted to the memory 3 from the logic circuit 2 can be controlled within the tolerance of the input terminal voltage of the memory 3, and the malfunction and destruction of the memory 3 can be prevented.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はメモリやタイマー等
をバックアップするための電源回路に関するものであ
る。
The present invention relates to a power supply circuit for backing up a memory, a timer, and the like.

【0002】[0002]

【従来の技術】半導体のメモリやタイマー等をバックア
ップするための電源としてリチウム電池等の一次電池を
組み込んだものがあり、上記一次電池では電池切れに伴
う交換が必要である。従って、上記一次電池の交換まで
の期間を長くする、または交換を不要にするために大容
量コンデンサを電源回路に組み込んだものがある。
2. Description of the Related Art There is a type in which a primary battery such as a lithium battery is incorporated as a power supply for backing up a memory or a timer of a semiconductor, and the above-mentioned primary battery needs to be replaced when the battery runs out. Therefore, there is a power supply circuit in which a large-capacity capacitor is incorporated in a power supply circuit in order to extend the period until the primary battery is replaced or to eliminate the need for replacement.

【0003】図3は従来のバックアップ機能付き電源回
路を示す回路図である。図3において装置電源1は論理
回路2及びメモリ3へ電力を供給する電源である。論理
回路2は電源が遮断されている時にはバックアップが不
要な回路であり、一方、メモリ3は電源が遮断されてい
る時にもバックアップが必要なメモリである。
FIG. 3 is a circuit diagram showing a conventional power supply circuit with a backup function. In FIG. 3, an apparatus power supply 1 is a power supply for supplying power to the logic circuit 2 and the memory 3. The logic circuit 2 is a circuit that does not need a backup when the power is turned off, while the memory 3 is a memory that needs a backup even when the power is turned off.

【0004】電源が遮断されている時メモリ3をバック
アップするための電力を供給するため一次電池4が一次
電池への充電防止のためダイオード7を介してメモリ3
に接続されている。また、メモリ3への電力の供給及び
一次電池4の消耗を遅らすための大容量コンデンサ5が
保護用の抵抗6及び一次電池4から充電されないように
するためのダイオード9を介してメモリ3に接続されて
いる。ダイオード8は大容量コンデンサ5の消耗を防ぐ
目的から装置電源1及び論理回路2に電流が流れないよ
うにするための逆流防止用ダイオードである。
In order to supply power for backing up the memory 3 when the power is cut off, the primary battery 4 is connected to the memory 3 via a diode 7 to prevent charging of the primary battery.
It is connected to the. In addition, a large-capacity capacitor 5 for delaying power supply to the memory 3 and consumption of the primary battery 4 is connected to the memory 3 via a protection resistor 6 and a diode 9 for preventing the primary battery 4 from being charged. Have been. The diode 8 is a backflow prevention diode for preventing current from flowing to the device power supply 1 and the logic circuit 2 for the purpose of preventing consumption of the large-capacity capacitor 5.

【0005】図3の電源回路によれば電源が遮断されて
いない時には装置電源1から論理回路2及びメモリ3に
直接電力を供給すると共にダイオード8、抵抗6を介し
て大容量コンデンサ5を充電する。また、停電、電源O
FF等により電源が遮断された時には先ず大容量コンデ
ンサ5からメモリ3に電力を供給し、大容量コンデンサ
5の電圧が低下した後は一次電池4により電力を供給し
てメモリ3の内容を保持している。
According to the power supply circuit shown in FIG. 3, when the power supply is not cut off, power is directly supplied from the device power supply 1 to the logic circuit 2 and the memory 3 and the large-capacity capacitor 5 is charged via the diode 8 and the resistor 6. . Power failure, power supply O
When the power is cut off by the FF or the like, first, power is supplied from the large-capacity capacitor 5 to the memory 3, and after the voltage of the large-capacity capacitor 5 decreases, power is supplied from the primary battery 4 to retain the contents of the memory 3. ing.

【0006】[0006]

【発明が解決しようとする課題】従来の技術において
は、図4の従来の電源回路の動作を説明するための波形
図に示す如く電源が遮断されていない時メモリ3にはダ
イオード8及びダイオード9を介して電力が供給される
ため、ダイオードの順電圧をVfとすると2倍のVfの
電圧降下が発生する。
In the prior art, as shown in the waveform diagram for explaining the operation of the conventional power supply circuit in FIG. 4, when the power is not cut off, the diode 8 and the diode 9 are stored in the memory 3. , A double voltage drop of Vf occurs when the forward voltage of the diode is Vf.

【0007】例えば、装置電源1の出力電圧を5.0
V、Vfを0.5Vとするとメモリ3の電源電圧は4.
0Vとなる。一方、装置電源1と直接接続されている論
理回路2の電源電圧は5Vとなり、論理回路2がメモリ
3に対して出力するコントロール信号の電圧はCMOS
出力であれば4.9Vである。従って、メモリ3の入力
端子電圧許容値が電源電圧+0.5Vであるとすると、
電源電圧が4.0Vのメモリ3に4.9Vの入力端子電
圧がかかり、入力端子電圧許容値を0.4V越えるた
め、メモリの誤動作、場合によってはメモリの破壊とい
う問題があった。
For example, the output voltage of the device power supply 1 is set to 5.0
Assuming that V and Vf are 0.5 V, the power supply voltage of the memory 3 is 3.
It becomes 0V. On the other hand, the power supply voltage of the logic circuit 2 directly connected to the device power supply 1 is 5 V, and the voltage of the control signal output from the logic circuit 2 to the memory 3 is CMOS.
For output, it is 4.9V. Therefore, assuming that the allowable input terminal voltage of the memory 3 is the power supply voltage + 0.5 V,
Since the input terminal voltage of 4.9 V is applied to the memory 3 having the power supply voltage of 4.0 V, which exceeds the allowable input terminal voltage of 0.4 V, there is a problem that the memory malfunctions and, in some cases, destroys the memory.

【0008】本発明が解決しようとする課題は論理回路
がメモリに対して出力するコントロール信号の電圧とメ
モリの電源電圧との間に生じる電圧差をメモリの入力端
子電圧許容値以内にし、メモリの誤動作、破壊という問
題を解決することにある。
The problem to be solved by the present invention is to reduce the voltage difference between the voltage of the control signal output from the logic circuit to the memory and the power supply voltage of the memory to within the allowable value of the input terminal voltage of the memory. It is to solve the problem of malfunction and destruction.

【0009】[0009]

【課題を解決するための手段】本発明は半導体のメモリ
やタイマー等をバックアップするための電源回路におい
て、装置電源からのみ、電源の供給を受けるバックアッ
プ不要な素子と、装置電源またはバッテリまたは大容量
コンデンサから電源の供給を受けるバックアップの必要
な素子と、前記装置電源と前記大容量コンデンサを接続
する第1のダイオードと、前記第1のダイオードと直列
に接続され前記大容量コンデンサと前記バックアップの
必要な素子を接続する第2のダイオードと、前記バッテ
リと前記バックアップの必要な素子の電源を接続する第
3のダイオードにより構成される電源バックアップ回路
と、前記第1のダイオードと前記第2のダイオードの直
列接続回路と並列に接続し、前記装置電源と前記バック
アップの必要な素子を接続する第4のダイオードを備え
るものである。
SUMMARY OF THE INVENTION The present invention relates to a power supply circuit for backing up a semiconductor memory, a timer, and the like. An element which needs a backup to be supplied with power from a capacitor, a first diode which connects the device power supply and the large capacity capacitor, and which is connected in series with the first diode and which has the large capacity capacitor and the backup required A power supply backup circuit composed of a second diode for connecting a power source of the battery and the element for which the backup is necessary; Connected in parallel with a series connection circuit, the device power supply and the In which a fourth diode that connects.

【0010】[0010]

【実施の形態】図1は本発明の一実施形態を示す電源回
路であり、従来技術に示す図3と同一番号にて示されて
いる構成要素についての機能は同一であるので説明を省
略する。ダイオード10はダイオード8とダイオード9
とに並列に接続し、装置電源1とメモリ3を接続するダ
イオードであり、大容量コンデンサ5及び一次電池4の
消耗を防ぐ目的から装置電源1及び論理回路2に電流が
流れないようにするための逆流防止用のダイオードであ
る。
FIG. 1 shows a power supply circuit according to an embodiment of the present invention. The functions of the components denoted by the same reference numerals as those in FIG. . Diode 10 is diode 8 and diode 9
To connect the device power supply 1 and the memory 3 in parallel, and to prevent current from flowing through the device power supply 1 and the logic circuit 2 for the purpose of preventing the consumption of the large-capacity capacitor 5 and the primary battery 4. Is a diode for preventing backflow.

【0011】図2の本発明の電源回路の動作を説明する
ための波形図に示す如く、電源が遮断されていない時に
は装置電源1とメモリ3はダイオード10により接続さ
れているため、ダイオード1個分の順電圧Vfの電圧降
下となる。例えば、発明が解決しようとする課題に示す
と同様の出力電圧値ではメモリ3の電源電圧は4.5V
であり、入力端子電圧は4.9Vで入力端子電圧許容値
以内となる。
As shown in the waveform diagram for explaining the operation of the power supply circuit of the present invention in FIG. 2, when the power supply is not cut off, the device power supply 1 and the memory 3 are connected by the diode 10, so that one diode is used. A forward voltage Vf for one minute. For example, with the same output voltage value as described in the problem to be solved by the invention, the power supply voltage of the memory 3 is 4.5 V
The input terminal voltage is 4.9 V, which is within the allowable value of the input terminal voltage.

【0012】従って、ダイオード10をダイオード8と
ダイオード9とに並列に接続し、装置電源1とメモリ3
を接続することにより論理回路2がメモリ3に対して出
力するコントロール信号の電圧とメモリ3の電源電圧と
の間に生じる電圧差をメモリの入力端子電圧許容値以内
とすることができ、メモリ3の誤動作、破壊を防止でき
る。
Therefore, the diode 10 is connected in parallel with the diode 8 and the diode 9, and the device power supply 1 and the memory 3 are connected.
, The voltage difference generated between the voltage of the control signal output from the logic circuit 2 to the memory 3 and the power supply voltage of the memory 3 can be set within the allowable value of the input terminal voltage of the memory 3. Malfunction and destruction can be prevented.

【0013】[0013]

【発明の効果】本発明によればメモリへのバックアップ
手段と並列にダイオードを接続することにより、論理回
路がメモリに対して出力するコントロール信号の電圧と
メモリの電源電圧との間に生じる電圧差をメモリの入力
端子電圧許容値以内とすることができるので、メモリは
誤動作、破壊されることなく安定に動作させることがで
きる。
According to the present invention, by connecting the diode in parallel with the backup means for the memory, the voltage difference generated between the voltage of the control signal output to the memory by the logic circuit and the power supply voltage of the memory is obtained. Can be set within the allowable range of the input terminal voltage of the memory, so that the memory can be stably operated without malfunction or destruction.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施形態を示すバックアップ機能
付き電源回路の回路図である。
FIG. 1 is a circuit diagram of a power supply circuit with a backup function according to an embodiment of the present invention.

【図2】 本発明の電源回路の動作を説明するための波
形図である。
FIG. 2 is a waveform chart for explaining the operation of the power supply circuit of the present invention.

【図3】 従来のバックアップ機能付き電源回路の回路
図である。
FIG. 3 is a circuit diagram of a conventional power supply circuit with a backup function.

【図4】 従来の電源回路の動作を説明するための波形
図である。
FIG. 4 is a waveform chart for explaining the operation of a conventional power supply circuit.

【符号の説明】[Explanation of symbols]

1 装置電源、2 論理回路、3 メモリ、4 一次電
池、5 大容量コンデンサ、6 抵抗、7〜10 ダイ
オード。
1 device power supply, 2 logic circuits, 3 memories, 4 primary batteries, 5 large capacity capacitors, 6 resistors, 7-10 diodes.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体のメモリやタイマー等をバックアッ
プするための電源回路において、装置電源からのみ、電
源の供給を受けるバックアップ不要な素子と、装置電源
またはバッテリまたは大容量コンデンサから電源の供給
を受けるバックアップの必要な素子と、 前記装置電源と前記大容量コンデンサを接続する第1の
ダイオードと、前記第1のダイオードと直列に接続され
前記大容量コンデンサと前記バックアップの必要な素子
を接続する第2のダイオードと、前記バッテリと前記バ
ックアップの必要な素子の電源を接続する第3のダイオ
ードにより構成される電源バックアップ回路と、 前記第1のダイオードと前記第2のダイオードの直列接
続回路と並列に接続し、前記装置電源と前記バックアッ
プの必要な素子を接続する第4のダイオードを備えるこ
とを特徴とする電源バックアップ回路。
In a power supply circuit for backing up a semiconductor memory, a timer, or the like, an element that does not need to be supplied with power only from an apparatus power supply, and is supplied with power from an apparatus power supply or a battery or a large-capacity capacitor. An element that needs to be backed up; a first diode that connects the device power supply and the large-capacity capacitor; and a second diode that is connected in series with the first diode and connects the large-capacity capacitor and the element that needs to be backed up. A power supply backup circuit composed of a third diode for connecting a power supply of the battery and the element requiring backup, and a parallel connection with a series connection circuit of the first diode and the second diode And a fourth die for connecting the device power supply and the element requiring backup. Power backup circuit, characterized in that it comprises a chromatography mode.
JP8206828A 1996-08-06 1996-08-06 Power supply backup circuit Pending JPH1051978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8206828A JPH1051978A (en) 1996-08-06 1996-08-06 Power supply backup circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8206828A JPH1051978A (en) 1996-08-06 1996-08-06 Power supply backup circuit

Publications (1)

Publication Number Publication Date
JPH1051978A true JPH1051978A (en) 1998-02-20

Family

ID=16529755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8206828A Pending JPH1051978A (en) 1996-08-06 1996-08-06 Power supply backup circuit

Country Status (1)

Country Link
JP (1) JPH1051978A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1300911C (en) * 2002-12-05 2007-02-14 华为技术有限公司 Circuit for preventing DC power supply voltage drop
DE102005061830B3 (en) * 2005-12-23 2007-06-28 Siemens Ag Österreich Backup circuit, e.g. for consumer units like electronic memory elements and timers, has a transistor and a charge-coupled memory device to connect into a reference potential/voltage
WO2007031355A3 (en) * 2005-09-14 2007-09-20 Siemens Ag Oesterreich Backup circuit with charge accumulator
CN100346555C (en) * 2003-08-01 2007-10-31 华为技术有限公司 Capacitive circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1300911C (en) * 2002-12-05 2007-02-14 华为技术有限公司 Circuit for preventing DC power supply voltage drop
CN100346555C (en) * 2003-08-01 2007-10-31 华为技术有限公司 Capacitive circuit
WO2007031355A3 (en) * 2005-09-14 2007-09-20 Siemens Ag Oesterreich Backup circuit with charge accumulator
DE102005061830B3 (en) * 2005-12-23 2007-06-28 Siemens Ag Österreich Backup circuit, e.g. for consumer units like electronic memory elements and timers, has a transistor and a charge-coupled memory device to connect into a reference potential/voltage
WO2007073950A3 (en) * 2005-12-23 2007-10-04 Siemens Ag Oesterreich Backup circuit comprising a charge storage device

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