JPH1054865A - Specifying method for electrostatically broken down place in fet integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a specifying method in which a broken down place in an FET integrated circuit due to static electricity is specified easily. SOLUTION: A C-MOS inverter circuit 10 is replaced by a simple equivalent circuit 20 which contains capacitors 21 to 32 and a resistance 18, potential distributions in respective parts of the capacitors 21 to 32 are simulated and computed when a power-supply voltage is applied to the equivalent circuit 20, and potential distributions of respective MOS-FET's 11 to 16 inside the C-MOS inverter circuit 10 are given immediately before static electricity is applied. A place in which an overvoltage is applied is specified by the potential distributions, and the MOS-FET's 11 to 16 in which there is a possibility of being broken down electrostatically can be specified. Consequently, it is possible to easily specify a place which is broken down by static electricity in the C-MOS inverter circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for specifying a broken portion of a FET (field effect transistor) integrated circuit due to static electricity.

[0002]

2. Description of the Related Art Recently, static electricity is generated due to friction generated in an assembly process and the like, and a package (envelope) of an integrated circuit (IC) is charged, and the charged package is discharged. The so-called electrostatic destruction, in which each element in an integrated circuit is damaged by discharging for some reason, has occurred frequently as the scale and density of integrated circuits have increased. This electrostatic destruction occurs when a high-speed and high-voltage impulse voltage is applied from a package to an internal integrated circuit via an external lead terminal, and a PN junction or an oxide film constituting each element in the integrated circuit or a wiring film between the elements is formed. In many cases, a large current flows to generate excessive heat, melt and break down. As a method for evaluating such electrostatic discharge (ESD), a package charging method has been conventionally known. In recent years, a broken portion of an integrated circuit due to static electricity can be estimated to some extent by simulation calculation of an equivalent circuit. FIG. 3 shows a test circuit of the package charging method. In FIG. 3, 1 is an integrated circuit, 1a is a package, 2 is an external lead terminal, 3 is a metal plate, 4 is an applied voltage source as an electrostatic source, and 5 is a switch. , 6 indicate the equivalent impedance of the object on the discharge path.

[0003]

However, when each element constituting the integrated circuit is an element having a complicated structure such as an FET, its equivalent circuit is composed of a current source, a large number of capacitive elements, resistance elements, and the like. Therefore, the equivalent circuit of the entire integrated circuit becomes complicated. Therefore, when static electricity is applied to the FET integrated circuit, it is extremely complicated to obtain the potential distribution of each part of the equivalent circuit of the FET integrated circuit by simulation calculation. Therefore, it has been extremely difficult to specify a broken portion of the FET integrated circuit due to static electricity by the conventional method.

Therefore, the present invention replaces the FET integrated circuit with a simple equivalent circuit including a capacitor, thereby achieving FE
It is an object of the present invention to provide a method capable of easily specifying a broken portion of a T integrated circuit due to static electricity.

[0005]

SUMMARY OF THE INVENTION According to the present invention, there is provided a method for identifying an electrostatic breakdown point of an FET integrated circuit, comprising the steps of: measuring a capacitance between the respective terminals of the FET integrated circuit having a plurality of terminals; Replacing the FET integrated circuit with an equivalent circuit including a capacitor, and calculating a potential distribution of each part of the equivalent circuit by a simulation calculation when a power supply voltage is applied to the equivalent circuit;
A step of specifying a location having an excessive potential from the potential distribution of each of the parts.

[0006] The FET integrated circuit is replaced with a simple equivalent circuit including a capacitor, and the potential distribution of each part of the equivalent circuit when a power supply voltage is applied to the equivalent circuit is calculated by simulation. The potential distribution of each element in the integrated circuit is given. By specifying a location to which an excessive voltage is applied from these potential distributions, an element that may be damaged by static electricity can be specified. Therefore, it is possible to easily specify a broken portion of the FET integrated circuit due to static electricity.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for specifying a portion where an electrostatic discharge is destroyed in an FET integrated circuit according to the present invention will be described below with reference to FIGS. FIG. 1 shows a C-MOS (complementary MOS) inverter circuit 10 as an FET integrated circuit used in the present embodiment. In the C-MOS inverter circuit 10 of FIG. 1, P-channel MOS-FETs 11 to 13 and N-channel MOS-FETs 14 to 16 are respectively connected in a pair to form a three-stage C-MOS inverter. In FIG. 1, reference numeral 17 denotes a stray capacitance, reference numeral 18 denotes a resistor, and power supply voltages V _DD and V _SS are normally fixed at +5 V and ground potential (0 V), respectively.

Next, a description will be given of a method of specifying a portion where static electricity is destroyed in the C-MOS inverter circuit 10 shown in FIG.
First, the P-channel MOS-FETs 11 to 13 and the N-channel MOS-FE in the C-MOS inverter circuit 10
The capacitance between the gate and the source terminal and between the gate and the drain terminal of T14 to T16 are measured with a capacitance meter or the like. Subsequently, based on the measured values of the capacitance between the gate and the source terminal and between the gate and the drain terminal of the P-channel MOS-FETs 11 to 13 and the N-channel MOS-FETs 14 to 16, the C-MOS inverter shown in FIG. P-channel MOS-FETs 11 to 13 and N of circuit 10
The channel MOS-FETs 14 to 16 and the resistor 18 are shown in FIG.
Is replaced by an equivalent circuit 20 including capacitors 21 to 32 and a resistor 18 as shown in FIG. After that, when a constant power supply voltage V _DD = + 5 V and V _SS = 0 V are applied to the equivalent circuit 20 using a computer (circuit simulator) incorporating a circuit simulation program such as SPICE, each point of the equivalent circuit 20 ( The potential at points A to D in FIG. 2) is calculated by simulation calculation. At this time, for example, if the capacitance of each of the capacitors 25 to 32 is extremely smaller than the stray capacitance 17 of the C-MOS inverter circuit 10,
Since the impedance of the stray capacitance 17 is extremely small, the potential at the point C approaches V _SS = 0 V without limit. Therefore, in this case, the voltage across the capacitor 29 becomes approximately 5 V, so that the P-channel MOS-FET 13
It can be seen that an extremely large voltage is applied between the gate and source terminals of FIG. Therefore, the element most likely to be damaged by static electricity can be specified as the P-channel MOS-FET 13. Note that the present inventor has identified the C-MOS specified in the present embodiment.
It was confirmed by experiments that the destruction point of the inverter circuit 10 and the actual destruction point when static electricity was applied to the C-MOS inverter circuit 10 under the same conditions as in the present embodiment by the package charging method shown in FIG. .

In this embodiment, the C-MOS inverter circuit 10 is replaced with a simple equivalent circuit 20 composed of capacitors 21 to 32 and a resistor 18, and the equivalent circuit 20 has a power supply voltage V
_DD, the capacitor in the case of applying the V _SS 21~32
Of the C-MOS inverter circuit 10 immediately before the static electricity is applied by calculating the potential distribution of the
Of the respective MOS-FETs 11 to 16 are given. By specifying a location where an excessive voltage is applied from these potential distributions, M
OS-FET can be specified. Therefore, the location where the C-MOS inverter circuit 10 is destroyed by the static electricity can be easily specified, and the countermeasure change of the element in the location susceptible to the electrostatic breakdown can be made at the circuit design stage. .

[0010] Embodiments of the present invention are not limited to the above embodiments, and various modifications are possible. For example, in the above-described embodiment, the case where the C-MOS inverter circuit is used as the FET integrated circuit has been described. However, the present invention is not limited to the C-MOS inverter circuit.
Other MOS-FET integrated circuits such as gates or MOS-F
The present invention can be applied to an insulated gate FET integrated circuit other than ET. In the above embodiment, the case where the FET integrated circuit is constituted by the MOS-FET and the resistor is shown. However, the case where there is no resistor may be employed. Elements may be included.

[0011]

According to the present invention, it is possible to easily specify a portion of a FET integrated circuit that is destroyed by static electricity by a simulation calculation of a simple equivalent circuit including a capacitor. By identifying in advance the locations that are susceptible to electrostatic damage and changing the countermeasures for those locations, the F in the assembly process can be reduced.
This makes it possible to prevent electrostatic breakdown of the ET integrated circuit. In particular, the effects of the present invention are remarkable in a multi-element and high-density integrated circuit such as an LSI (large-scale integrated circuit).

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a C-MOS inverter circuit used in an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a capacitor equivalent circuit of the C-MOS inverter circuit shown in FIG.

FIG. 3 is a test circuit diagram schematically showing a package charging method.

[Explanation of symbols]

1. . . Integrated circuit, 1a. . . Package 2. . . 2. external lead terminals; . . 3. metal plate; . . Applied voltage source,
5. . . Switch, 6. . . Equivalent impedance, 1
0. . . C-MOS inverter circuit (FET integrated circuit), 11-13. . . P-channel MOS-FET, 1
4-16. . . N-channel MOS-FET, 17. . .
Stray capacitance, 18. . . Resistance, 20. . . Equivalent circuit, 21
~ 32. . . Capacitor

Claims (1)

[Claims] A step of measuring a capacitance between the respective terminals of the FET integrated circuit having a plurality of terminals; a step of replacing the FET integrated circuit with an equivalent circuit including a capacitor from the capacitance; A step of calculating a potential distribution of each part of the equivalent circuit when a power supply voltage is applied to the equivalent circuit by a simulation calculation; anda step of specifying a location of a potential which is excessive than the potential distribution of each part. Method for specifying the location of an electrostatic breakdown in a FET integrated circuit.