JPH1055314A - Cache memory controller - Google Patents

Abstract

(57) [Problem] To provide a cache memory control device capable of reducing cache access by unnecessary snoops and guaranteeing cache consistency at high speed. An unnecessary cache snoop is reduced by using both a snoop method and a directory method. For this purpose, the main memory controller 110 stores the state of the cache in the state storage unit 112.
(Including a directory) to determine whether or not snooping is required and to continue snooping only when snooping is required, and to notify cache controllers 104 to 106 of snooping suspension when snooping is not required. Emits a signal. Cache controller 1
In steps 04 to 106, when the snoop interruption signal is received, the snoop is interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control device for a multiprocessor system which guarantees cache coherency by a directory method or a snoop method, and more particularly to a control method for guaranteeing data consistency among a plurality of cache memories. The present invention relates to a cache memory control device that performs high-speed and efficient.

[0002]

2. Description of the Related Art As a method of guaranteeing data consistency between cache memories in a multiprocessor system,
Generally, a method called a directory method and a method called a snoop method are known. See David A. Patterson, John for the directory and snoop methods.
L. Hennessy, Shinji Tomita, et al., "Computer Architecture-A Quantitative Approach to Design, Realization, and Evaluation-" (Published by Nikkei BP, December 25, 1992) PP.478-486
It is described in. The directory method has a table (directory) for managing the state of caching of the data with respect to the entire main memory, and first examines the table (directory) for a memory access started by a certain processor. If it is found that the desired latest data exists only in a certain cache, not in the main memory, the data is accessed for that cache.

As a conventional example adopting the directory system, there is one disclosed in Japanese Unexamined Patent Publication No. Hei 4-245350, "Cache Matching System". The publication discloses that in a memory shared by a plurality of processors, data in the memory is stored in a cache of each processor in any holding state (a first state in which data is not held in any cache of each processor). , A second state held only in the cache of one of the processors, and a third state held in the caches of two or more of the processors) (Table) or tag information (table) having a bit number equal to the number of processors indicating whether data in the memory is held in the cache of each processor, and referring to the tag information. When a memory write access from the processor occurs,
This document describes that unnecessary matching processing is not performed in a processor that does not originally require matching processing.

In the directory system, a necessary cache access is performed after a table (tag information) is always checked. Therefore, if data exists in another cache, the access time becomes long. This was the cause of performance degradation. Also, in a cache system that guarantees the consistency of the cache by the conventional directory method, it is necessary to provide a directory for the entire main storage capacity. Therefore, the directory needs to be increased as the capacity of the main memory increases. Was.

[0005] On the other hand, the snoop method is a method for checking whether or not all caches simultaneously store a copy of data corresponding to an address of a memory access started by a certain processor. The snoop method has an advantage that the check can be performed at a relatively high speed because all the caches check whether or not there is desired data in the own cache simultaneously with the access to the main memory. However, with the recent increase in the speed of processors, a memory device often has a cache of two or three layers in addition to the main memory. In this case, the memory access is smaller than that of the snoop of the cache of all the layers. There has been a case where it can be performed faster. Therefore, there is a problem that data cannot be returned to the processor in order to wait for the end of the snoop, even though the main memory access has been completed.

In many cases, the transfer unit (block) between the main memory and the cache is larger than the transfer unit (line) between the cache and the processor. The need for snoops is increasing. In such a case, if snooping is performed unconditionally for all memory accesses, the traffic on the bus increases, and further, the bus is saturated. Further, while snooping the cache of each hierarchy, access from the processor to the cache is suppressed, which causes a problem that the performance of the entire multiprocessor system is reduced.

A first object of the present invention is to provide a cache memory control device capable of ensuring high-speed cache consistency in a multiprocessor system. A second object of the present invention is to provide a cache memory control device capable of reducing cache access due to unnecessary snoops and improving system performance. A third object of the present invention is to provide a cache memory control device capable of reducing the capacity of a directory in a cache system that guarantees the consistency of a cache by a directory method.

[0008]

According to a first aspect of the present invention, there is provided a cache memory control apparatus (see FIGS. 1 to 5) for a snoop system in a multiprocessor system having a cache in order to achieve the first and second objects. And a directory method are used together to reduce unnecessary cache snooping. More specifically, state storage means (112) indicating the state of caching of data on the main memory (111), and whether or not snooping of another cache is necessary depending on the contents of the state storage means (112) Determination circuit block (20)
2), an interrupt signal control circuit block (203) for issuing a snoop interrupt signal based on the determination result of the determination circuit block (202), and each cache controller (1).
04 to 106) to the snoop control block (302)
And an interruption circuit block (303). That is, in response to an access from the processor, the snoop of each cache is searched at the same time as the state storage means (112) indicating the state of the caching. As a result, if it is determined that the snoop is unnecessary, the snoop is terminated. Instead of waiting for snooping, snoop is interrupted and data is returned to the processor.

In order to achieve the first and second objects, the cache memory control device according to the present invention further comprises a snoop interruption signal (130) for notifying a snoop interruption to each cache memory; (104 to 106), the snoop interruption signal (1
An interrupt circuit block (303) for interrupting the snoop when 30) is received is provided. That is, in the first object, when it is determined that the snoop is unnecessary, the interruption of the snoop is notified to each cache controller, and the current snoop or the snoop currently waiting is stopped. Like that.

In order to achieve the first and second objects, the cache memory control device of the present invention (see FIGS. 6 to 8) performs only a snoop on a specific line for access to a block. Circuit and
State storage means (412) representing the state of caching of data on the main memory, a determination circuit block (502) for determining whether or not snooping of another cache is necessary based on the contents of the state storage means; As a result of the determination by the determination circuit block (502), when it is determined that snoop is unnecessary for the data corresponding to the block including the address, the data of the entire block is output to the cache controller, and the snoop is required. If it is found that there is, a line transfer control circuit that reports to the main memory access control circuit block (504) that the transfer is switched to transfer of only a specific line, and notifies the cache controller of information transferred to the specific line. A block (503) is provided.

The cache memory control device of the present invention (FIG. 9)
In order to achieve the third object, the cache (702, 802)
A cache information signal (1000) is provided between the cache (702, 802) and the directory (1100) according to the cache information signal, if necessary, when the cache state changes. ), And when a DMA occurs, the cache information signals invalidation of the cache data from the directory (1100) and writing back of the cache data to the main memory (1200) to the cache (702, 802) by the cache information signal. I am trying to do it.

That is, by using the cache information signal, the cache state and the directory state can always be matched, and as a result, the cache snoop can be optimized with a minimum directory capacity. As a result, the directory only needs to have the total cache capacity, and cache snooping is not required when a directory mishit occurs in the DMA. Is instructed by the cache information signal, so that it is not necessary to determine the cache hit.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. (First Embodiment) In a first embodiment of the present invention, if it is determined that snoop is unnecessary by referring to the state storage means indicating the state of caching, the snoop is interrupted without waiting for the end of snoop. It is like that. FIG. 1 is a diagram showing the overall system configuration of the first embodiment of the present invention. In the figure, reference numerals 101 to 103 denote processors 1 to n and 107 to 1 constituting a multiprocessor system, respectively.
Reference numeral 09 denotes write-back type caches 1 to n connected to the processors 1 to n, respectively, and 104 to 106 denote cache controllers 1 to n for controlling the caches 1 to n, respectively.
It is. Reference numeral 111 denotes a main memory, and 112 denotes a state storage unit. 110 controls the main memory (111) via the signal group (128), and controls the signal group (12).
9) is a main memory controller for controlling the state storage means (112).

The cache controller 1 (104) sends the signal to the processor 1 (101) via the signal group (121) and the cache 1 (107) via the signal group (124).
It is connected to the. Similarly, cache controller 2
(105) is the processor 2 (10) via the signal group 122.
2) and via the signal group (125)
(108) and connected to the cache controller n (1
06) is transmitted to the processor n (10) through the signal group (123).
3) and via the signal group (126)
(109). The cache controllers 1 (104) to n (106) and the main memory controller (110) are connected to each other via a signal group (127), and data transfer and snoop control are performed via this signal group (127). Done. The signal (130) is a snoop interruption signal sent from the main memory controller (110) to each of the cache controllers 1 (104) to n (106).

FIG. 2 shows a main memory controller (110).
FIG. 3 is a diagram showing an internal configuration of the device. As shown in the figure, the main memory controller (110) includes a main memory access control block (201) and a determination circuit block (20).
2) is included. Main memory access control block (20
1) comprises a main memory access control circuit (204) for controlling writing and reading to and from the main memory (111) and a state storage means control circuit (205) for controlling writing and reading to and from the state storage means (112);
The determination circuit block (202) determines whether or not to interrupt snoop based on the contents of the state storage means read by the state storage means control circuit (205) of the main memory access control block (201), and determines whether or not to interrupt the snoop. Block (20
Report to 3). Interruption signal control circuit block (203)
Is a block that generates a snoop interruption signal (130) and sends it to the cache controllers 1 (104) to n (106).

FIG. 3 shows the cache controller 1 (10
It is a figure which shows the internal structure of 4). As shown in the figure, the cache controller 1 (104) includes a cache access control block (301), a snoop control block (302), and a suspension circuit block (303). The interruption circuit block (303) is provided with an interruption signal control circuit block (20) of the main memory controller (110).
This is a block that determines whether the snoop interruption signal is valid or invalid based on the snoop interruption signal (130) sent from 3). If the snoop control block (302) determines that the snoop interruption signal is valid, the snoop control block (302) interrupts the cache access block (30).
The access control block (301) notifies the snoop interruption to the snoop control block (3).
02) is a block for interrupting the snoop process when the snoop interruption is notified from 02). The other cache controllers 2 (105) to n (106) have the same configuration as the cache controller 1 (104).

FIG. 4 is a diagram showing the position of the state storage means (112) corresponding to each block in the memory space of the main memory (111). Here, the block is a unit managed in the cache. As shown in the figure, the state storage means (112) is provided in the main memory (11).
Each block in the memory space of 1) has one table entry.

FIG. 5 shows the state storage means (11) shown in FIG.
It shows the definition of the contents of the table entry of 2). Here, each entry of the state storage means (112) is composed of two bits, and the value of the entry is (a) "00".
In the case of (b), the data of the block is not stored in any cache, and in the case of (b) "01", the data of the block is stored in at least one cache, and the content thereof matches the main memory. (C)
In the case of "10", it means that the data of the block is stored in at least one cache and the content does not match the main memory. (d) "11" is undefined.

<Read Access> Next, the operation in read access from the processor will be described in detail. When the processor 1 (101) requests read access,
First, the cache controller 1 (104) checks whether or not data corresponding to the address is stored in the cache 1 (107) by using an address array (not shown). (A) In the case of a cache 1 (107) hit If the data at the address is stored in the cache 1 (107) (hit), the cache controller 1 (1)
04) reads the data from the cache 1 (107), sends it to the processor 1 (101), and completes the read access.

(B) In the case of a cache 1 (107) mishit On the other hand, if the data at the address is not stored in the cache 1 (107), the cache controller 1 (1)
04) sends the data read request signal of the address to the main memory controller (11) via the signal group (127).
0). The main memory controller (110)
Access to the main memory (111) is started by the information (read request signal, address signal, other signal) of the signal group (127). Meanwhile, at the same time, the cache controller 2 (105) to the cache controller n (106)
Starts snooping of the cache 2 (108) to the cache n (109) according to the information of the signal group (127).

In the main memory controller (110), first, the main memory (111) and the state storage means (112) respond to the address to be accessed by the processor 1 (101) by the main memory access control block (201). Then, the following operations are performed by the determination circuit block (202) in accordance with the 2-bit value read from the state storage means (112). (A) In the case of "00": a value read from the main memory (111) is transmitted to the cache controller 1 (104) via the signal group (127), and the snoop interruption signal (130) is enabled. Interrupt snooping of other caches. Further, the contents of the state storage means (112) are updated to "01". (B) In the case of "01": a value read from the main memory (111) is sent to the cache controller 1 (104) via the signal group (127), and the snoop interruption signal (130) is enabled. Interrupt snooping of other caches. The contents of the state storage means (112) are not changed. (C) In the case of "10": invalidating the value read from the main memory (111), invalidating the snoop interruption signal (130), and continuing the snoop of the other cache. As a result of the snoop, the cache having the latest data sends the latest data to the cache controller 1 (104) via the signal group (127). The main memory controller (110) writes the latest data transmitted via the signal group (127) to the main memory (111). Further, the contents of the state storage means (112) are updated to "01".

The cache controller 1 (104)
It receives the data sent from the main memory controller (110), updates the cache 1 (107), and sends the data to the processor 1 (101). On the other hand, the other cache controllers 2 (10
5) to the cache controller n (106) receive the snoop interruption signal (130) sent from the main memory controller (110) in the interruption circuit block (303), and perform the snoop control if the snoop interruption signal (130) is valid. The snoop is interrupted by transmitting the information to the block (302). If the snoop interruption signal (130) is invalid, the snoop is continued as it is. As a result, if the latest data is in any cache, the snoop is interrupted. The latest data is transmitted to the cache controller 1 via the signal group (127).
The process of sending to (104) is performed.

<Write Access> Next, the operation in the write access from the processor will be described in detail. When the processor 1 (101) requests a write access,
First, the cache controller 1 (104) checks whether the data corresponding to the address is stored in the cache 1 (107) (cache hit) or not (cache miss). (A) In the case of a cache 1 (107) hit If the data of the address is stored in the cache 1 (107), the cache controller 1 (104)
The write data is stored in the cache 1 (107) and the access is completed (in the case of a write-back cache).

(B) In the case of a cache 1 (107) mishit On the other hand, if the data of the address is not stored in the cache 1 (107), the cache controller 1 (1
04) sends a write request signal for the data of the address to the main memory controller (11) via the signal group (127).
0). The main memory controller (110)
The write access to the main memory (111) is started by the information (write request signal, address signal, data signal, other signal) sent via the signal group (127).
Meanwhile, at the same time, the cache controller 2 (10
5)-The cache controller n (106) uses the information of the signal group (127) to make the cache 2 (108)-
Start snooping on cache n (109).

At this time, the main memory controller (11
Operation 0) will be described. Main memory controller (11
In (0), first, the contents of the main memory (111) and the contents of the state storage means (112) are read by the main memory access control circuit (201) from the address to which the processor 1 (101) is to access. Next, the determination circuit (202) performs the following operations according to the value read from the state storage means (112). (A) In the case of "00": data written via the signal group (127) is written into the main memory (111), and at the same time, the snoop interruption signal (130) is enabled to suspend the snoop of the other cache. . The state storage means (1
The contents of 12) are not changed. (B) In the case of “01”: data transmitted via the signal group (127) is written to the main memory (111), but the snoop interruption signal (130) is invalidated and snooping of another cache is continued. . The cache having the data at the address invalidates the data at the address in the cache in order to maintain consistency with the main memory (111). Further, the contents of the state storage means (112) are updated to "00". (C) In the case of "10": Snoop interruption signal (130)
Is invalidated, and snooping of another cache is continued.
The cache having the latest data at the address writes the data transmitted via the signal group (127) to the cache. Also, the contents of the state storage means (112) are not changed.

In the cache controller 2 (105) and the cache controller n (106), the main memory controller (11) is operated by the interrupt circuit block (303).
0) is received, and if the snoop interruption signal (130) is valid, the information is transmitted to the snoop control block (302) to interrupt the snoop, and the snoop interruption signal (130) is transmitted. Is invalid, continue snooping, if the same data in the main memory is in the cache, invalidate the data in the cache, and if data in the cache is newer than the main memory, 1 to signal group (12
7) Write the data transmitted via the cache to the cache.

According to the first embodiment described above, unnecessary cache snooping in a multiprocessor system can be reduced, and the time required for cache snooping is longer than the time required for main memory access. In the case of a long system, the main memory access is not limited by cache snooping, so that the system performance can be improved.

(Second Embodiment) A second embodiment of the present invention refers to a state storage means indicating the state of caching,
When it is determined that snooping is unnecessary, the data of the entire block is output to the cache controller, and when it is determined that snooping is required, the transfer is switched to transfer of only a specific line. FIG. 6 is a diagram showing the overall system configuration of the second embodiment of the present invention. In the figure, reference numerals 401 to 403 denote processors 1 to n constituting a multiprocessor system, and 407 to 409 denote write-back caches 1 to n connected to the processors 1 to n, respectively, and 404 to 406 denote caches 1
Cache controllers 1 to n that perform the control of. 411 is a main memory, and 412 is a state storage means. Reference numeral 410 denotes a main memory controller that controls the main memory (411) via the signal group (427) and controls the state storage means (412) via the signal group (429).

The cache controller 1 (404) sends the signal to the processor 1 (401) via the signal group (421) and the cache 1 (407) via the signal group (424).
It is connected to the. Similarly, cache controller 2
(405) is the processor 2 via the signal group (422).
(402) and to the cache 2 (408) via the signal group (425),
(406) is a processor n via a signal group (423).
(403) and to the cache n (409) via the signal group (426). The cache controllers 1 (404) to n (406) and the main memory controller (410) are interconnected via a signal group (427), and data transfer and snoop control are performed via the signal group (427). Done. A signal (430) is sent from the main memory controller (410) to each of the cache controllers 1 (404) to n (406).
This is a bit line transfer signal. When this signal indicates invalid, block transfer is performed, and when valid, line transfer is performed.

FIG. 7 shows the main memory controller (410).
FIG. 3 is a diagram showing an internal configuration of the device. As shown in the figure, the main memory controller (410) includes a main memory access control block (501) and a determination circuit block (50).
2) and a line transfer control circuit block (503). The main memory access control block (501) includes a main memory access control circuit (504) that controls writing and reading to and from the main memory (411) and a state storage means control circuit (505) that controls writing and reading to and from the state storage means (412). The determination circuit block (502) includes a main memory access control block (501).
The line transfer control circuit block (503) determines whether or not line transfer is possible based on the contents of the state storage means read by the state storage means control circuit (505) and reports it to the line transfer control circuit block (503). ) Is a control block for generating and transmitting the line transfer signal (430).

FIG. 8 shows the cache controller 1 (40
It is a figure which shows the internal structure of 4). As shown in the figure, the cache controller 1 (404) includes a cache access control block (601) and a snoop control block (602). The line transfer signal (430) sent from the line transfer control circuit block (503) of the main memory controller (410) is input to the cache access control block (601) of the cache controller (404) and controls data transfer to the cache. Used for The cache controller 2
(405) to n (406) are also the cache controller 1
The configuration is the same as (404). The correspondence between the main memory (411) and the state storage means (412) and the contents of the state storage means (412) are the same as those in FIGS.

Next, the read access and write access operations of the second embodiment will be described in detail. <Read Access> When the processor 1 (401) requests a read access, the cache controller 1 (4
04) first checks with an address array (not shown) whether data corresponding to the address is stored in the cache 1 (407). (A) In the case of a cache 1 (407) hit: If the data at the address is stored in the cache 1 (407), the cache controller 1 (404) reads the data from the cache 1 (407) and (401) to complete the read access.

(B) In the case of cache 1 (407) mishit: On the other hand, if the data at the address is cache 1 (4
07), the cache controller 1 (404) transmits the read request signal, address signal, and other signals of the block including the address to a signal group (42).
7) to the main memory controller (410). The main memory controller (410) receives the signal group (4
27) (the read request signal), the main memory (4
11) Access is started. On the other hand, at the same time, the cache controllers 2 (405) to n (406) respectively execute the caches 2 (408) to n (n) based on the information of the signal group (427).
The snoop of (409) is started.

In the main memory controller (410), the main memory (411) and the state storage means (412) use the main memory access control block (501) for the address to be accessed by the processor 1 (401). Then, the following operations are performed by the determination circuit block (502) according to the 2-bit value read from the state storage means (412). (A) In the case of “00”: data of a block read from the main memory (411) is transmitted via a signal group (427).
It is sent to the cache controller 1 (404). Further, the contents of the state storage means (412) are updated to "01". At this time, the line transfer signal (430) is set in an invalid state. (B) In the case of "01": The block read from the main memory (411) is transmitted to the cache controller 1 (404) via the signal group (427). The contents of the state storage means (412) are not changed. At this time, the line transfer signal (430) is set in an invalid state. (C) In the case of "10": The block read from the main memory (411) is transmitted to the cache controller 1 (404) via the signal group (427). At this time, the content of the state storage means (412) is updated to "01". At this time, the line transfer signal (430) is kept valid. In this case, when the latest data exists in another cache, the data is transferred according to the snoop protocol.

The cache controller 1 (404)
It receives data sent from the main memory controller (410) and sends the data to the processor 1 (401). At this time, if the line transfer signal (430) is in an invalid state, the data for the block is updated in the cache 1 (407), and the line transfer signal (43) is updated.
If (0) is in the valid state, the cache 1 (407) updates the data only for the line.

<Write Access> Next, the operation in the write access from the processor will be described in detail. When the processor 1 (401) requests a write access,
First, the cache controller 1 (404) checks whether the data corresponding to the address is stored in the cache 1 (407) (cache hit) or not (cache miss). (A) In the case of a cache 1 (407) hit If the data of the address is stored in the cache 1 (407), the cache controller 1 (404)
The write data is stored in the cache 1 (407) and the access is completed (in the case of a write-back cache).

(B) In the case of a cache 1 (407) mishit On the other hand, if the data at the address is not stored in the cache 1 (407), the cache controller 1 (4
04) sends a write request signal, an address signal, and a data signal of the data of the address to the main memory controller (410) via the signal group (427). The main memory controller (410) starts a write access to the main memory (411) according to the information (write request signal) sent via the signal group (427). On the other hand, at the same time, the cache controller 2 (405) to the cache controller n (406) transmit the signal group (427)
From the cache 2 (408) to the cache n
The snoop of (409) is started.

At this time, the main memory controller (41)
Operation 0) will be described. Main memory controller (41
0), first, the main memory access control block (50
According to 1), the contents of the main memory (411) and the contents of the state storage means (412) are read from the address to which the processor 1 (401) is going to access. The following operations are performed according to the value read from the storage unit (412). (A) For “00”: Write the data transmitted via the signal group (427) to the main memory (411). The contents of the state storage means (412) are not changed. (B) In the case of “01”: Write the data transmitted via the signal group (427) to the main memory (411). The cache having the data of the address is stored in the main memory (41
In order to maintain consistency with 1), the data at the address in the cache is invalidated. Also, a state storage means (412)
Is updated to “00”. (C) In the case of "10": A cache having the latest data at the address is found by snooping, and a signal group (4
27) writes the data transmitted via it to its cache. At this time, the contents of the state storage means (412) are not changed.

In the case of write access,
The line transfer signal (430) is in an invalid state. The cache controller 2 (405) to the cache controller n (406) perform snooping. If the same data as in the main memory is in the cache, the data is invalidated, and the latest data newer than the main memory is stored in the cache. In some cases, the data sent from the processor 1 via the signal group (427) is written to the cache. In the second embodiment, unnecessary cache snoops in the multiprocessor system can be reduced, as in the first embodiment, so that the system performance can be improved.

(Third Embodiment) Next, a third embodiment capable of further reducing snoops will be described. The first
In the second embodiment, the blocks stored in the state storage means include blocks corresponding to the address accessed by the processor. Whether it is held in at least one cache, and b. If it is held, it is information indicating what state (whether or not it matches the main memory) is held, but in the third embodiment, the block at the address is a. Which cache it is in, and b. This is information indicating what state is stored in the cache (whether the latest data newer than the main memory is stored).

In this case, it is apparent that a normal directory may be used as the state storage means without any special provision for judging the necessity of snooping. In this way, a bit more (for example, the number of processors) is required to indicate which cache exists in the cache, but if the block at the corresponding address has the latest data, the data of that line is retained. Unnecessary snoops can be further reduced by examining the cache that is in use, continuing snooping only on that cache, and interrupting snoops on other caches.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described in detail. A fourth embodiment of the present invention provides a cache information signal between a cache and a directory,
The cache information signal always matches the cache state with the directory state. FIG. 9 shows a block diagram of a fourth embodiment of the present invention. In the figure, 700 and 800 are CPUa and CPUb, 701
And 801 are instruction control units in each CPU, and 702 and 80
2 is a 2-way set associative cache in each CPU, 703 and 803 are cache buses in each CPU, 900 is a CPU bus, 1000 is a cache information signal which is a feature of the present invention, 1100 is a directory, 1200 is a main memory, Reference numeral 1300 denotes a main memory control signal, 1400 denotes an IO bus, and 1500 denotes an IO.

In this embodiment, the cache information signal 1000 is 1 bit for indicating whether or not to perform caching.
1 bit to indicate which operation of CPUa or CPUb, 1 bit to indicate operation of the first way or the second way, and 1 bit to indicate that the cache state is invalid, clean, or dirty It is composed of a total of 5 bits of 2 bits. In the following example, caching is performed when the 0th bit is “0”. "1" indicates that no caching is performed. First bit: “0” indicates cache / directory access on the CPUa side. "1" indicates cache / directory access on the CPUb side. Second bit: “0” indicates access to the first way. "1" indicates access to the second way. Third and fourth bits: "00" indicates that the next state of the cache is clean. "01" indicates that the next state of the cache becomes dirty.
"10" indicates that the next state of the cache is invalid. "11" indicates that cache data (block) of the cache is written back to the main memory.
For example, if the cache information is “00000”,
This indicates that the state of the first way of the cache / directory on the CPUa side is to be cleaned.

FIG. 10 shows a configuration diagram of the cache and the directory in this embodiment. As shown in FIG. 10A, it is assumed that each of the CPUa and the CPUb has a 2-way set associative cache with a depth X entry and a write allocate cache. In this case, as shown in FIG. 10B, the directory of the 2-way set associative of the depth X entry is set to the CPU.
It has two sets, a side and CPUb side.

Next, the operation of each circuit block shown in FIG. 9 will be described. FIG. 11 is a flowchart of the directory change. Hereinafter, the operation of each circuit block when the directory is changed will be described with reference to FIG. (1) When hit at the time of CPU read request: CPUa
Instruction control unit 701 issues a main memory read to the cache bus 703 (step S1; read), and the cache 7
02 is a hit (step S2;
Hit), and the cache 702 returns the requested data to the instruction control unit 701. In this case, CPUa does not generate a command on CPU bus 900 and cache information signal 1000. Therefore, the directory 1100 is not changed (step S6).

(2) In the case of a mishit at the time of a CPU read request: the instruction control unit 701 of the CPU
03 is issued (step S1; read), and if the hit determination result of the cache 702 is a mishit (step S2; mishit), the cache 70 is read.
2 issues a main memory read to the CPU bus 900, takes the block of the main memory 1200 into the cache 702, and returns the requested data to the instruction control unit 701.
At this time, the cache 702 stores the cache information signal 100
0 is reported that either the first way or the second way of the cache 702 is in a clean state (step S3). In this case, the CPUa sets the cache information signal 1000 to “00000” (when the first way of the cache on the CPUa side is in a clean state) or “00”.
100 "(when the second way of the cache on the CPUa side is in a clean state).
(The main memory read request). The directory 1100 stores the cache information signal 1000
And the first or second way of the corresponding entry
The way tag information is updated to clear the status (step S3).

(3) If the cache is dirty due to a hit at the time of CPU write request: instruction control unit 701 of CPUa
Issues a main memory write to the cache bus 703 (step S1; write), and when the hit determination result of the cache 702 is hit (step S4; hit) and the cache state is dirty (step S5; dirty), the cache 702 Cache write data 702
Write to In this case, the CPUa is the CPU bus 900
And no command is issued to the cache information signal 1000. Therefore, no change occurs in the directory 1100 (step S7).

(4) When the cache is clean due to a hit at the time of a CPU write request: the instruction control unit 701 of the CPUa
Issues a main memory write to the cache bus 703 (step S1; write), and if the hit determination result of the cache 702 is hit (step S4; hit) and the cache state is clean (step S5; clean), the cache 702 Main memory write data cache 702
To invalidate the cache 802 of the CPU b, and issues an invalidation request to the CPU bus 900. At this time, the cache 702 simultaneously outputs the cache information signal 10
00, it is reported that either the first way or the second way of the cache 702 is in a dirty state (step S7). In this case, the CPUa sets the cache information signal 1000 to “00001” (when the first way of the cache on the CPUa side is in a dirty state) or “0”.
0101 "(when the second way of the cache on the CPUa side is in a dirty state).
It is issued at the same time as the 0 command (invalidation request). The directory 1100 receives the cache information signal 1000 and makes the status of the first way or the second way of the corresponding entry dirty (step S7).

(5) In the case of a mishit at the time of a CPU write request: the instruction control unit 701 of the CPU
03 is issued (step S1; write), and if the hit determination result of the cache 702 is a mishit (step S4; mishit), the cache 70
2 issues a main memory read to the CPU bus 900, fetches a block of the main memory 1200 into the cache 702,
The data of the instruction control unit 701 is written to the cache 702. The cache 702 transfers the main memory read to the CPU bus 9
When issued to 00, the cache 702 simultaneously reports to the cache information signal 1000 that either the first way or the second way of the cache 702 is in a dirty state (step S7). In this case, the CPUa adds “00001” (CPUa
When the first way of the cache on the side is in a dirty state, or "00101" (when the second way of the cache on the CPUa side is in a dirty state), the command of the CPU bus 900 (main memory read request) Issued at the same time. The directory 1100 receives the cache information signal 1000 and receives the first entry of the corresponding entry.
The tag information of the way or the second way is updated to make the status dirty (step S7).

As described above, in this embodiment, the cache 702 and the directory 1100 can always be kept in the same state by using the cache information. Similarly, the state of the cache 802 of the CPUb and the state of the directory 1100 can always be kept the same.

FIG. 12 is a flow chart of the directory operation at the time of DMA. Hereinafter, the operation of each block in FIG. 1 at the time of a DMA request will be described with reference to FIG. (1) In case of mishit in DMA read: IO1500
Issues a DMA read to the IO bus 1400, and when the hit determination result of the directory 1100 is a mishit (step S11; mishit), the directory 1100 instructs the main memory 1200 to output data to the IO 1500. In this case, the cache 702 and the cache 802
No snoops needed. Here, no command is issued to CPU bus 900 and cache information signal 1000.

(2) In case of DMA read and dirty due to hit on CPUa side: IO 1500 is connected to IO bus 1400 by D
An MA read is issued, and the hit determination result of the directory 1100 is a CPUa side hit (step S11; CPUa
If the state of the directory on the CPUa side is dirty (Step S12; Dirty) at the side hit, the directory 1
100 issues a write-back (write-back) request of the cache 702 to the main memory 1200 to the CPU bus 900 (step S13), and at the same time, the cache 7
02 is reported to be either the first way or the second way. In this case, the directory 1100 stores “00011” (when the block in the first way of the cache on the CPUa side is written back to the main memory) or “00111” (block in the second way of the cache on the CPUa side) in the cache information signal 1000. Command (when writing back to the memory) is issued at the same time as the command (write-back request) of the CPU bus 900. The cache 702 receives the cache information signal 1000, writes the data of the first way or the second way of the cache back to the main memory, and then invalidates the entry. The main memory 1200 returns the block written back from the cache 702 to the IO 1500. At this time, the CPUa side directory is changed to invalid (step S14).

(3) In case of DMA read and dirty due to hit on CPUb side: IO 1500 is connected to IO bus 1400 by D
An MA read is issued, and the hit determination result of the directory 1100 is a CPUb side hit (step S11; CPUb
If the state of the directory on the CPUb side is dirty (Step S17; Dirty) in directory hit, the directory 1
100 issues a write-back (write-back) request of the cache 802 to the main memory 1200 to the CPU bus 900 (step S18), and at the same time, the block to be written back is
02 is reported to be either the first way or the second way. In this case, the directory 1100 sets the cache information signal 1000 to “01011” (when writing the first way block of the CPUb side cache back to the main memory) or “01111” (when writing the second way block of the CPUb side cache to the main memory). Command (when writing back to the memory) is issued at the same time as the command (write-back request) of the CPU bus 900. The cache 802 receives the cache information signal 1000, writes the data of the first way or the second way of the cache back to the main memory, and then makes the entry invalid. The main memory 1200 returns the data written back from the cache 802 to the IO 1500. At this time, the directory on the CPUb side is changed to invalid (step S19).

(4) In the case of a DMA read and the CPUa side hit and clean: IO 1500 is connected to IO bus 1400 by D
An MA read is issued, and the hit determination result of the directory 1100 is a CPUa side hit (step S11; CPUa
If the state of the directory on the CPUa side is clean (step S12; clean) at the side hit, the directory 1
100 instructs the main memory 1200 to output data to the IO 1500. In this case, there is no need to snoop the cache 702 and the cache 802. Here, no command is issued to CPU bus 900 and cache information signal 1000.

(5) In the case of the DMA read and the CPUb side hit and clean: IO 1500 is connected to IO bus 1400 by D
An MA read is issued, and the hit determination result of the directory 1100 is a CPUb side hit (step S11; CPUb
If the state of the directory on the CPUb side is clean (step S17; clean) at the side hit, the directory 1
100 instructs the main memory 1200 to output data to the IO 1500. In this case, there is no need to snoop the cache 702 and the cache 802. Here, no command is issued to CPU bus 900 and cache information signal 1000.

(6) In case of mishit in DMA write:
If the IO 1500 issues a DMA write to the IO bus 1400 and the hit determination result of the directory 1100 is a mishit (step S11: mishit), the directory 1100 instructs the main memory 1200 to write data from the IO 1500. In this case, the cache 70
No snooping of 2 and cache 802 is required. Here, the CPU bus 900 and the cache information signal 100
No command is issued for 0.

(7) In case of DMA write and dirty due to CPUa hit: IO 1500 is connected to IO bus 1400 by D
MA write is issued, and the hit determination result of the directory 1100 is a CPUa side hit (step S11; CPUa
If the state of the directory on the CPUa side is dirty (Step S12; Dirty) at the side hit, the directory 1
100 issues a request to write back the main memory 1200 of the cache 702 to the CPU bus 900 (step S13), and at the same time, the block to be written back is written in the first way or the second way of the cache 702 by the cache information signal 1000. Report either. In this case, the directory 1100 stores the cache information signal 1
000 to “00011” (when rewriting the block of the first way of the cache on the CPUa side to the main memory) or “00111” (when rewriting the block of the second way of the cache on the CPUa side to the main memory). C
It is issued at the same time as the PU bus 300 command (write-back request). The cache 702 stores the cache information signal 1
000 is received and the data of the first way or the second way of the cache is written back to the main memory, and then the entry is invalidated. The directory 1100 stores the write-back block of the cache 702 in the main memory 1200.
Then, the data from the IO 1500 is written to the main memory 1200. At this time, the CPUa side directory is changed to invalid (step S14).

(8) In case of DMA write and dirty due to hit of CPUb side: IO 1500 is connected to IO bus 1400 by D
MA write is issued, and the hit determination result of the directory 1100 is a CPUb side hit (step S11; CPUb
If the state of the directory on the CPUb side is dirty (Step S17; Dirty) in directory hit, the directory 1
100 issues a write-back request to the main memory 1200 of the cache 802 to the CPU bus 900 (step S18), and at the same time, the cache information signal 1000 causes the block to be written back to the first way or the second way of the cache 802. Report either. In this case, the directory 1100 stores the cache information signal 1
The command of “01011” (when rewriting the block of the first way of the cache on the CPUb side to the main memory) or “01111” (when rewriting the block of the second way of the cache on the CPUb side to the main memory) is stored in 000. C
It is issued at the same time as the PU bus 900 command (write-back request). The cache 802 receives the cache information signal 1
000 is received and the data of the first way or the second way of the cache is written back to the main memory, and then the entry is invalidated. The directory 1100 stores the write-back block of the cache 802 in the main memory 1200.
Then, the data from the IO 1500 is written to the main memory 1200. At this time, the directory on the CPUb side is changed to invalid (step S19).

(9) In the case where the CPUa side hits the DMA write and is clean: IO 1500 is connected to IO bus 1400 by D
MA write is issued, and the hit determination result of the directory 1100 is a CPUa side hit (step S11; CPUa
If the state of the directory on the CPUa side is clean (step S12; clean) at the side hit, the directory 1
100 issues a request to invalidate the cache 702 to the CPU bus 900,
000 reports that the data to be invalidated is either the first way or the second way of the cache 702. In this case, the directory 1100 indicates “00010” in the cache information signal 1000 (when the first way of the cache on the CPUa side becomes invalid).
Or "00110" (the second cache of the CPUa side)
Command (when the way enters the invalid state) is issued at the same time as the command (invalidation request) on the CPU bus 900. The cache 702 stores the cache information signal 1
000 is received and the first way or the second way of the cache is invalidated (step S16).
The directory 1100 writes data from the IO 1500 to the main memory 1200. At this time, the CPUa side directory is changed to invalid (step 14).

(10) When the CPU write hits the CPUb side and the DMA is clean: The IO 1500 issues a DMA write to the IO bus 1400, and the hit determination result of the directory 1100 indicates that the CPU b hits (step S11; CPU
If the state of the directory on the CPUb side is clean (step S17; clean) in the (b-side hit), the directory 1100 is stored in the cache 802 on the CPU bus 900.
At the same time that the invalidation request is issued, the data to be invalidated
Is reported to be either the first way or the second way. In this case, the directory 1100 changes the cache information signal 1000 to “01010” (when the first way of the CPUb side cache is invalid) or “01110” (when the second way of the CPUb side cache is invalid). ) Is issued at the same time as the command (invalidation request) on the CPU bus 900. The cache 802 receives the cache information signal 1000 and invalidates the first way or the second way of the cache (step S2).
1). The main memory 1200 writes data from the IO 1500. At this time, the directory on the CPUb side is changed to invalid (step S19).

With the above operation, the directory capacity can be the total of the cache capacity. In addition, cache snooping in the case of a directory mishit in the DMA is not necessary, and the cache also specifies the cache and way in which invalidation or write-back occurs during the cache snooping in the DMA. In the fourth embodiment, a two-way cache has been described. However, it is apparent that the number of ways can be expanded by simply changing the bit of the cache information regardless of the number of ways in the cache. Further, in the above embodiment, the case where the cache is provided in the CPU has been described. However, the present invention is applicable to the case where the cache is located inside the CPU and the case where the cache is located outside the CPU regardless of the physical position of the cache. Is also applicable. Further, in the above-described embodiment, the cache of the write-back system has been described, but the present invention is applicable to a write-through system and a write-back system regardless of the cache system.

[0062]

According to the present invention, in a multiprocessor system having a cache, unnecessary snooping of a cache can be reduced by using both a snoop method and a directory method. In a system in which the time required for the snoop of the cache is longer than the required time, the main memory access is not limited by the cache snoop, so that the system performance can be improved. The present invention does not depend on the hierarchical structure of the cache in the system, and is effective even if each processor has a cache having a different hierarchical structure. Also, it does not depend on the protocol for guaranteeing the consistency of each cache. Further, the present invention provides
It is effective whether each cache is a write-through system or a write-back system, and both cache systems are mixed in the system and in the hierarchy. Further, in the present invention, the state storage means may be constituted by a DRAM or an SRAM. That is, the present invention does not depend on the constituent elements of the state storage means.

Further, according to the present invention, in a system in which cache coherency is guaranteed by a directory method, a cache information signal is provided between a cache and a directory so that the directory state and the cache state always coincide with each other, thereby reducing the main memory capacity. There is no need to have a directory for everything, and a directory with the total cache capacity is sufficient. In addition, cache snooping at the time of directory mishit in DMA becomes unnecessary,
Even during a DMA cache snoop, the directory indicates the cache and way in which invalidation or write-back occurs, so that it is not necessary to determine the cache hit.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram for implementing a first embodiment of the present invention.

FIG. 2 is a diagram showing main blocks of a main memory controller for implementing the first embodiment of the present invention.

FIG. 3 is a diagram showing main blocks of a cache controller for implementing the first embodiment of the present invention.

FIG. 4 is a diagram showing a main memory space and a corresponding state storage means.

FIG. 5 is a diagram showing contents of an embodiment of a state storage means.

FIG. 6 is an overall configuration diagram for implementing a second embodiment of the present invention.

FIG. 7 is a diagram showing main blocks of a main memory controller for implementing a second embodiment of the present invention.

FIG. 8 is a diagram showing main blocks of a cache controller for implementing a second embodiment of the present invention.

FIG. 9 is a block diagram of a fourth embodiment of the present invention.

FIG. 10 is a configuration diagram of a cache and a directory according to a fourth embodiment of the present invention.

FIG. 11 is a flowchart for changing a directory according to a fourth embodiment of the present invention.

FIG. 12 is an operation flow of a directory at the time of DMA according to the fourth embodiment of the present invention.

[Explanation of symbols]

101, 401 ... Processor 1, 102, 402 ... Processor 2, 103, 403 ... Processor n, 104, 4
04: Cache controller 1, 105, 405: Cache controller 2, 106, 406: Cache controller n, 107, 407: Cache 1, 10
8, 408: Cache 2, 109, 409: Cache n, 110, 410: Main memory controller, 11
1,411: Main memory, 112, 412: State storage means, 130: Snoop interruption signal, 201, 501: Main memory access control block, 202, 502: Judgment circuit block, 203: Interruption signal control circuit block, 204,
504: Main memory access control circuit, 205, 505: State storage means control circuit, 301, 601: Cache access control block, 302, 602: Snoop control block, 303: Interruption circuit block, 430: Line transfer signal, 503: Line Transfer control circuit block, 700,
800: CPU, 701, 801: CPU instruction control unit,
702, 802: cache, 703, 803: cache bus, 900: CPU bus, 1000: cache information signal, 1100: directory, 1200: main memory, 1300: main memory control signal, 1400: IO bus,
1500 ... IO

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahide Tsuboi 1 Ikegami, Haruoka-cho, Owariasahi-shi, Aichi Prefecture Inside the Office Systems Division of Hitachi, Ltd. (72) Inventor Koichi Okazawa 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Incorporated Hitachi Systems Development Laboratory (72) Inventor Masaya Umemura 1099, Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture (72) Inventor Tomonori Naito 1st Ikegami, Haruoka-cho, Owariasahi-city, Aichi Prefecture Inside Hitachi Asahi Electronics Co., Ltd. (72) Tetsuo Hiramitsu 1st Ikegami, Haruoka-machi, Owariasahi-shi, Aichi Japan Inc. Hitachi Asahi Electronics (72) Who Masumi Terao Nagoya, Aichi Prefecture, Naka-ku Sakae Third Street No. 10 No. 22 Date start-Central software within Co., Ltd.

Claims (6)

[Claims] A plurality of processors; a main memory shared by the plurality of processors; a main memory controller for controlling the main memory; and a main memory controller located between each of the plurality of processors and the main memory. A cache memory control device in a multiprocessor system having a plurality of cache memories for holding a copy of the contents of the main memory and a cache controller for controlling each of the plurality of cache memories; State storage means for storing a state, a determination circuit for searching the state storage means in response to an address accessed from the processor, and determining whether or not snooping of another cache is necessary for the address; If it is determined by the circuit that snooping is unnecessary, the cache A snoop interruption signal for notifying a snoop interruption outputted to a controller, and an interruption circuit for interrupting the snoop when each of the cache controllers receives the snoop interruption signal. Memory controller. 2. A plurality of processors, a main memory shared by the plurality of processors, a main memory controller controlling the main memory, and a main memory controller located between each of the plurality of processors and the main memory. A plurality of cache memories for holding a copy of the contents of the main memory, and a cache controller for controlling each of the plurality of cache memories, and a transfer unit (block) from the main memory to the cache memory is: In a cache memory control device in a multiprocessor system that is a plurality of transfer units (lines) from the cache memory to the processor, a snoop that snoops only a specific line in the block when the cache controller requests a block replacement. A circuit and data on the main memory A state storage means for storing the state, searches the state storage means corresponding to the access address from the processor,
A determination circuit for determining a state of data corresponding to the block including the address; and a determination unit that determines that the snoop is unnecessary for the data corresponding to the block including the address as a result of the determination by the determination circuit. Data to the cache controller, and when it is determined that snooping is necessary, switching to transfer of only a specific line is provided, and means for notifying the cache controller of the information of the specific line is provided. Cache memory control device. 3. The cache control device according to claim 1, wherein the state storage means determines which data in the main memory is stored in at least one cache memory, and further stores the data. A cache memory control device, which stores the state in which the data is held. 4. The cache memory control device according to claim 1, wherein said state storage means determines which data in said main memory is stored in said cache memory, and which data is stored in said cache memory. What is stored in a cache memory is a cache memory control device. 5. A cache memory control device in a multiprocessor system in which cache coherency is guaranteed by a directory method, a cache information signal transmitted / received between a cache and a directory is provided, and a cache state and a directory state are used by using the cache information signal. A cache memory control device, wherein 6. The cache memory control device according to claim 5, wherein when the cache state changes, the cache reports a change in the cache state to the directory by using a cache information signal, and when a DMA occurs, the directory changes. Wherein the invalidation of the cache data and the writing back of the cache data to the main memory are reported to the cache by a cache information signal.