JPH1055672A5 - - Google Patents

Description

[Title of Invention] Semiconductor memory device [Claims]
1. A semiconductor memory device having a pair of first and second bit lines connected to a plurality of memory cells,
a bit line precharge circuit that precharges the first bit line and the second bit line to a first voltage between a high potential voltage and a low potential voltage;
a sense amplifier for amplifying and outputting a potential difference between the first bit line and the second bit line;
The sense amplifier
a first field effect transistor of one conductivity type, having a first current input/output electrode connected to a first node and a second current input/output electrode connected to the first bit line;
a second field effect transistor of one conductivity type, having a first current input/output electrode connected to the first node and a second current input/output electrode connected to the second bit line;
a third field effect transistor of the other conductivity type, the first current input/output electrode of which is connected to the second node;
a fourth field effect transistor of the other conductivity type, the first current input/output electrode of which is connected to the second node;
a first switch element connected between the first node and the gate of the first field effect transistor;
a second switch element connected between the first node and the gate of the second field effect transistor;
2. After precharging the first bit line and the second bit line,
2. The semiconductor memory device according to claim 1, wherein the first switch element and the second switch element are made conductive to diode-connect the first field-effect transistor and the second field-effect transistor, and a second voltage is applied to the first node .
3. The second voltage:
The difference between the voltage of the first bit line and the voltage of the second bit line is set to be substantially the same as the difference between the threshold voltage of the first field effect transistor and the threshold voltage of the second field effect transistor.
3. The semiconductor memory device according to claim 2, wherein :
Claim 4: During amplification operation,
The first switch element and the second switch element are non-conductive,
the first field effect transistor and the third field effect transistor have second current input/output electrodes connected to the first bit line and gates connected to the second bit line;
The second field effect transistor and the fourth field effect transistor have second current input/output electrodes connected to the second bit line and gates connected to the first bit line.
4. The semiconductor memory device according to claim 1, 2 or 3 , wherein:
5. After a first sense amplifier drive voltage is applied to the first node and the first field effect transistor and the second field effect transistor are activated,
a second sense amplifier drive voltage is applied to the second node to activate the third field effect transistor and the fourth field effect transistor;
5. The semiconductor memory device according to claim 1, 2, 3 or 4 , wherein:
6. A third switch element connected between the gates of the first field effect transistor and the third field effect transistor;
a fourth switch element connected between the gates of the second field effect transistor and the fourth field effect transistor;
the third field effect transistor has a second current input/output electrode connected to the first bit line and a gate connected to the second bit line;
The fourth field effect transistor has a second current input/output electrode connected to the second bit line and a gate connected to the first bit line.
6. The semiconductor memory device according to claim 1, 2, 3, 4 or 5, characterized in that :
7. A third switch element connected between the gates of the first field effect transistor and the third field effect transistor;
a fourth switch element connected between the gates of the second field effect transistor and the fourth field effect transistor;
a fifth switch element connected between the first bit line and the gate of the fourth field effect transistor;
a sixth switch element connected between the second bit line and the gate of the third field effect transistor;
a seventh switch element connected between a second current input/output electrode of the third field effect transistor and a gate of the third field effect transistor;
an eighth switch element connected between a second current input/output electrode of the fourth field effect transistor and a gate of the fourth field effect transistor;
a second current input/output electrode of the third field effect transistor is connected to the first bit line;
connecting a second current input/output electrode of the fourth field effect transistor to the second bit line;
6. The semiconductor memory device according to claim 1, 2, 3, 4 or 5, characterized in that :
8. A third switch element and a fourth switch element connected in series between the gates of the first field effect transistor and the third field effect transistor;
a fifth switch element and a sixth switch element connected in series between the gates of the second field effect transistor and the fourth field effect transistor;
a seventh switch element connected between a second current input/output electrode of the third field effect transistor and a gate of the third field effect transistor;
an eighth switch element connected between a second current input/output electrode of the fourth field effect transistor and a gate of the fourth field effect transistor;
a second current input/output electrode of the third field effect transistor is connected to the first bit line;
a second current input/output electrode of the fourth field effect transistor is connected to the second bit line;
a connection point between the third switch element and the fourth switch element is connected to the second bit line;
connecting a connection point between the fifth switch element and the sixth switch element to the first bit line;
6. The semiconductor memory device according to claim 1, 2, 3, 4 or 5, characterized in that :
9. A third switch element connected between second current input/output electrodes of said first field effect transistor and said third field effect transistor; and
a fourth switch element connected between second current input/output electrodes of the second field effect transistor and the fourth field effect transistor;
a fifth switch element connected between the first bit line and the gate of the fourth field effect transistor;
a sixth switch element connected between the second bit line and the gate of the third field effect transistor;
connecting a gate of the first field effect transistor to a gate of the third field effect transistor;
connecting the gate of the second field effect transistor to the gate of the fourth field effect transistor;
6. The semiconductor memory device according to claim 1, 2, 3, 4 or 5, characterized in that :
10. A third switch element connected between second current input/output electrodes of said first field effect transistor and said third field effect transistor; and
a fourth switch element connected between second current input/output electrodes of the second field effect transistor and the fourth field effect transistor;
a gate of the first field effect transistor is connected to a gate of the third field effect transistor and to a second current input/output electrode of the fourth field effect transistor;
connecting a gate of the second field effect transistor to a gate of the fourth field effect transistor and to a second current input/output electrode of the third field effect transistor;
6. The semiconductor memory device according to claim 1, 2, 3, 4 or 5, characterized in that :
Detailed Description of the Invention
[0001]
[Technical Field to which the Invention Belongs]
The present invention relates to a semiconductor memory device that employs a bit line precharge method, which includes a pair of bit lines connected to a plurality of memory cells and a sense amplifier consisting of a flip-flop circuit that amplifies the differential voltage between the pair of bit lines generated by a selected memory cell when reading data, and precharges the bit lines to a voltage between the maximum and minimum voltages during amplification.
[0002]
Here, the threshold voltage Vth of a MOS transistor depends on the gate length, and the shorter the gate length, the greater the degree of reduction due to the short channel effect. Therefore, the imbalance (difference) ΔVth in the threshold voltage Vth due to processing variations between paired MOS transistors that make up a sense amplifier consisting of a flip-flop circuit becomes larger as the gate length becomes shorter.
[0003]
This imbalance ΔVth in the threshold voltage Vth becomes the offset voltage of the sense amplifier, so if, with miniaturization, the differential voltage between the bit lines that occurs when reading data becomes equal to or less than this imbalance ΔVth, the sense amplifier will malfunction. Therefore, a countermeasure is required.
[0004]
2. Description of the Related Art
FIG. 20 is a circuit diagram showing the essential parts of an example of a conventional dynamic random access memory (hereinafter referred to as DRAM) that is designed to prevent malfunction of a sense amplifier due to an imbalance ΔVth in the threshold voltages Vth of a pair of MOS transistors that constitute a sense amplifier made up of a flip-flop circuit.
[0005]
In Figure 20, WL-A is a word line for selecting a memory cell, BL-A and /BL-A are bit lines each forming a pair to which multiple memory cells are connected, 1 indicates one of the memory cells connected to the bit line BL-A, 2 is a cell capacitor, and 3 is a cell transistor.
[0006]
Also, reference numeral 4 denotes a bit line precharge circuit that precharges the bit lines BL-A and /BL-A, reference numerals 5 to 7 denote nMOS transistors whose conduction (hereinafter referred to as ON) or non-conduction (hereinafter referred to as OFF) is controlled by a bit line precharge signal φPR, and VCC denotes the power supply voltage.
[0007]
Also, 8 is a sense amplifier consisting of a flip-flop circuit, 9 and 10 are a pair of nMOS transistors that perform amplification operation, 11 to 13 are nMOS transistors whose ON/OFF is controlled by a control signal φ1, 14 and 15 are nMOS transistors whose ON/OFF is controlled by a control signal φ2, 16 is an nMOS transistor whose ON/OFF is controlled by a control signal φ3, and VE is a voltage lower than VCC.
[0008]
FIG. 21 is a waveform diagram showing the operation of this DRAM during bit line precharge and data read, showing the bit line precharge signal φPR and control signals φ1 to φ3.
[0009]
That is, in this DRAM, when the bit lines are precharged, the bit line precharge signal φPR is set to VP, the control signals φ1 to φ3 are set to 0 V, the nMOS transistors 5 to 7 are set to ON, and the nMOS transistors 11 to 16 are set to OFF, and the bit lines BL-A and /BL-A are precharged to the power supply voltage VCC, where VP≧VCC+Vth (threshold voltage of the nMOS transistors).
[0010]
Thereafter, the bit line precharge signal φPR is set to 0 [V], the control signal φ1 is set to VP, the nMOS transistors 5 to 7 are set to OFF, and the nMOS transistors 11 to 13 are set to ON.
[0011]
As a result, nMOS transistors 9 and 10 are diode-connected, and the voltage at node N1 = the voltage at bit line BL-A = VE + Vth9 (threshold voltage of nMOS transistor 9), and the voltage at node N2 = the voltage at bit line BL-A = VE + Vth10 (threshold voltage of nMOS transistor 10).
[0012]
Thereafter, the control signal φ1 is set to 0 [V], the control signal φ2 is set to VP, the nMOS transistors 11 to 13 are set to OFF, and the nMOS transistors 14 and 15 are set to ON. In this case, the capacitances of the nodes N1 and N2 are sufficiently smaller than the capacitances of the bit lines BL-A and /BL-A, so that the voltage of the node N1 = the voltage of the bit line BL-A = VE + Vth10, and the voltage of the node N2 = the voltage of the bit line /BL-A = VE + Vth9.
[0013]
For example, if Vth9=Vth10+ΔVth, then as shown in FIG. 22, the nMOS transistor 9 having a threshold voltage of Vth9=Vth10+ΔVth has a gate voltage=voltage on bit line/BL-A=VE+Vth10+ΔVth, and the nMOS transistor 10 having a threshold voltage of Vth10 has a gate voltage=voltage on bit line BL-A=VE+Vth10.
[0014]
That is, threshold voltage Vth9 of nMOS transistor 9 - threshold voltage Vth10 of nMOS transistor 10 = gate voltage of nMOS transistor 9 - gate voltage of nMOS transistor 10 = ΔVth, and the imbalance ΔVth between the threshold voltages Vth9, Vth10 of nMOS transistors 9, 10 apparently disappears.
[0015]
Thereafter, when the data of the selected memory cell is read out onto the bit line BL-A or the bit line /BL-A, the control signal φ3 is set to VCC and the nMOS transistor 16 is set to ON, and the nMOS transistors 9 and 10 are activated to perform an amplification operation, thereby amplifying the differential voltage between the bit lines BL-A and /BL-A generated by the selected memory cell.
[0016]
In this manner, in this DRAM, before the nMOS transistors 9 and 10 perform their amplification operation, a charge sufficient to compensate for the offset voltage of the sense amplifier 8 is accumulated in the gates of the nMOS transistors 9 and 10, thereby apparently eliminating the imbalance ΔVth between the threshold voltages Vth9 and Vth10 of the nMOS transistors 9 and 10, thereby preventing malfunction of the sense amplifier 8.
[0017]
FIG. 23 is a circuit diagram showing the essential parts of another example of a conventional DRAM which is adapted to prevent malfunction of a sense amplifier due to an imbalance ΔVth in the threshold voltages Vth of a pair of MOS transistors which constitute a sense amplifier made up of a flip-flop circuit.
[0018]
In Figure 23, WL-B is a word line for selecting a memory cell, BL-B and /BL-B are bit lines each forming a pair to which multiple memory cells are connected, 18 indicates one of the memory cells connected to the bit line BL-B, 19 is a cell capacitor, and 20 is a cell transistor.
[0019]
Reference numeral 21 denotes a bit line precharge circuit that precharges the bit lines BL-B and /BL-B, and reference numerals 22 to 24 denote nMOS transistors whose ON/OFF states are controlled by a bit line precharge signal φPR.
[0020]
Further, 25 is a sense amplifier consisting of a flip-flop circuit, 26 and 27 are a pair of nMOS transistors that perform amplification operations, 28 is an nMOS transistor whose ON/OFF is controlled by a bit line precharge signal φPR, 29 and 30 are nMOS transistors whose ON/OFF is controlled by a control signal φ4, and 31 is an nMOS transistor whose ON/OFF is controlled by a control signal φ5.
[0021]
FIG. 24 is a waveform diagram showing the operation of this DRAM during bit line precharge and data read, showing the bit line precharge signal φPR and control signals φ4 and φ5.
[0022]
That is, in this DRAM, when the bit lines are precharged, the bit line precharge signal φPR is VP, the control signals φ4 and φ5 are 0V, the nMOS transistors 22 to 24 and 26 to 28 are ON, and the nMOS transistors 29 to 31 are OFF.
[0023]
As a result, nodes N3 and N4 are precharged to VCC, the voltage of bit line BL-B is VCC-Vth26 (threshold voltage of nMOS transistor 26), and the voltage of bit line /BL-B is VCC-Vth27 (threshold voltage of nMOS transistor 27).
[0024]
Thereafter, the bit line precharge signal φPR is set to 0 [V], the control signal φ4 is set to VP, the nMOS transistors 22 to 24 and 28 are set to OFF, and the nMOS transistors 29 and 30 are set to ON.
[0025]
In this case, the capacitance of nodes N3 and N4 is sufficiently smaller than the capacitance of bit lines BL-B and /BL-B, so the voltage of node N3 = the voltage of bit line BL-B = VCC - Vth26, and the voltage of node N4 = the voltage of bit line /BL-B = VCC - Vth27.
[0026]
For example, if Vth26=Vth27+ΔVth, then as shown in FIG. 25, the nMOS transistor 26 having a threshold voltage of Vth26=Vth27+ΔVth has a gate voltage=voltage at node N4=VCC-Vth27, and the nMOS transistor 27 having a threshold voltage of Vth27 has a gate voltage=voltage at node N3=VCC-Vth27-ΔVth.
[0027]
That is, threshold voltage Vth26 of nMOS transistor 26-threshold voltage Vth27 of nMOS transistor 27=gate voltage of nMOS transistor 26-gate voltage of nMOS transistor 27=ΔVth, and the imbalance ΔVth between the threshold voltages Vth26, Vth27 of nMOS transistors 26, 27 apparently disappears.
[0028]
Thereafter, when the data of the selected memory cell is read out onto the bit line BL-B or the bit line /BL-B, the control signal φ5 is set to VCC , the nMOS transistor 31 is turned ON, and the nMOS transistors 26 and 27 are activated to perform an amplification operation, thereby amplifying the differential voltage between the bit lines BL-B and /BL-B generated by the selected memory cell.
[0029]
In this manner, in this DRAM as well, before the nMOS transistors 26, 27 perform their amplification operation, a charge sufficient to compensate for the offset voltage of the sense amplifier 25 is accumulated in the gates of the nMOS transistors 26, 27, thereby apparently eliminating the imbalance ΔVth between the threshold voltages Vth26, Vth27 of the nMOS transistors 26, 27 and preventing malfunction of the sense amplifier 25.
[0030]
[Problem to be solved by the invention]
However, the conventional DRAMs shown in Figures 20 and 23 use a VCC precharge method for bit line precharge, which is rarely used nowadays, and cannot be applied to semiconductor memory devices that use a bit line precharge method in which the bit lines are precharged to a voltage halfway between the maximum and minimum voltages during amplification, or near the halfway point.
[0031]
In view of the above, an object of the present invention is to provide a semiconductor memory device that employs a bit line precharge method for precharging bit lines to a voltage between the maximum and minimum voltages during amplification, that prevents malfunction of the sense amplifier due to imbalance in the threshold voltages of paired field effect transistors that constitute a sense amplifier made up of a flip-flop circuit, and that is capable of responding to miniaturization.
[0032]
[Means for solving the problem]
The present invention relates to a semiconductor memory device having a pair of first and second bit lines connected to a plurality of memory cells, the semiconductor memory device comprising: a bit line precharge circuit for precharging the first and second bit lines to a first voltage between a high potential voltage and a low potential voltage; and a sense amplifier for amplifying and outputting a potential difference between the first and second bit lines, the sense amplifier comprising a first field effect transistor of one conductivity type having a first current input/output electrode connected to a first node and a second current input/output electrode connected to the first bit line; The transistor comprises a second field effect transistor of one conductivity type connected to a first node and having a second current input/output electrode connected to a second bit line, a third field effect transistor of the other conductivity type having a first current input/output electrode connected to the second node, a fourth field effect transistor of the other conductivity type having a first current input/output electrode connected to the second node, a first switch element connected between the first node and the gate of the first field effect transistor, and a second switch element connected between the first node and the gate of the second field effect transistor.
[0033]
In the present invention, after the first and second bit lines are precharged to a first voltage, the sense amplifier turns on the first and second switch elements to diode-connect the first and second field effect transistors before data is read, and a second voltage is applied to the first node so that the difference between the voltage of the first bit line and the voltage of the second bit line is the same as the difference between the threshold voltage of the second field effect transistor and the threshold voltage of the first field effect transistor.
[0034]
Furthermore, during amplification operation, the sense amplifier has the first and second switch elements turned OFF, the first and third field effect transistors have their second current input/output electrodes connected to the first bit line and their gates connected to the second bit line, and the second and fourth field effect transistors have their second current input/output electrodes connected to the second bit line and their gates connected to the first bit line, forming a flip-flop circuit, and after a first sense amplifier drive voltage is applied to the first node to activate the first and second field effect transistors, a second sense amplifier drive voltage is applied to the second node to activate the third and fourth field effect transistors.
[0035]
That is, in the present invention , during amplification operation, the sense amplifier forms a flip-flop circuit using the first to fourth field effect transistors, and after the first and second field effect transistors in a pair are activated, the third and fourth field effect transistors in a pair are activated.
[0036]
Here, after the first and second bit lines are precharged to the first voltage, and before data is read, the first and second switch elements are turned ON to diode-connect the first and second field effect transistors, and the difference between the voltage of the first bit line and the voltage of the second bit line is made the same as the difference between the threshold voltage of the second field effect transistor and the threshold voltage of the first field effect transistor. Therefore, during the amplification operation, the imbalance in the threshold voltages of the first and second field effect transistors, which are activated first, appears to disappear.
[0037]
Therefore, according to the first invention, in a semiconductor memory device employing a bit line precharge method in which the bit lines are precharged to a voltage between the maximum and minimum voltages during amplification, it is possible to prevent malfunction of the sense amplifier due to imbalance in the threshold voltages of the pair of first and second field effect transistors that constitute a sense amplifier made up of a flip-flop circuit.
[0038]
[Embodiments of the Invention]
Hereinafter, first to sixth embodiments of the present invention will be described with reference to FIGS. 1 to 19, taking as an example the case where the present invention is applied to a DRAM.
[0039]
(First embodiment: Figures 1 to 4)
1 is a circuit diagram showing the main components of a first embodiment of the present invention. In the figure, WL-C denotes a word line for selecting a memory cell, BL-C and /BL-C denote pairs of bit lines to which a plurality of memory cells are connected, 33 denotes one of the memory cells connected to the bit line BL-C, 34 denotes a cell capacitor, and 35 denotes a cell transistor. In this example, the power supply voltage VCC is set to 1 V.
[0040]
Also, 36 is a bit line transfer circuit that connects the bit lines BL-C, /BL-C to a bit line precharge circuit and a sense amplifier, which will be described later, and 37 and 38 are nMOS transistors that form switch elements whose ON/OFF is controlled by a bit line transfer signal BT.
[0041]
Reference numeral 39 denotes a bit line precharge circuit that precharges the bit lines BL-C and /BL-C, and reference numerals 40 to 42 denote nMOS transistors that function as switch elements whose ON/OFF states are controlled by a bit line precharge signal PREC.
[0042]
Furthermore, Vref1 is a reference voltage higher than 0 [V] and lower than VCC/2 = 0.5 [V], for example, 0.3 [V], 43 is an nMOS transistor which serves as a switch element whose ON/OFF is controlled by a control signal RC1, and 44 is a reference voltage line which supplies the reference voltage Vref1 supplied via the nMOS transistor 43 to the bit line precharge circuit 39.
[0043]
Further, 45 denotes a sense amplifier made up of a flip-flop circuit, 46 and 47 denote a pair of nMOS transistors that perform an amplifying operation, and 48 and 49 denote a pair of pMOS transistors that perform an amplifying operation.
[0044]
Further, 50 and 51 are nMOS transistors which form switch elements whose ON/OFF is controlled by a control signal DIO, and 52 and 53 are nMOS transistors which form switch elements whose ON/OFF is controlled by a control signal CON.
[0045]
Also, 54 is an nMOS transistor whose ON/OFF is controlled by a control signal NCN, 55 is a sense amplifier drive voltage line that supplies the sense amplifier drive voltage SNL supplied via the nMOS transistor 54 to the sense amplifier 45, and 56 is a sense amplifier drive voltage line that supplies the sense amplifier drive voltage SPL to the sense amplifier 45.
[0046]
In this example, the sense amplifier drive voltage SNL has a voltage value of 0 [V], VCC/2 (0.5 [V]), or Vref1, and the sense amplifier drive voltage SPL has a voltage value of VCC, VCC/2, or Vref1.
[0047]
Furthermore, Vref2 is a reference voltage lower than the power supply voltage VCC and higher than VCC/2, for example, 0.8 V, 57 is an nMOS transistor that serves as a switch element whose ON/OFF is controlled by a control signal RC2, and 58 is a reference voltage line that supplies the reference voltage Vref2 supplied via the nMOS transistor 57 to the sense amplifier 45.
[0048]
2 and 3 are waveform diagrams showing the continuous read operation of data from memory cell 33, taking as an example the case where Vth47 (threshold voltage of nMOS transistor 47) = Vth46 (threshold voltage of nMOS transistor 46) + ΔVth. FIG. 2 shows the case where logic "0" is stored in memory cell 33, i.e., the voltage of storage node N6 of memory cell 33 = 0 [V], while FIG. 3 shows the case where logic "1" is stored in memory cell 33, i.e., the voltage of storage node N6 of memory cell 33 = VCC.
[0049]
2A and 3A show the voltage at node N5 and the sense amplifier drive voltage SPL, with the solid line representing the voltage at node N5 and the dashed line representing the sense amplifier drive voltage SPL.
[0050]
2B and 3B show the bit line precharge signal PREC and control signals RC1, NCN, and RC2, with the dashed line representing the bit line precharge signal PREC, the solid line representing the control signal RC1, the dotted line representing the control signal NCN, and the two-dotted line representing the control signal RC2.
[0051]
2C and 3C show the voltages of the control signals CON and DIO and the word line WL-C, with the dashed line representing the control signal CON, the dashed line representing the control signal DIO, and the solid line representing the voltage of the word line WL-C.
[0052]
2D and 3D show the voltages of the bit lines BL-C and /BL-C and the voltage of the storage node N6 of the memory cell 33, with the solid line representing the voltage of the bit line BL-C, the dashed line representing the voltage of the bit line /BL-C, and the dashed line representing the voltage of the storage node N6 of the memory cell 33.
[0053]
That is, in the first embodiment of the present invention, when the bit lines are precharged, the bit line transfer signal BT is at H level, the nMOS transistors 37 and 38 are ON, the control signal NCN is at H level, the nMOS transistor 54 is ON, the sense amplifier drive voltages SNL and SPL are VCC/2, and the bit line precharge signal PREC is at H level, and the nMOS transistors 40 to 42 are ON.
[0054]
Next, the control signal RC1 is set to H level, the nMOS transistor 43 is turned ON, and the bit lines BL-C and /BL-C are precharged to the reference voltage Vref1. In this case, the sense amplifier drive voltages SNL and SPL are set to Vref1.
[0055]
Furthermore, at the same timing as the rising edge of the control signal RC1, the control signal DIO is changed from a state in which the control signal DIO is at L level and the control signal CON is at H level, and the nMOS transistors 50, 51 are turned ON. Note that the control signal RC1 may be changed to H level after the control signal DIO is at H level and the nMOS transistors 50, 51 are turned ON.
[0056]
Thereafter, the control signals PREC, RC1, CON, and NCN are set to L level, and the control signal RC2 is set to H level, the nMOS transistors 40 to 43, 52, and 53 are set to OFF, the nMOS transistor 54 is set to OFF, and the nMOS transistor 57 is set to ON, the nMOS transistors 46 and 47 are each diode-connected, and the voltage of the node N5 is set to the reference voltage Vref2.
[0057]
As a result, bit lines BL-C and /BL-C are supplied with charge from node N5 via nMOS transistors 46 and 47, respectively, and the voltage of bit line BL-C rises from reference voltage Vref1 toward (Vref2-Vth46), and the voltage of bit line /BL-C rises from reference voltage Vref1 toward (Vref2-Vth47) = (Vref2-Vth46-ΔVth).
[0058]
Here, since it takes time to wait for the voltage of the bit line BL-C to reach Vref2-Vth46 and the voltage of the bit line /BL-C to reach Vref2-Vth46-ΔVth, the voltage of the bit line BL-C, /BL-C is set to a voltage close to VCC/2 and the voltage difference between the bit lines BL-C, /BL-C reaches ΔVth, that is, the voltage of the bit line BL-C=Vref2-Vth46-α (where α>0), the bit line When /BL-C=Vref2-Vth46-ΔVth-α, the control signals DIO and RC2 are set to L level, the control signal CON is set to H level, the nMOS transistors 50, 51, 57 are set to OFF, the nMOS transistors 52 and 53 are set to ON, the control signal NCN is set to H level, the nMOS transistor 54 is set to ON, the sense amplifier drive voltage SNL is set to VCC/2, and the sense amplifier drive voltage SPL is set to VCC/2.
[0059]
In this state, as shown in FIG. 4, the gate voltage of nMOS transistor 46, whose threshold voltage is Vth46, is such that: its gate voltage = voltage at node N8 = voltage on bit line BL-C ≈ Vref2 - Vth46 - ΔVth - α; and the gate voltage of nMOS transistor 47, whose threshold voltage is Vth47 = Vth46 + ΔVth, is such that: its gate voltage = voltage at node N7 = voltage on bit line BL-C ≈ Vref2 - Vth46 - α.
[0060]
That is, threshold voltage Vth47 of nMOS transistor 47 - threshold voltage Vth46 of nMOS transistor 46 = gate voltage of nMOS transistor 47 - gate voltage of nMOS transistor 46 = ΔVth, and the imbalance ΔVth between the threshold voltage Vth46 of nMOS transistor 46 and the threshold voltage Vth47 of nMOS transistor 47 apparently disappears, and a charge sufficient to compensate for the offset voltage of the sense amplifier 45 is accumulated in the gates of nMOS transistors 46 and 47.
[0061]
Thereafter, the word line WL-C is set to H level, data from the memory cell 33 is read onto the bit line BL-C, and the sense amplifier drive voltage SNL is set to 0 [V], activating the nMOS transistors 46 and 47 to start amplifying operation. Subsequently, the sense amplifier drive voltage SPL is set to VCC, activating the pMOS transistors 48 and 49 to start amplifying operation.
[0062]
As a result, the differential voltage between the bit lines BL-C and /BL-C is amplified, and as shown in Figure 2, when the memory cell 33 stores "0", the voltage of the bit line BL-C drops toward 0 [V] and the voltage of the bit line /BL-C rises toward VCC, and the data read from the memory cell 33 is latched into the sense amplifier 45.
[0063]
In contrast, as shown in FIG. 3, when memory cell 33 stores "1", the voltage of bit line BL-C rises toward VCC, and the voltage of bit line /BL-C falls toward 0 V, and the data read from memory cell 33 is latched by sense amplifier 45.
[0064]
As described above, according to the first embodiment of the present invention, before the sense amplifier 45 performs an amplification operation, an electric charge sufficient to compensate for the offset voltage of the sense amplifier 45 is accumulated in the gates of the nMOS transistors 46, 47, thereby apparently eliminating the imbalance ΔVth of the threshold voltages Vth46, Vth47 of the nMOS transistors 46, 47, and during the amplification operation, the nMOS transistors 46, 47 are activated before the pMOS transistors 48, 49. Therefore, even if the voltage difference between the bit lines BL-C, /BL-C falls below the imbalance ΔVth of the threshold voltages Vth46, Vth47 of the nMOS transistors 46, 47 as a result of miniaturization, normal operation of the sense amplifier 45 can be ensured, and miniaturization can be accommodated.
[0065]
(Second embodiment: Figs. 5 to 8)
FIG. 5 is a circuit diagram showing the main parts of a second embodiment of the present invention. The second embodiment of the present invention is provided with a sense amplifier 60 having a circuit configuration different from that of the sense amplifier 45 provided in the first embodiment of the present invention shown in FIG. 1, but is otherwise configured in the same manner as the first embodiment of the present invention.
[0066]
In this sense amplifier 60, 61 and 62 are a pair of nMOS transistors that perform an amplifying operation, and 63 and 64 are a pair of pMOS transistors that perform an amplifying operation.
[0067]
Further, 65 and 66 are nMOS transistors that form switch elements whose ON/OFF is controlled by a control signal DIO, 67 to 70 are nMOS transistors that form switch elements whose ON/OFF is controlled by a control signal CON, and 71 and 72 are nMOS transistors that form switch elements whose ON/OFF is controlled by the control signal DIO.
[0068]
6 and 7 are waveform diagrams showing the continuous read operation of data from memory cell 33, taking as an example the case where Vth62 (threshold voltage of nMOS transistor 62) = Vth61 (threshold voltage of nMOS transistor 61) + ΔVth. FIG. 6 shows the case where logic "0" is stored in memory cell 33, i.e., the voltage of storage node N6 of memory cell 33 = 0 [V], while FIG. 7 shows the case where logic "1" is stored in memory cell 33, i.e., the voltage of storage node N6 of memory cell 33 = VCC.
[0069]
6A and 7A show the voltage at node N5 and the sense amplifier drive voltage SPL, with the solid line representing the voltage at node N5 and the dashed line representing the sense amplifier drive voltage SPL.
[0070]
6B and 7B show the bit line precharge signal PREC and control signals RC1, NCN, and RC2, with the dashed line representing the bit line precharge signal PREC, the solid line representing the control signal RC1, the dotted line representing the control signal NCN, and the two-dotted line representing the control signal RC2.
[0071]
6C and 7C show the voltages of the control signals CON and DIO and the word line WL-C, with the dashed line representing the control signal CON, the dashed line representing the control signal DIO, and the solid line representing the voltage of the word line WL-C.
[0072]
6D and 7D show the voltages of the bit lines BL-C and /BL-C and the voltage of the storage node N6 of the memory cell 33, with the solid line representing the voltage of the bit line BL-C, the dashed line representing the voltage of the bit line /BL-C, and the dashed line representing the voltage of the storage node N6 of the memory cell 33.
[0073]
That is, in the second embodiment of the present invention, when the bit lines are precharged, the bit line transfer signal BT is at H level and the nMOS transistors 37 and 38 are on, the control signal NCN is at H level, the nMOS transistor 54 is on, the sense amplifier drive voltages SNL and SPL are VCC/2, and the bit line precharge signal PREC is at H level and the nMOS transistors 40 to 42 are on. In this case, the sense amplifier drive voltages SNL and SPL may be set to Vref1.
[0074]
Next, the control signal RC1 is set to H level, the nMOS transistor 43 is turned ON, and the bit lines BL-C and /BL-C are precharged to the reference voltage Vref1. In this case, the sense amplifier drive voltages SNL and SPL are set to Vref1.
[0075]
Furthermore, at the same timing as the rising edge of the control signal RC1, from a state in which the control signal DIO is at L level and the control signal CON is at H level, the control signal DIO is changed to H level and the nMOS transistors 65, 66, 71, and 72 are turned ON. Note that the control signal RC1 may also be changed to H level after the control signal DIO is set to H level and the nMOS transistors 65, 66, 71, and 72 are turned ON.
[0076]
Thereafter, the control signals PREC, RC1, CON, and NCN are set to L level, and the control signal RC2 is set to H level, the nMOS transistors 40 to 43, 67 to 70 are set to OFF, the nMOS transistor 54 is set to OFF, and the nMOS transistor 57 is set to ON, the nMOS transistors 61 and 62 and the pMOS transistors 63 and 64 are each diode-connected, and the voltage of the node N5 is set to the reference voltage Vref2.
[0077]
As a result, charge is supplied to the bit lines BL-C and /BL-C from node N5 via nMOS transistors 61 and 62, respectively, and the voltage of the bit line BL-C rises from the reference voltage Vref1 toward (Vref2-Vth61), and the voltage of the bit line /BL-C rises from the reference voltage Vref1 toward (Vref2-Vth62) = (Vref2-Vth61-ΔVth).
[0078]
Here, since it takes time to wait for the voltage of the bit line BL-C to reach Vref2-Vth61 and the voltage of the bit line /BL-C to reach Vref2-Vth61-ΔVth, the voltage of the bit line BL-C and /BL-C is set to a voltage close to VCC/2 and the voltage difference between the bit lines BL-C and /BL-C is ΔVth, that is, the voltage of the bit line BL-C=Vref2-Vth61-α and the voltage of the bit line /BL-C=V When Vth becomes ref2 - Vth61 - ΔVth - α, the control signals DIO and RC2 are set to L level, the control signal CON is set to H level, nMOS transistors 65, 66, 71, 72 are set to OFF, nMOS transistors 67 to 70 are set to ON, the control signal NCN is set to H level, nMOS transistor 54 is set to ON, the sense amplifier drive voltage SNL is set to VCC/2, and the sense amplifier drive voltage SPL is set to VCC/2.
[0079]
In this state, as shown in FIG. 8, the gate voltage of nMOS transistor 61 having a threshold voltage Vth61 is such that the voltage at node N8 = the voltage on bit line BL-C ≈ Vref2 - Vth61 - ΔVth - α, and the gate voltage of nMOS transistor 62 having a threshold voltage Vth62 = Vth61 + ΔVth is such that the voltage at node N7 = the voltage on bit line BL-C ≈ Vref2 - Vth61 - α.
[0080]
That is, threshold voltage Vth62 of nMOS transistor 62 - threshold voltage Vth61 of nMOS transistor 61 = gate voltage of nMOS transistor 62 - gate voltage of nMOS transistor 61 = ΔVth, and the imbalance ΔVth between the threshold voltage Vth61 of nMOS transistor 61 and the threshold voltage Vth62 of nMOS transistor 62 apparently disappears, and a charge sufficient to compensate for the offset voltage of the sense amplifier 60 is accumulated in the gates of nMOS transistors 61 and 62.
[0081]
Thereafter, the word line WL-C is set to H level, data from the memory cell 33 is read onto the bit line BL-C, and the sense amplifier drive voltage SNL is set to 0 [V], activating the nMOS transistors 61 and 62 to start amplifying operation, and subsequently the sense amplifier drive voltage SPL is set to VCC, activating the pMOS transistors 63 and 64 to start amplifying operation.
[0082]
As a result, the differential voltage between the bit lines BL-C and /BL-C is amplified, and as shown in Figure 6, if the memory cell 33 stores "0", the voltage of the bit line BL-C drops toward 0 [V] and the voltage of the bit line /BL-C rises toward VCC, and the data read from the memory cell 33 is latched into the sense amplifier 60.
[0083]
In contrast, as shown in Figure 7, when memory cell 33 stores "1", the voltage of bit line BL-C rises toward VCC, and the voltage of bit line /BL-C falls toward 0 [V], and the data read from memory cell 33 is latched into sense amplifier 60.
[0084]
As described above, according to the second embodiment of the present invention, before the sense amplifier 60 performs an amplification operation, an electric charge sufficient to compensate for the offset voltage of the sense amplifier 60 is accumulated in the gates of the nMOS transistors 61, 62, thereby apparently eliminating the imbalance ΔVth between the threshold voltages Vth61, Vth62 of the nMOS transistors 61, 62, and during the amplification operation, the nMOS transistors 61, 62 are activated before the pMOS transistors 63 , 64. Therefore, even if the voltage difference between the bit lines BL-C, /BL-C becomes equal to or less than the imbalance ΔVth between the threshold voltages Vth61, Vth62 of the nMOS transistors 61, 62 as a result of miniaturization, normal operation of the sense amplifier 60 can be ensured, and miniaturization can be accommodated.
[0085]
Furthermore, when the nMOS transistors 61 and 62 are diode-connected and the voltage of the bit line BL-C is increased from the reference voltage Vref1 toward (Vref2-Vth61) and the voltage of the bit line /BL-C is increased from the reference voltage Vref1 toward (Vref2-Vth62)=(Vref2-Vth61-ΔVth), the nMOS transistors 71 and 72 are turned ON and the pMOS transistors 63 and 64 are diode-connected. Therefore, even if the imbalance ΔVth between the threshold voltages Vth61 and Vth62 of the nMOS transistors 61 and 62 is large, the pMOS transistors 63 and 64 remain OFF, i.e., no current flows through the pMOS transistors 63 and 64, and the voltage of the bit line BL-C=Vref2-Vth61-α and the voltage of the bit line /BL-C=Vref2-Vth61-ΔVth-α can be established.
[0086]
(Third form: Figure 9)
FIG. 9 is a circuit diagram showing the main parts of a third embodiment of the present invention. The third embodiment of the present invention is provided with a sense amplifier 74 having a circuit configuration different from that of the sense amplifier 60 provided in the second embodiment of the present invention shown in FIG. 5, but is otherwise configured in the same manner as the second embodiment of the present invention.
[0087]
The sense amplifier 74 has nMOS transistors 67 and 69 connected in series between the gate of the nMOS transistor 61 and the gate of the pMOS transistor 63, and nMOS transistors 68 and 70 connected in series between the gate of the nMOS transistor 62 and the gate of the pMOS transistor 64. The connection point of the nMOS transistors 67 and 69 is connected to a node N8, and the connection point of the nMOS transistors 68 and 70 is connected to a node N7. Otherwise, the sense amplifier 74 is configured in the same way as the sense amplifier 60.
[0088]
In the third embodiment of the present invention, when the third embodiment is operated in the same manner as the second embodiment of the present invention, before the sense amplifier 74 performs an amplification operation, an electric charge sufficient to compensate for the offset voltage of the sense amplifier 74 is accumulated in the gates of the nMOS transistors 61, 62, thereby apparently eliminating the imbalance ΔVth of the threshold voltages Vth61, Vth62 of the nMOS transistors 61, 62, and during the amplification operation, the nMOS transistors 61, 62 can be activated before the pMOS transistors 63, 64. Therefore, even if the differential voltage between the bit lines BL-C, /BL-C becomes equal to or less than the imbalance ΔVth of the threshold voltages Vth61, Vth62 of the nMOS transistors 61, 62 due to miniaturization, normal operation of the sense amplifier 74 can be ensured, and miniaturization can be accommodated.
[0089]
Furthermore, when the nMOS transistors 61 and 62 are diode-connected and the voltage of the bit line BL-C is increased from the reference voltage Vref1 toward (Vref2-Vth61) and the voltage of the bit line /BL-C is increased from the reference voltage Vref1 toward (Vref2-Vth62)=(Vref2-Vth61-ΔVth), the nMOS transistors 71 and 72 can be turned ON and the pMOS transistors 63 and 64 can be diode-connected. Therefore, even if the imbalance ΔVth between the threshold voltages Vth61 and Vth62 of the nMOS transistors 61 and 62 is large, the pMOS transistors 63 and 64 maintain the OFF state, i.e., no current flows through the pMOS transistors 63 and 64, and the voltage of the bit line BL-C=Vref2-Vth61-α and the voltage of the bit line /BL-C=Vref2-Vth61-ΔVth-α.
[0090]
(Fourth embodiment: Figs. 10 to 13)
FIG. 10 is a circuit diagram showing the main parts of a fourth embodiment of the present invention. The fourth embodiment of the present invention is provided with a sense amplifier 77 having a circuit configuration different from that of the sense amplifier 45 provided in the first embodiment of the present invention, but is otherwise configured in the same manner as the first embodiment of the present invention.
[0091]
In this sense amplifier 77, 78 and 79 are a pair of nMOS transistors that perform an amplifying operation, and 80 and 81 are a pair of pMOS transistors that perform an amplifying operation.
[0092]
Further, 82 and 83 are nMOS transistors which form switch elements whose ON/OFF is controlled by a control signal DIO, and 84 to 87 are nMOS transistors which form switch elements whose ON/OFF is controlled by a control signal CON.
[0093]
11 and 12 are waveform diagrams showing the continuous read operation of data from memory cell 33, taking as an example the case where Vth79 (threshold voltage of nMOS transistor 79) = Vth78 (threshold voltage of nMOS transistor 78) + ΔVth. FIG. 11 shows the case where logic "0" is stored in memory cell 33, i.e., the voltage of storage node N6 of memory cell 33 = 0 [V], while FIG. 12 shows the case where logic "1" is stored in memory cell 33, i.e., the voltage of storage node N6 of memory cell 33 = VCC.
[0094]
11A and 12A show the voltage at node N5 and the sense amplifier drive voltage SPL, with the solid line representing the voltage at node N5 and the dashed line representing the sense amplifier drive voltage SPL.
[0095]
11B and 12B show the bit line precharge signal PREC and control signals RC1, NCN, and RC2, with the dashed line representing the bit line precharge signal PREC, the solid line representing the control signal RC1, the dotted line representing the control signal NCN, and the two-dotted line representing the control signal RC2.
[0096]
11C and 12C show the voltages of the control signals CON and DIO and the word line WL-C, with the dashed line representing the control signal CON, the dashed line representing the control signal DIO, and the solid line representing the voltage of the word line WL-C.
[0097]
11D and 12D show the voltages of the bit lines BL-C and /BL-C and the voltage of the storage node N6 of the memory cell 33, with the solid line representing the voltage of the bit line BL-C, the dashed line representing the voltage of the bit line /BL-C, and the dot-dash line representing the voltage of the storage node N6 of the memory cell 33.
[0098]
That is, in the fourth embodiment of the present invention, when the bit lines are precharged, the bit line transfer signal BT is at H level and the nMOS transistors 37 and 38 are on, the control signal NCN is at H level, the nMOS transistor 54 is on, the sense amplifier drive voltages SNL and SPL are VCC/2, and the bit line precharge signal PREC is at H level and the nMOS transistors 40 to 42 are on. In this case, the sense amplifier drive voltages SNL and SPL may be set to Vref1.
[0099]
Next, the control signal RC1 is set to H level, the nMOS transistor 43 is turned ON, and the bit lines BL-C and /BL-C are precharged to the reference voltage Vref1. In this case, the sense amplifier drive voltages SNL and SPL are set to Vref1.
[0100]
Furthermore, from a state in which the control signal DIO is at L level and the control signal CON is at H level, the control signal DIO is changed to H level at the same timing as the rising edge of the control signal RC1, and the nMOS transistors 82 and 83 are turned ON. Note that the control signal RC1 may be changed to H level after the control signal DIO is set to H level and the nMOS transistors 82 and 83 are turned ON.
[0101]
Thereafter, the control signals PREC, RC1, CON, and NCN are set to L level, and the control signal RC2 is set to H level, the nMOS transistors 40 to 43, 84 to 87 are set to OFF, the nMOS transistor 54 is set to OFF, and the nMOS transistor 57 is set to ON, the nMOS transistors 78 and 79 are each diode-connected, and the node N5 is set to the reference voltage Vref2.
[0102]
As a result, charge is supplied to the bit lines BL-C and /BL-C from node N5 via nMOS transistors 78 and 79, respectively, and the voltage of the bit line BL-C rises from the reference voltage Vref1 toward (Vref2-Vth78), and the voltage of the bit line /BL-C rises from the reference voltage Vref1 toward (Vref2-Vth79) = (Vref2-Vth78-ΔVth).
[0103]
Here, since it takes time to wait for the voltage of bit line BL-C to reach Vref2-Vth78 and the voltage of bit line /BL-C to reach Vref2-Vth78-ΔVth, when the voltages of bit lines BL-C and /BL-C are close to VCC/2 and the voltage difference between bit lines BL-C and /BL-C becomes ΔVth, that is, when the voltage of bit line BL-C=Vref2-Vth78-α and the voltage of bit line /BL-C=Vref2-Vth78-ΔVth-α, the control signals DIO and RC2 are set to L level, the control signal CON is set to H level, nMOS transistors 82 and 83 are set to OFF, nMOS transistors 84 to 87 are set to ON, the control signal NCN is set to H level, nMOS transistor 54 is set to ON, the sense amplifier drive voltage SNL is set to VCC/2, and the sense amplifier drive voltage SPL is set to VCC/2.
[0104]
In this state, as shown in FIG. 13, the gate voltage of nMOS transistor 78, whose threshold voltage is Vth78, is such that: (Voltage at node N8) (Voltage on bit line BL-C) = Vref2 - Vth78 - ΔVth - α; and the gate voltage of nMOS transistor 79, whose threshold voltage is Vth79 = Vth78 + ΔVth, is such that: (Voltage at node N7) (Voltage on bit line BL-C) = Vref2 - Vth78 - α.
[0105]
That is, threshold voltage Vth79 of nMOS transistor 79 - threshold voltage Vth78 of nMOS transistor 78 = gate voltage of nMOS transistor 79 - gate voltage of nMOS transistor 78 = ΔVth, and the imbalance ΔVth between the threshold voltage Vth78 of nMOS transistor 78 and the threshold voltage Vth79 of nMOS transistor 79 apparently disappears, and a charge sufficient to compensate for the offset voltage of the sense amplifier 77 is accumulated in the gates of nMOS transistors 78 and 79.
[0106]
Thereafter, the word line WL-C is set to H level, data from the memory cell 33 is read onto the bit line BL-C, and the sense amplifier drive voltage SNL is set to 0 [V], activating the nMOS transistors 78 and 79 to start amplifying operation, and subsequently the sense amplifier drive voltage SPL is set to VCC, activating the pMOS transistors 80 and 81 to start amplifying operation.
[0107]
As a result, the differential voltage between the bit lines BL-C and /BL-C is amplified, and as shown in Figure 11, when memory cell 33 stores "0", the voltage of bit line BL-C drops toward 0 [V] and the voltage of bit line /BL-C rises toward VCC, and the data read from memory cell 33 is latched into sense amplifier 77.
[0108]
In contrast, as shown in FIG. 12, when memory cell 33 stores "1", the voltage of bit line BL-C rises toward VCC, and the voltage of bit line /BL-C falls toward 0 V, and the data read from memory cell 33 is latched by sense amplifier 77.
[0109]
As described above, according to the fourth embodiment of the present invention, before the sense amplifier 77 performs an amplification operation, an electric charge sufficient to compensate for the offset voltage of the sense amplifier 77 is accumulated in the gates of the nMOS transistors 78, 79, thereby apparently eliminating the imbalance ΔVth of the threshold voltages Vth78, Vth79 of the nMOS transistors 78, 79, and during the amplification operation, the nMOS transistors 78, 79 are activated before the pMOS transistors 80, 81. Therefore, even if, as the miniaturization progresses, the differential voltage between the bit lines BL-C, /BL-C becomes equal to or less than the imbalance ΔVth of the threshold voltages Vth78, Vth79 of the nMOS transistors 78, 79, normal operation of the sense amplifier 77 can be ensured, and miniaturization can be accommodated.
[0110]
Furthermore, when nMOS transistors 78, 79 are each diode-connected and the voltage of bit line BL-C is increased from reference voltage Vref1 toward (Vref2-Vth78) and the voltage of bit line /BL-C is increased from reference voltage Vref1 toward (Vref2-Vth79)=(Vref2-Vth78-ΔVth), nMOS transistors 86, 87 are kept OFF. Therefore, even if the imbalance ΔVth between the threshold voltages Vth78 and Vth79 of nMOS transistors 78, 79 is large, no current flows through pMOS transistors 80, 81, and the voltage of bit line BL-C=Vref2-Vth78-α and the voltage of bit line /BL-C=Vref2-Vth78-ΔVth-α can be established.
[0111]
(Fifth embodiment: Figs. 14 to 17)
FIG. 14 is a circuit diagram showing the main parts of a fifth embodiment of the present invention. The fifth embodiment of the present invention is provided with a sense amplifier 89 having a circuit configuration different from that of the sense amplifier 77 provided in the fourth embodiment of the present invention shown in FIG. 10, but is otherwise configured in the same manner as the fourth embodiment of the present invention.
[0112]
This sense amplifier 89 is configured in the same manner as the sense amplifier 77, except that the nMOS transistors 84 and 85 provided in the sense amplifier 77 are omitted, and the junction point between the pMOS transistor 80 and the nMOS transistor 86 is connected to the gate of the pMOS transistor 81, and the junction point between the pMOS transistor 81 and the nMOS transistor 87 is connected to the gate of the pMOS transistor 80.
[0113]
15 and 16 are waveform diagrams showing the continuous read operation of data from memory cell 33, taking as an example the case where Vth79 (threshold voltage of nMOS transistor 79) = Vth78 (threshold voltage of nMOS transistor 78) + ΔVth, with FIG. 15 showing the case where logic "0" is stored in memory cell 33, i.e., the voltage of storage node N6 of memory cell 33 = 0 [V], and FIG. 16 showing the case where logic "1" is stored in memory cell 33, i.e., the voltage of storage node N6 of memory cell 33 = VCC.
[0114]
15A and 16A show the voltage at node N5 and the sense amplifier drive voltage SPL, with the solid line representing the voltage at node N5 and the dashed line representing the sense amplifier drive voltage SPL.
[0115]
15B and 16B show the bit line precharge signal PREC and control signals RC1, NCN, and RC2, with the dashed line representing the bit line precharge signal PREC, the solid line representing the control signal RC1, the dotted line representing the control signal NCN, and the two-dotted line representing the control signal RC2.
[0116]
15C and 16C show the voltages of the control signals CON and DIO and the word line WL-C, with the dashed line representing the control signal CON, the dashed line representing the control signal DIO, and the solid line representing the voltage of the word line WL-C.
[0117]
15D and 16D show the voltages of the bit lines BL-C and /BL-C and the voltage of the storage node N6 of the memory cell 33, with the solid line representing the voltage of the bit line BL-C, the dashed line representing the voltage of the bit line /BL-C, and the dot-dash line representing the voltage of the storage node N6 of the memory cell 33.
[0118]
That is, in the fifth embodiment of the present invention, when the bit lines are precharged, the bit line transfer signal BT is at H level and the nMOS transistors 37 and 38 are on, the control signal NCN is at H level, the nMOS transistor 54 is on, the sense amplifier drive voltages SNL and SPL are VCC/2, and the bit line precharge signal PREC is at H level and the nMOS transistors 40 to 42 are on. In this case, the sense amplifier drive voltages SNL and SPL may be set to Vref1.
[0119]
Next, the control signal RC1 is set to H level, the nMOS transistor 43 is turned ON, and the bit lines BL-C and /BL-C are precharged to the reference voltage Vref1. In this case, the sense amplifier drive voltages SNL and SPL are set to Vref1.
[0120]
Furthermore, from a state in which the control signal DIO is at L level and the control signal CON is at H level, the control signal DIO is changed to H level at the same timing as the rising edge of the control signal RC1, and the nMOS transistors 82 and 83 are turned ON. Note that the control signal RC1 may be changed to H level after the control signal DIO is set to H level and the nMOS transistors 82 and 83 are turned ON.
[0121]
Thereafter, the control signals PREC, RC1, CON, and NCN are set to L level, and the control signal RC2 is set to H level, the nMOS transistors 40 to 43, 86, and 87 are set to OFF, the nMOS transistor 54 is set to OFF, and the nMOS transistor 57 is set to ON, the nMOS transistors 78 and 79 are each diode-connected, and the node N5 is set to the reference voltage Vref2.
[0122]
As a result, charge is supplied to the bit lines BL-C and /BL-C from the node N5 via the nMOS transistors 78 and 79, respectively, and the voltage of the bit line BL-C rises from the reference voltage Vref1 toward (Vref2-Vth78), and the voltage of the bit line /BL-C rises from the reference voltage Vref1 toward (Vref2-Vth79) = (Vref2-Vth78-ΔVth).
[0123]
Here, since it takes time to wait for the voltage of bit line BL-C to reach Vref2-Vth78 and the voltage of bit line /BL-C to reach Vref2-Vth78-ΔVth, when the voltages of bit lines BL-C and /BL-C are close to VCC/2 and the voltage difference between bit lines BL-C and /BL-C becomes ΔVth, that is, when the voltage of bit line BL-C=Vref2-Vth78-α and bit line /BL-C=Vref2-Vth78-ΔVth-α, the control signals DIO and RC2 are set to L level, the control signal CON is set to H level, nMOS transistors 82 and 83 are set to OFF, nMOS transistors 86 and 87 are set to ON, the control signal NCN is set to H level, nMOS transistor 54 is set to ON, the sense amplifier drive voltage SNL is set to VCC/2, and the sense amplifier drive voltage SPL is set to VCC/2.
[0124]
In this state, as shown in FIG. 17, the gate voltage of nMOS transistor 78, whose threshold voltage is Vth78, is such that the voltage at node N8 is equal to the voltage on bit line BL-C, that is, Vref2-Vth78-ΔVth-α, and the gate voltage of nMOS transistor 79, whose threshold voltage is Vth79=Vth78+ΔVth, is such that the voltage at node N7 is equal to the voltage on bit line BL-C, that is, Vref2-Vth78-α.
[0125]
That is, threshold voltage Vth79 of nMOS transistor 79 - threshold voltage Vth78 of nMOS transistor 78 = gate voltage of nMOS transistor 79 - gate voltage of nMOS transistor 78 = ΔVth, and the imbalance ΔVth between the threshold voltage Vth78 of nMOS transistor 78 and the threshold voltage Vth79 of nMOS transistor 79 apparently disappears, and a charge sufficient to compensate for the offset voltage of sense amplifier 89 is accumulated in the gates of nMOS transistors 78 and 79.
[0126]
Thereafter, the word line WL-C is set to H level, data from the memory cell 33 is read onto the bit line BL-C, and the sense amplifier drive voltage SNL is set to 0 [V], activating the nMOS transistors 78 and 79 to start amplifying operation, and subsequently the sense amplifier drive voltage SPL is set to VCC, activating the pMOS transistors 80 and 81 to start amplifying operation.
[0127]
As a result, the differential voltage between the bit lines BL-C and /BL-C is amplified, and as shown in Figure 15, when the memory cell 33 stores "0", the voltage of the bit line BL-C drops toward 0 [V] and the voltage of the bit line /BL-C rises toward VCC, and the data read from the memory cell 33 is latched by the sense amplifier 89.
[0128]
In contrast, as shown in FIG. 16, when memory cell 33 stores "1", the voltage of bit line BL-C rises toward VCC, while the voltage of bit line /BL-C falls toward 0 V, and the data read from memory cell 33 is latched by sense amplifier 89.
[0129]
As described above, according to the fifth embodiment of the present invention, before the sense amplifier 89 performs an amplification operation, an electric charge sufficient to compensate for the offset voltage of the sense amplifier 89 is accumulated in the gates of the nMOS transistors 78, 79, thereby apparently eliminating the imbalance ΔVth of the threshold voltages Vth78, Vth79 of the nMOS transistors 78, 79, and during the amplification operation, the nMOS transistors 78, 79 are activated before the pMOS transistors 80, 81. Therefore, even if, as the miniaturization progresses, the differential voltage between the bit lines BL-C, /BL-C becomes equal to or less than the imbalance ΔVth of the threshold voltages Vth78, Vth79 of the nMOS transistors 78, 79, normal operation of the sense amplifier 89 can be ensured, and miniaturization can be accommodated.
[0130]
Furthermore, when nMOS transistors 78, 79 are each diode-connected and the voltage of bit line BL-C is increased from reference voltage Vref1 toward (Vref2-Vth78) and the voltage of bit line /BL-C is increased from reference voltage Vref1 toward (Vref2-Vth79)=(Vref2-Vth78-ΔVth), nMOS transistors 86, 87 are kept OFF. Therefore, even if the imbalance ΔVth between the threshold voltages Vth78 and Vth79 of nMOS transistors 78, 79 is large, no current flows through pMOS transistors 80, 81, and the voltage of bit line BL-C=Vref2-Vth78-α and the voltage of bit line /BL-C=Vref2-Vth78-ΔVth-α can be established.
[0131]
(Sixth form: Figures 18 and 19)
18 is a circuit diagram showing a main part of a sixth embodiment of the present invention, which includes a sense amplifier 91 having a circuit configuration different from that of the sense amplifier 45 provided in the first embodiment of the present invention shown in FIG.
[0132]
In this sense amplifier 91, 92 and 93 are a pair of pMOS transistors that perform an amplifying operation, and 94 and 95 are a pair of nMOS transistors that perform an amplifying operation.
[0133]
Also, 96 and 97 are nMOS transistors which form switch elements whose ON/OFF is controlled by a control signal DIO, and 98 and 99 are nMOS transistors which form switch elements whose ON/OFF is controlled by a control signal CON.
[0134]
Also, 100 is an nMOS transistor whose ON/OFF is controlled by a control signal PCN, 101 is a sense amplifier drive voltage line that supplies a sense amplifier drive voltage SPL supplied via the nMOS transistor 100 to the sense amplifier 91, and 102 is a sense amplifier drive voltage line that supplies a sense amplifier drive voltage SNL to the sense amplifier 91.
[0135]
The sense amplifier drive voltage SNL has a voltage value of 0 [V], VCC/2, or Vref3 (0.7 [V]), and the sense amplifier drive voltage SPL has a voltage value of VCC, VCC/2, or Vref3.
[0136]
Furthermore, Vref4 is a reference voltage higher than 0 [V] and lower than VCC/2, for example, 0.2 [V], 103 is an nMOS transistor forming a switch element whose ON/OFF is controlled by a control signal RC2, and 104 is a reference voltage line that supplies the reference voltage Vref4 supplied via the nMOS transistor 103 to the sense amplifier 91. The rest of the configuration is the same as that of the first embodiment of the present invention shown in FIG.
[0137]
In the sixth embodiment of the present invention, when the bit lines are precharged, the bit line transfer signal BT is at H level and the nMOS transistors 37 and 38 are on, the control signal PCN is at H level, the nMOS transistor 100 is on, the sense amplifier drive voltages SNL and SPL are VCC/2, and the bit line precharge signal PREC is at H level and the nMOS transistors 40 to 42 are on. In this case, the sense amplifier drive voltages SNL and SPL may be set to Vref3.
[0138]
Next, the control signal RC1 is set to H level, the nMOS transistor 43 is turned ON, and the bit lines BL-C and /BL-C are precharged to the reference voltage Vref3. In this case, the sense amplifier drive voltages SNL and SPL are set to Vref3.
[0139]
Furthermore, at the same timing as the rising edge of the control signal RC1, the control signal DIO is changed from a state in which the control signal DIO is at L level and the control signal CON is at H level, and the nMOS transistors 96 and 97 are turned ON. Note that the control signal RC1 may be changed to H level after the control signal DIO is at H level and the nMOS transistors 96 and 97 are turned ON.
[0140]
Thereafter, the control signals PREC, RC1, and PCN are set to L level, the control signal CON is set to H level, and the control signal RC2 is set to H level, the nMOS transistors 40 to 43, 98, 99, and 100 are set to OFF, the nMOS transistor 103 is set to ON, the pMOS transistors 92 and 93 are each diode-connected, and the node N7 is set to the reference voltage Vref4.
[0141]
As a result, for example, if Vth93 (threshold voltage of pMOS transistor 93) = Vth92 (threshold voltage of nMOS transistor 92) + ΔVth, the bit lines BL-C and /BL-C discharge their charges toward node N9 via pMOS transistors 92 and 93, respectively, and the voltage of bit line BL-C drops from reference voltage Vref3 toward (Vref4 - Vth92), and the voltage of bit line /BL-C drops from reference voltage Vref3 toward (Vref4 - Vth93) = (Vref4 - Vth92 - ΔVth).
[0142]
Here, since it takes time to wait for the voltage of the bit line BL-C to reach Vref4-Vth92 and the voltage of the bit line /BL-C to reach Vref2-Vth92-ΔVth, the voltage of the bit line BL-C and /BL-C is set to a voltage close to VCC/2 and the voltage difference between the bit lines BL-C and /BL-C reaches ΔVth, that is, the voltage of the bit line BL-C=Vref4-Vth92+α and the voltage of the bit line /BL-C= When Vref4-Vth92-ΔVth+α is reached, the control signals DIO and RC2 are set to L level, the control signal CON is set to H level, nMOS transistors 96, 97, 103 are set to OFF, nMOS transistors 98 and 99 are set to ON, the control signal PCN is set to H level, nMOS transistor 100 is set to ON, the sense amplifier drive voltage SNL is set to VCC/2, and the sense amplifier drive voltage SPL is set to VCC/2.
[0143]
In this state, as shown in FIG. 19, the gate voltage of pMOS transistor 92, whose threshold voltage is Vth92, is such that: (Voltage at node N8) (Voltage on bit line BL-C) = Vref4 - Vth92 - ΔVth + α; and the gate voltage of pMOS transistor 93, whose threshold voltage is Vth93 = Vth92 + ΔVth, is such that: (Voltage at node N7) (Voltage on bit line BL-C) = Vref4 - Vth92 + α.
[0144]
That is, threshold voltage Vth93 of pMOS transistor 93 - threshold voltage Vth92 of pMOS transistor 92 = gate voltage of pMOS transistor 93 - gate voltage of nMOS transistor 92 = ΔVth, and the imbalance ΔVth between the threshold voltage Vth92 of pMOS transistor 92 and the threshold voltage Vth93 of pMOS transistor 93 apparently disappears, and a charge sufficient to compensate for the offset voltage of the sense amplifier 91 is accumulated in the gates of pMOS transistors 92 and 93.
[0145]
Thereafter, the word line WL-C is set to H level, data from the memory cell 33 is read onto the bit line BL-C, and the sense amplifier drive voltage SPL is set to VCC, activating the pMOS transistors 92 and 93 to start amplifying operation. Subsequently, the sense amplifier drive voltage SNL is set to 0 [V], activating the nMOS transistors 94 and 95 to start amplifying operation.
[0146]
As a result, the differential voltage between bit lines BL-C and /BL-C is amplified, and if memory cell 33 stores "0", the voltage of bit line BL-C drops toward 0 [V] and the voltage of bit line /BL-C rises toward VCC, and the data read from memory cell 33 is latched into sense amplifier 91.
[0147]
On the other hand, if memory cell 33 stores "1", the voltage of bit line BL-C rises toward VCC and the voltage of bit line /BL-C falls toward 0 [V], and the data read from memory cell 33 is latched into sense amplifier 91.
[0148]
As described above, according to the sixth embodiment of the present invention, before the sense amplifier 91 performs an amplification operation, an electric charge sufficient to compensate for the offset voltage of the sense amplifier 91 is accumulated in the gates of the pMOS transistors 92, 93, thereby apparently eliminating the imbalance ΔVth of the threshold voltages Vth92, Vth93 of the pMOS transistors 92, 93, and during the amplification operation, the pMOS transistors 92, 93 are activated before the nMOS transistors 94, 95. Therefore, even if the voltage difference between the bit lines BL-C, /BL-C becomes equal to or less than the imbalance ΔVth of the threshold voltages Vth92, Vth93 of the pMOS transistors 92, 93 as a result of miniaturization, normal operation of the sense amplifier 91 can be ensured, and miniaturization can be accommodated.
[0149]
[Effects of the Invention]
As described above, according to the present invention , in a semiconductor memory device employing a bit line precharge method in which a bit line is precharged between the maximum and minimum voltages during amplification, it is possible to prevent malfunction of the sense amplifier due to imbalance in the threshold voltages of a pair of field effect transistors that constitute a sense amplifier made up of a flip-flop circuit, and to accommodate miniaturization.
[Brief explanation of the drawings]
FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.
FIG. 2 is a waveform diagram showing a continuous read operation of data from memory cells in the first embodiment of the present invention.
FIG. 3 is a waveform diagram showing a continuous read operation of data from memory cells in the first embodiment of the present invention.
FIG. 4 is a circuit diagram for explaining the operation of the first embodiment of the present invention.
FIG. 5 is a circuit diagram showing a main part of a second embodiment of the present invention.
FIG. 6 is a waveform diagram showing a continuous read operation of data from memory cells in a second embodiment of the present invention.
FIG. 7 is a waveform diagram showing a continuous read operation of data from memory cells in a second embodiment of the present invention.
FIG. 8 is a circuit diagram for explaining the operation of the second embodiment of the present invention.
FIG. 9 is a circuit diagram showing a main part of a third embodiment of the present invention.
FIG. 10 is a circuit diagram showing a main part of a fourth embodiment of the present invention.
FIG. 11 is a waveform diagram showing a continuous read operation of data from memory cells in a fourth embodiment of the present invention.
FIG. 12 is a waveform diagram showing a continuous read operation of data from memory cells in the fourth embodiment of the present invention.
FIG. 13 is a circuit diagram for explaining the operation of the fourth embodiment of the present invention.
FIG. 14 is a circuit diagram showing a main part of a fifth embodiment of the present invention.
FIG. 15 is a waveform diagram showing a continuous read operation of data from memory cells in the fifth embodiment of the present invention.
FIG. 16 is a waveform diagram showing a continuous read operation of data from memory cells in the fifth embodiment of the present invention.
FIG. 17 is a circuit diagram for explaining the operation of the fifth embodiment of the present invention.
FIG. 18 is a circuit diagram showing a main part of a sixth embodiment of the present invention.
FIG. 19 is a circuit diagram for explaining the operation of the sixth embodiment of the present invention.
FIG. 20 is a circuit diagram showing a main part of an example of a conventional DRAM.
21 is a waveform diagram showing the operations of the conventional DRAM shown in FIG. 20 when precharging bit lines and when reading data.
22 is a circuit diagram for explaining the operation of the conventional DRAM shown in FIG. 20 when precharging bit lines.
FIG. 23 is a circuit diagram showing a main part of another example of a conventional DRAM.
24 is a waveform diagram showing the operations of the conventional DRAM shown in FIG. 23 during bit line precharging and data reading.
25 is a circuit diagram for explaining the operation of the conventional DRAM shown in FIG. 23 when precharging bit lines.
[Explanation of symbols]
46, 47: Pair of nMOS transistors 48, 49 that perform an amplifying operation; Pair of pMOS transistors 61, 62 that perform an amplifying operation; Pair of nMOS transistors 63, 64 that perform an amplifying operation; Pair of pMOS transistors 78, 79 that perform an amplifying operation; Pair of nMOS transistors 80, 81 that perform an amplifying operation; Pair of pMOS transistors 92, 93 that perform an amplifying operation; Pair of pMOS transistors 94, 95 that perform an amplifying operation; Pair of nMOS transistors that perform an amplifying operation