JPH1063370A - Data load circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent data from being errorneously held in plural integrated circuits which are cascade-connected. SOLUTION: When the states of the enable terminals E12 and E13 of the integrated circuits 2 and 3 are changed from a low level into the high level after the integrated circuits 1, 2 and 3 are reset, the input of clocks CLK2 and CLK3 for holding data to the integrated circuits 2 and 3 is prohibited. When the states of the enable terminals E12 and E13 are changed from the high level into the low level after that, a the input of the clocks CLK2 and CLK3 are permitted. Thus, a faultiness where data to be held in the first stage integrated circuit 1 is errorneously simultaneously held in the integrated circuits 2 and 3 after the succeeding stage is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cascade connection of a plurality of integrated circuits each having a built-in holding circuit for holding predetermined bit data, and sequentially transfers the predetermined bit data from the first integrated circuit to the next integrated circuit. The present invention relates to a data load circuit to be held.

[0002]

2. Description of the Related Art When character display is performed on a liquid crystal display, a plasma display, or the like, display data for character display (for example, "1" indicates display and "0" indicates no display) is corresponding to a display position. An integrated circuit that holds and supplies the data to the display to perform display driving is used. However, since the number of display data bits that can be held by one integrated circuit is limited, a plurality of integrated circuits can be cascaded to increase the number of display data bits that can be supplied to the display at one time in parallel. I am doing it. For example, assuming that the holding circuit built in one integrated circuit can hold 240 bits of display data and the 720 bits of display data are to be displayed in parallel, three integrated circuits may be connected in cascade. Will be. Hereinafter, a conventional data load circuit in which three integrated circuits are cascaded will be described with reference to FIG.

In FIG. 3, (1), (2), and (3) are first-stage, second-stage, and third-stage integrated circuits, respectively, and each of the integrated circuits (1), (2), and (3) is a printed circuit board. The above is connected via the wiring (4). First-stage integrated circuit (1)
Has a built-in holding circuit (5) in which 240 D flip-flops (not shown) are cascaded and capable of holding 240 bits of display data. The holding circuit (5) has 8
The display data DATA of the bit unit is applied in parallel in synchronization with the clock CLK1, that is, the display data DATA of the 8-bit unit is sequentially taken into the holding circuit (5) in synchronization with the 30 clocks CLK1, so that the holding circuit (5) is provided. (5) is a state where 240-bit display data is held in all the D flip-flops. The display data DA
TA is applied to the holding circuit (5) through the 8-bit data bus (6), and the enable terminal EI1 for enabling the integrated circuit (1) is low active,
Grounded. The integrated circuit (1) has a clock C
A 5-bit counter (7) for counting LK1 is built in, and an overflow signal OF1 that becomes "1" when 30 clocks CLK1 are counted is output. Further, the integrated circuit (1) incorporates an AND gate (8) for generating the clock CLK1,
The following three inputs, that is, the state of the enable terminal EI1 and the overflow output OF1 of the counter (7) are inverted and applied to the D gate (8) and the original clock CLK is applied to the D gate (8). Therefore, in the first-stage integrated circuit (1), since the enable terminal EI1 is always fixed to the low level, generation of the clock CLK1 depends only on the overflow signal OF1 of the counter (7), that is, generation of 30 clocks CLK1. When the holding circuit (5) finishes holding all the 240-bit display data, the overflow signal OF1
Becomes "1", and the generation of the clock CLK1 is stopped from the AND gate (8). Thus, the content of the holding circuit (5) is fixed as it is while holding the display data of 240 bits, and the counter (7) is fixed while outputting the overflow signal OF1 of "1". The overflow signal OF1 of the counter (7) is output from the terminal EO1 via the inverter (9). If the overflow signal OF1 is “1”, the output of the terminal EO1 becomes an enable signal for the second-stage integrated circuit (2). The integrated circuits (1), (2), and (3) receive the load signal LOAD before performing the so-called data load that causes the holding circuit (5) to hold the display data, so that the internal holding circuits (5) and (5) The counter (7) is reset.

Since the second-stage integrated circuit (2) and the third-stage integrated circuit (3) have the same configuration as the first-stage integrated circuit (1), the internal elements of the integrated circuits (2) and (3) For the same configuration as the integrated circuit (1), the same number is written,
The description is omitted. However, since the third-stage integrated circuit (3) does not need to generate an enable signal to the next stage, the inverter (9) is omitted.

[0005] (10) (11) (12) is a 240-stage D
Flip-flops, each of which is an integrated circuit (1) (2)
(3) The contents held by the internal holding circuit (5) are set at the timing to be displayed on the display. The individual D flip-flops constituting the holding circuit (5) of each integrated circuit (1) (2) (3) correspond to 240 individual D flip-flops (10) (11) (12), respectively. ing. These D flip-flops (10)
(11) and (12) are loaded with the contents of the preceding holding circuit (5) by the generation of the load signal LOAD, and the counter (7) in the integrated circuits (1), (2) and (3) is loaded.
Is reset to the initial state.

In the above configuration, when 240 bits (= 8 bits × 30) of display data is held in the first-stage integrated circuit (1), the overflow signal OF1 of the counter (7) becomes “1”. The output of the clock CLK1 from the AND gate (8) is stopped, the contents of the holding circuit (5) are held as it is, the counter (7) is stopped, and the output of the terminal EO1 becomes "0".

The output of the terminal EO1 of the first-stage integrated circuit (1) is applied to the enable terminal EI2 of the second-stage integrated circuit (2) via the wiring (4). This enable terminal EI2
Becomes low according to "0" of the terminal EO1, the second-stage integrated circuit (2) is enabled, and the clock CLK2 starts to be generated from the AND gate (8). Thus, the next 240-bit display data is held in the second-stage integrated circuit (2). Then, since the overflow signal OF2 of the counter (7) becomes "1", the output of the clock CLK2 from the AND gate (8) is stopped, the content of the holding circuit (5) is held as it is, and the counter (7) is turned on. The operation stops, and the terminal EO2 output becomes “0”.

The output of the terminal EO2 of the second integrated circuit (2) is applied to the enable terminal EI3 of the third integrated circuit (3) via the wiring (4). This enable terminal EI
When 3 goes low according to “0” of the terminal EO2, 3
The integrated circuit (3) at the stage becomes enabled, and AND
The clock CLK3 starts to be generated from the gate (8). As a result, the next 240-bit display data is held in the third-stage integrated circuit (2). Then, since the overflow signal OF3 of the counter (7) becomes "1", the output of the clock CLK3 from the AND gate (8) is stopped, the content of the holding circuit (5) is held as it is, and the counter (7) is turned on. Stop operation.

The display data held in the integrated circuits (1), (2), and (3) are D flip-flops (10), (11), and (12) for display on the display at a predetermined display timing. Is held.

[0010]

After the display data is output from the integrated circuits (1), (2), and (3) to the corresponding D flip-flops (10), (11), and (12), the following new data is output. Display data is integrated into an integrated circuit (1) (2)
In order to load the data into (3), the integrated circuit (1) (2) (3) and the D flip-flop (1
0) (11) (12) must be reset.

However, even if the integrated circuits (1), (2) and (3) are reset, a time constant circuit is formed by the resistance and the capacitance of the wiring (4), and the following problems occur. That is, the terminals EO of the integrated circuits (1) and (2)
1, EO2 instantaneously goes to a high level upon reset. The enable terminals EI2, EI3 of the integrated circuits (2), (3) respectively connected to the terminals EO1 and EO2 are instantaneous due to the time constant of the interposed wiring (4). Can not rise to a high level. In other words, the integrated circuit (1)
Although (2) outputs a high-level signal to disable to the integrated circuits (2) and (3), the enable terminals EI2 and E1 of the integrated circuits (2) and (3) are output.
Because of the time constant, I3 can only gradually rise from the low level to the high level. As a result, the AND gate (8) of the integrated circuits (2) and (3) is based on the time constant from reset. For a predetermined time, the state of the enable terminals EI2 and EI3 recognized as low level is applied. Thus, the clock CLK1 is supplied to the integrated circuit (1).
Are applied to the integrated circuits (2) and (3) at the same time, the display data to be written in the holding circuit of the integrated circuit (1) is held in the integrated circuits (2) and (3). The circuit (5) also has a problem in that writing is performed for a predetermined time based on the time constant.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to solve the problem that after a plurality of cascaded integrated circuits are reset, a predetermined number of bits of data are erroneously written to the plurality of integrated circuits simultaneously. And

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a feature thereof is a holding circuit for holding data of a predetermined number of bits in synchronization with a clock. An integrated circuit comprising: a detection circuit for detecting that data holding in the holding circuit is completed; and a clock generation circuit for generating the clock based on an enable signal, an output of the detection circuit, and an original clock. After a plurality of cascade connections are performed and the plurality of integrated circuits are reset to perform data loading, the output of the detection circuit provided in each of the integrated circuits is used as an enable signal of the next-stage integrated circuit. In a data load circuit for sequentially loading data of the number of bits for each of the integrated circuits, when a reset of the plurality of integrated circuits is performed, When the output of the detection circuit becomes one of the logical values that disables the next-stage integrated circuit, the enable signal of the next-stage integrated circuit has the wiring connecting the preceding and next-stage integrated circuits. In the period until the clock generation circuit recognizes that the other logical value has changed from the other logical value to the one logical value by the constant, means for inhibiting the clock input to the next integrated circuit is provided. is there. Further, the means for inhibiting the clock input to the next integrated circuit is provided after resetting the plurality of integrated circuits.
After detecting that the enable signal of each of the integrated circuits has changed from the other logical value to one of the logical values, the change signal is changed from one logical value to the other logical value, and the clock input to each of the integrated circuits is permitted. It is characterized by the following.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit diagram showing a data load circuit of the present invention, and each integrated circuit (1) (2) shown in FIG.
(3) Each is provided inside. In FIG. 1, (13)
Is an enable terminal, and each integrated circuit (1) (2)
(3) corresponds to the enable terminals EI1, EI2, and EI3. (14) is a preceding stage D flip-flop, and its D (data) input is connected to the enable terminal (13) through two stages of serially connected inverters (15) and (16). (17) is a subsequent D flip-flop. The D terminal is connected to the Q of the preceding D flip-flop (14).
(Output) terminal. The original clock CLK is commonly applied to the C (clock) terminals of the D flip-flops (14) and (17), and the high active load signal LOAD is inverted and applied to the R (reset) terminal via the inverter (18). Is done. (19) a NAND gate for inverting and outputting the logical product of the output of the * Q (inverted output) terminal of the D flip-flop (14) and the Q terminal output of the D flip-flop (17). The NAND gates (20) and (21) constitute an RS flip-flop. One input of the NAND gate (20) serving as a set terminal is connected to the output of the NAND gate (19), and the NAND gate (21) serving as a reset terminal. A load signal LOAD is applied to one of the inputs via an inverter (18). Then, from the output of the NAND gate (21), the enable signals EI1 ', EI2', EI which fall from a high level to a low level when the RS flip-flop is set in synchronization with the rise of the original clock CLK.
3 'is output.

In each of the integrated circuits (1), (2) and (3) in FIG. 3, enable terminals EI1, EI2, EI3 and A
The circuit of FIG. 1 is provided between the enable input of the ND gate (8) and the state input of the enable terminal, and the reset outputs EI1 ′, EI2 ′, and EI3 ′ of the RS flip-flop are connected to the EI gate.
1, EI2 and EI3 are applied to the AND gate (8). This operation will be described with reference to the waveform diagram of FIG. FIG. 2 shows waveforms of data retention of the integrated circuits (1) and (2).

First, as an initial setting, the load signal LOA
When D becomes high level and occurs for a predetermined time, initialization inside the integrated circuits (1), (2) and (3) is performed. Then, the counter (7) is reset, the output of the terminal EO1 of the integrated circuit (1) sharply rises to the high level, and the integrated circuit (2) at the next stage attempts to disable. However, the input of the enable terminal EI2 of the integrated circuit (2) is connected to the terminal EO1 of the integrated circuit (1) and the integrated circuit (2).
Due to the time constant of the wiring (4) interposed between the terminal EO1 and the enable terminal EI2, even if the terminal EO1 rises sharply, it can only gradually rise. The gradual rising of the enable terminal EI2 is sampled by the circuit of FIG. 1 at the rising of the original clock CLK.
5) Even if the change from low level to high level is detected by (16), the output of the RS flip-flop remains at high level. That is, the enable terminal EI is connected to the AND gate (8) of the integrated circuit (2).
Although EI2 'is applied instead of the state of 2,
Since EI2 'is at the high level, the AN of the integrated circuit (2) is
D gate (8) is in a closed state, and CKL2
Does not occur. As a result, while the 8-bit data DATA is held in the holding circuit (5) inside the integrated circuit (1), the next-stage integrated circuit (2) stops the data holding operation and erroneously occurs. In addition, the inconvenience of holding data to be held in the integrated circuit (1) in the integrated circuit (2) can be avoided.

Thereafter, when the counter (7) inside the integrated circuit (1) counts 30 rising edges of the clock CLK1 and outputs a high-level overflow signal OF1, the terminal EO1 becomes low level, and the integrated circuit (2) is reset. Attempt to enable. However, the integrated circuit (2) can only gradually fall due to the time constant of the wiring (4) between the terminal EO1 of the integrated circuit (1) and the enable terminal EI2 of the integrated circuit (2). Can not. Then, by gradually sampling the falling edge of the enable terminal EI2 at the rising edge of the original clock CLK with the threshold voltage Vth of the inverter (16) as a boundary, the data DATA is integrated.
In synchronization with the rising edge of the original clock CLK generated at the boundary between the last 8-bit unit data 1-30 to be held at the first time and the 8-bit unit data 2-1 to be held first by the integrated circuit (2). The output of the RS flip-flop falls to a low level. As a result, the AND gate (8) of the integrated circuit (2) opens the gate, the clock CLK2 starts to be generated, and the 8-bit data DATA2-1, 2-2,.
.. Are held in the holding circuit (5) in synchronization with the fall of the clock CLK2. This operation is the same between the integrated circuits (2) and (3).

As described above, after the reset of the integrated circuits (1), (2) and (3), when the waveforms of the enable terminals EI2 and EI3 rise, the generation of the clocks CLK2 and CLK3 is inhibited. Since the generation of the clocks CLK2 and CLK3 is permitted when the waveform falls, the data to be held in the integrated circuit (1) is erroneously held in the integrated circuits (2) and (3) at the same time. Problems can be resolved.

Incidentally, the present invention is not limited to the circuit shown in FIG. 1 and ignores the rise of the enable terminals EI2 and EI3 after the reset of the integrated circuits (1), (2) and (3) as in the embodiment of the present invention. Any configuration may be used as long as it can respond to the subsequent fall.

[0020]

According to the present invention, when reset signals of a plurality of integrated circuits change from one logical value to another logical value after resetting of the plurality of integrated circuits, the integrated circuit of the next stage is reset. Prohibit clock input to hold data to
Thereafter, when the enable signal changes from the other logical value to one logical value, the clock input is permitted. As a result, there is obtained an advantage that it is possible to solve the problem that data to be held in the first-stage integrated circuit is erroneously and simultaneously held in the next and subsequent integrated circuits.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a data load circuit of the present invention.

FIG. 2 is a waveform chart showing the operation of FIG.

FIG. 3 is a circuit diagram showing a conventional data load circuit.

[Explanation of symbols]

 (1) (2) (3) Integrated circuit (4) Wiring (5) Holding circuit (7) Counter (8) AND gate (14) (17) D flip-flop

Claims (2)

[Claims] A holding circuit for holding data of a predetermined number of bits in synchronization with a clock, a detection circuit for detecting completion of data holding in the holding circuit, an enable signal,
After cascading a plurality of integrated circuits each including an output of the detection circuit and a clock generation circuit that generates the clock based on the original clock, and resetting the plurality of integrated circuits to perform data loading, A data load circuit that sequentially loads data of a predetermined number of bits in units of the integrated circuits by using an output of the detection circuit provided in each of the integrated circuits as an enable signal of an integrated circuit in a next stage; When the output of the detection circuit in the integrated circuit of the preceding stage becomes one of the logical values that disables the integrated circuit of the next stage at the time of resetting the integrated circuits, the enable signal of the integrated circuit of the next stage Is changed from the other logical value to one logical value by the time constant of the wiring connecting the integrated circuit of the previous stage and the next stage. A data load circuit comprising means for inhibiting the clock input to the next integrated circuit during a period until it is recognized. 2. The method according to claim 1, wherein said means for inhibiting clock input to said next integrated circuit comprises: after resetting said plurality of integrated circuits, changing an enable signal of each of said integrated circuits from the other logical value to one logical value. 2. The data load circuit according to claim 1, wherein a change from one logical value to the other logical value is detected after that, and the clock input to each of the integrated circuits is permitted.