JPH1064953A - Face-down bonding semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a face-down bonding semiconductor device suitable for flip-chip bonding a semiconductor substrate having electric connection portions having different surface heights on an insulating substrate having wiring electrodes, and manufacturing thereof. It is an object of the present invention to provide a face-down bonding semiconductor device capable of performing uniform face-down bonding using a semiconductor substrate having a step on the surface and pillars, and a method of manufacturing the same. SOLUTION: A semiconductor substrate 11 having electric connection portions having different surface heights formed on one surface, and an insulating substrate 18 having a wiring electrode 19 formed on the surface thereof have the electric connection portion and the wiring electrode 19 respectively. Are electrically and mechanically connected to each other, the conductive pillars 16 and 17 having different heights are configured such that the relatively high pillar 17 has a larger diameter than the relatively low pillar 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a face-down bonding semiconductor device and a method of manufacturing the same, and more particularly, to a method of flip-chip bonding a semiconductor substrate having electric connection portions having different surface heights on an insulating substrate having wiring electrodes. The present invention relates to a face-down bonding semiconductor device suitable for a semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with an increase in bandwidth of a communication system or the like, a demand for a semiconductor device having a high operating frequency has been increased. A compound semiconductor such as GaAs has higher carrier mobility than Si and is suitable for a semiconductor device which operates at high speed. However, a semiconductor chip using a compound semiconductor is more expensive than a semiconductor chip using Si.

In many applications, high-speed operation is rarely required for the entire circuit, and it is sufficient that a part of the circuit can operate at high speed. In addition, there are some circuit parts where higher integration density is desired than high-speed operation. Therefore, a method is employed in which only a portion of the circuit requiring high-speed (high-frequency) operation is formed on a chip such as a compound semiconductor.

In a high-frequency circuit, it is important to reduce the inductance and capacitance of the line. It is desirable that the high-frequency semiconductor chip be connected to the line by a connecting means that is as short as possible with low resistance. Face-down bonding such as flip-chip bonding, in which a surface electrode on a semiconductor substrate is connected to a wiring electrode on an insulating substrate using bumps, pillars, or the like, is suitable for such purpose.

[0005]

When face-down bonding is performed using bumps, pillars, and the like, the bumps and pillars are usually formed at the same height. When the semiconductor surface has a step, it is difficult to perform face-down bonding directly on the step surface. Even if a slight difference in elevation is absorbed by crushing bumps or pillars, it is difficult to make the bonding characteristics uniform.

An object of the present invention is to provide a face-down bonding semiconductor device capable of performing uniform face-down bonding using a semiconductor substrate having a step on the surface and pillars, and a method of manufacturing the same.

It is another object of the present invention to provide a method of manufacturing a face-down bonding semiconductor device in which pillars having different heights can be easily formed on a substrate.

[0008]

According to one aspect of the present invention, there is provided a semiconductor substrate having electric connection portions having different surface heights formed on one surface, an insulating substrate having a wiring electrode formed on the surface,
Conductive pillars having different heights for electrically and mechanically connecting the electrical connection part and the wiring electrode, wherein a relatively high pillar has a larger diameter than a relatively low pillar. And a face-down bonding semiconductor device having:

By changing the diameter of the pillar, pillars having different heights can be easily formed. By selecting the diameter, the height of the pillar can be selected.

According to another aspect of the present invention, a step of preparing a semiconductor substrate having electric connection portions having different surface heights on one surface and an insulating substrate having wiring electrodes formed on the surface;
On one of the semiconductor substrate and the insulating substrate,
Forming a resist pattern having a plurality of openings having different diameters exposing a part of the conductive surface of the electrical connection portion or the wiring electrode; and forming a conductive pattern exposed in the plurality of openings on the one substrate. Contact the plating surface with the plating solution,
A plating step of forming pillars, and a step of face-down bonding the one substrate on which the pillars are formed and the other substrate, wherein the diameter of the pillars connected to the high surface height electrical connection portion has a surface height A method for manufacturing a face-down bonding semiconductor device smaller than the diameter of a pillar connected to an electrical connection part having a low height.

When a resist pattern having openings having different diameters is formed on a substrate and plating is performed, the supply of a fresh plating solution changes depending on the diameter of the openings, and plating layers having different heights are formed. By using such a plating layer, pillars having different heights can be formed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A flip chip bonding semiconductor device and a method of manufacturing the same according to an embodiment of the present invention will be described below without limitation. It is obvious that a similar technique can be applied to other face-down bonding semiconductor devices.

FIGS. 1A and 1B show a basic embodiment of the present invention. 1A shows a plan view of the semiconductor substrate 11, and FIG. 1B shows a longitudinal sectional view of the flip-chip bonding semiconductor device.

As shown in FIG. 1A, a semiconductor substrate 11
The circuit elements 12 and 13 are formed on the surface of.

As shown in FIG. 1B, these circuit elements 12, 13 have different heights. Surface electrodes 14 and 15 are formed on the surfaces of these circuit elements 12 and 13.

When the insulating substrate 18 on which the wiring electrodes 19 are formed is to be flip-chip bonded to the surface of the semiconductor substrate 11 by using pillars, as shown in FIG. 1B, conductive pillars 16 having different heights are used. 17 must be used. If pillars 16 and 17 having different heights for canceling steps on the surface of the semiconductor substrate are used, the semiconductor substrate 11
The upper surface electrodes 14 and 15 can be flip-chip bonded to the wiring electrodes 19 on the insulating substrate 18.

Hereinafter, how the pillars having different heights are formed and used will be described in more detail.

FIG. 2A is a graph showing a change in the height of a plating layer when a resist mask having an opening is formed on a base surface and plating is performed on an area exposed in the opening. The horizontal axis indicates the diameter D of the opening in μm, and the vertical axis indicates the height of the plating layer in μm.

FIG. 2B schematically shows the structure of the sample used. A seed metal layer 31 is formed on the surface of the insulating substrate 18, and a photoresist layer 32 is applied on the surface. The photoresist layer 32 has a thickness of t by being applied a plurality of times. By performing contact exposure or proximity exposure on the photoresist layer 32, an opening 38 is formed. The openings 38 are designed to have different diameters D.

The plating layer 35 is grown by plating on the seed metal layer 31 covered with the photoresist layer 32 having openings of different diameters D. After removing the resist layer, a sintering process is performed. The height H of the plating layer 35 is measured as a function of the opening diameter D.

As the plating solution, cyan plating solutions having different deposition efficiencies were used. In FIG. 2A, a curve Ha
1 and Ha2 show the results when a cyan plating solution of the trade name Autolonex was used. The curves Hb1 and Hb2 are
The experimental results in the case where a cyan plating solution of trade name Temperex is used are shown. The characteristics can be adjusted by changing the depth of the opening, that is, the thickness of the photoresist layer. Curves Ha1 and Ha2 show characteristics adjusted by changing the thickness of the photoresist. Curve Hb1
And Hb2. The thickness of each resist layer is Ha1: 14 μm, Ha2: 25 μm, Hb1: 2.
0 μm, Hb2: 25 μm.

As is clear from the curves in FIG.
As the diameter D of the opening increases, the height H of the plating layer to be formed rapidly increases at first, and tends to saturate soon. The region where the height H varies with the diameter D can be selected over a fairly wide range by adjusting the thickness of the photoresist. Therefore, when it is desired to obtain plating layers having different heights, a characteristic including a desired height may be selected, and a diameter D that achieves the desired height may be selected on the characteristic curve.

Hereinafter, more specific embodiments will be described. FIG. 3A is a sectional view of a flip-chip bonding semiconductor device using a compound semiconductor chip according to an embodiment of the present invention. The semiconductor substrate 11 is formed of, for example, GaAs, and has a channel layer 21 on the surface. The periphery of the channel layer is surrounded by the semi-insulating region 22. Channel layer 21
A gate electrode 28, a source electrode 27s, and a drain electrode 27d are formed thereon, and a MESFET is formed.
The gate electrode 28 forms a Schottky contact with the channel layer 21, and the source / drain electrodes 27s and 27d form an ohmic contact with the channel layer. Source /
The drain electrodes 27s and 27d have a thickness of, for example, 35 nm.
AuGe layer, Ni layer 11 nm thick, 154 nm thick
Is formed by laminating Au layers.

On the left semi-insulating region 22 of the MESFET, for example, a SiON layer 23 having a thickness of about 240 nm is formed, and a capacitor lower electrode 24 is formed thereon. The capacitor lower electrode 24 has a thickness of, for example, 10 nm.
And a 300 nm-thick Au layer. On the capacitor lower electrode 24, a thickness of about 240 n
An mN SiON layer 25 is formed thereon, and a capacitor upper electrode 26 is formed thereon. Capacitor upper electrode 26
Has a thickness of, for example, about 1
It is formed by stacking a 0 nm Ti layer and an Au layer having a thickness of about 300 nm. According to such a configuration, the source /
A step of about 1 μm occurs between the surface of the drain electrode 27 and the surface of the upper electrode 26 of the capacitor.

The insulating protective layer 2 is formed on the surface of the semiconductor substrate.
9 are formed. An opening exposing a central portion of the electrode surface is formed in the insulating protection layer 29. Surface electrodes 14, 15s, and 15d are formed on the exposed electrode surfaces.

On the insulating substrate 18, wiring electrodes 19c,
19s and 19d are formed. Surface electrodes 14, 15
s, 15d and the conductive pillars 16, 1 having different heights to uniformly connect the wiring electrodes 19c, 19s, 19d.
7s and 17d are used. These conductive pillars may be formed on the insulating substrate 18 or on the semiconductor substrate 11.

FIG. 3B schematically shows a plan configuration of the semiconductor substrate 11. The field effect transistor FE is shown on the right side of the figure.
T is formed, and a capacitor CAP is formed on the left side. A conductive pillar 16 having a small diameter is arranged on the surface electrode 14 of the capacitor. On the surface electrodes 15s and 15d on the source and drain of the FET, conductive pillars 17s and 17d having a large diameter are arranged. Note that the gate electrode 28 is drawn out onto the insulating substrate at a place different from that in FIG.

Transistor FET and capacitor CA
The manufacturing process of the semiconductor substrate 11 on which the P is formed can be performed by a conventionally known method. Next, a method of forming conductive pillars having different heights on an insulating substrate will be described.

FIG. 4A shows a step of forming a photoresist layer 32 having an opening on the insulating substrate 18.

A seed metal layer 31 is formed on an insulating substrate 18 having wiring electrodes (not shown). For example, an Au layer having a thickness of about 100 nm or a stack of a TiW layer having a thickness of about 100 nm and an Au layer having a thickness of about 100 nm are formed. The seed metal layer 31 can be formed by sputtering, vapor deposition, plating, or the like. A photoresist layer 32 is formed on the surface of the seed metal layer 31 using a highly viscous resist material. In order to use the curve Hb2 in FIG. 2A, a photoresist layer is applied twice to form a photoresist layer 32 having a thickness of about 25 μm.

A mask M is arranged on the photoresist layer, and the opening is exposed by contact exposure or proximity exposure. The opening 38 is formed by developing the photoresist layer. Although the case of positive exposure has been described, negative exposure may be performed. In this case, the black and white of the mask are reversed.

The FET and the capacitor C shown in FIG.
In order to absorb the step difference of 1 μm of the AP, a pillar having a height of 19 μm and a pillar having a height of 20 μm will be formed. FIG.
Using the curve Hb2 of (A), the height 19 μm and the height 2
In order to form a 0 μm plating layer, the diameter D of the opening is about 3
It can be seen that 2.3 μmφ and about 34.6 μmφ are sufficient. The diameter of the opening 38 shown in FIG. 4A is designed in this manner.

FIG. 4B shows a step of plating the seed metal layer 31 on the insulating substrate 18. The insulating substrate 18 on which the photoresist layer 32 having openings having different diameters is formed,
It is immersed in the plating solution 33 together with the counter electrode 34. A positive potential is applied to the counter electrode 34 and a negative potential is applied to the seed metal layer 31 on the insulating substrate, and a current of 5.8 A / Wf is passed through the plating solution 33 at 43 ° C. for 133 minutes. At this time, the growth rate of the plating layer is about 0.15 μm / min.

FIG. 4C schematically shows the state of the plating layer thus formed. In the opening for the capacitor, a plating layer 35c having a height of about 19 μm is grown,
Plating layers 35 s and 35 d having a height of about 20 μm grow in the openings corresponding to the source / drain electrodes.

After the formation of the plating layer having the desired height, the photoresist layer 32 is removed as shown in FIG. Thereafter, the seed metal layer 31 other than the pillar-shaped plating layer is removed by ion milling. Thus, the pillar-shaped plating layer 35 having a desired height is formed on the insulating substrate 18.
Can be formed.

As described above, the insulating substrate on which the pillars having the desired height are formed is arranged on the semiconductor substrate 11 and bonded to the surface electrode of the semiconductor substrate, whereby the flip-chip bonding semiconductor device shown in FIG. Can be completed.

Although the case where pillars are formed on an insulating substrate has been described, pillars may be formed on a semiconductor substrate.

FIG. 5 schematically shows a process of forming conductive pillars on the semiconductor substrate 11. On the semiconductor substrate 11, a photoresist layer 36 is applied. As in the above-described resist layer application step, a sufficiently thick photoresist layer 36 is formed by repeating the application a desired number of times. Photoresist layer 36
A mask is arranged thereon, and exposure of a desired pattern is performed by contact exposure or proximity exposure. The surface electrodes 14, 15 are developed by developing the photoresist layer 36.
An opening 38 exposing s and 15d is formed.

Thereafter, similarly to the above-described embodiment, a plating step as shown in FIG.
Pillars 16, 17s and 17d are formed on 5d. After that, the photoresist layer 36 is removed.

FIG. 6 schematically shows a semiconductor device according to another embodiment of the present invention. Insulating substrate 18 on semiconductor substrate 11
Bonding. Pillars 41, 42, 43 whose height gradually decreases are formed on the surface of the peripheral portion of the semiconductor substrate 11. These are the bonding monitor pillars,
A circuit portion is formed in another portion of the semiconductor substrate 11,
Conductive pillars for electrical connection are separately formed on the circuit portion.

For example, it is assumed that the height of the monitor pillar 42 is equal to the height of the pillar required for electrical connection of the circuit portion. The state where the highest pillar 41 is crushed and the next highest pillar 42 is bonded to the insulating substrate 11 is a good state. If the insulating substrate 18 is pushed too much, the lower pillar 43 will also contact the insulating substrate 18.

As described above, a state where two of the three pillars having different heights are connected is a good state. The state where only one pillar is connected is a state where the pushing is insufficient, and the state where all three pillars are connected is an excessively pushed state.

In the semiconductor device manufacturing process, after performing flip chip bonding, the monitor pillar 4
By visually observing the bonding states of 1, 42, and 43, the quality of the bonding can be easily determined. That is, it is possible to easily determine the excess or deficiency of the bonding without flowing a current.

Although the case where the semiconductor substrate has the transistor and the capacitor has been described, this is merely an example and the semiconductor substrate may have any configuration. The semiconductor substrate is not limited to a compound semiconductor substrate. Even if a Si substrate is used, the advantages of face-down bonding such as flip chip bonding can be obtained.

A case has been described where a semiconductor substrate having a step on the surface and an insulating substrate having wiring electrodes formed on the surface are face-down bonded. Face-down bonding is performed between a substrate having a flat surface and a substrate having a step surface. In this case, a similar step can be performed. For example, a compound semiconductor substrate may be flip-chip bonded on a Si substrate.

Although the case in which the substrate on which the resist mask is formed is immersed in a plating solution for electrolytic plating has been described, electroless plating may be used. Other plating methods such as a pad method may be used.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0048]

As described above, according to the present invention,
A semiconductor substrate having a step surface and a substrate having a flat surface can be uniformly flip-chip bonded.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view showing a semiconductor device according to a basic embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a graph showing an experimental result and a configuration of a sample used in the experiment.

FIG. 3 is a sectional view and a plan view showing a more specific embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a plating process according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating a plating process according to another embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a function of a monitor pillar according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 11 semiconductor substrate 12, 13 circuit element 14, 15 surface electrode 16, 17 conductive pillar 18 insulating substrate 19 wiring electrode 21 channel layer 22 semi-insulating region 23, 25 SiON layer 24, 26 capacitor electrode 27s source electrode 27d drain electrode 28 Gate electrode 29 Insulation protection layer 31 Seed metal layer 32 Photoresist layer 33 Plating solution 34 Counter electrode 36 Photoresist layer

Claims (10)

[Claims] 1. A semiconductor substrate having electric connection portions having different surface heights formed on one surface, an insulating substrate having a wiring electrode formed on the surface, and an electric and mechanical connection between the electric connection portion and the wiring electrode. A face-down bonding semiconductor device comprising conductive pillars having different heights to be electrically connected, the conductive pillar having a relatively high pillar having a larger diameter than the relatively low pillar. 2. The semiconductor device according to claim 1, wherein said semiconductor substrate is formed on a surface layer of said one surface and has a surface electrode of a first height, and a second semiconductor element formed on said one surface and higher than a first height.
2. The face-down bonding semiconductor device according to claim 1, further comprising: a circuit element having a surface electrode having a height of about 0.15 mm, and wherein said electric connection portion is said surface electrode. 3. The face-down bonding semiconductor device according to claim 1, wherein said conductive pillar has a diameter of about 60 μm or less. 4. The face-down bonding semiconductor device according to claim 1, further comprising a monitor pillar connected to only one of said semiconductor substrate and said insulating substrate and having a gap between said semiconductor substrate and said insulating substrate. . 5. A step of preparing a semiconductor substrate having electric connection portions having different surface heights formed on one surface, and an insulating substrate having wiring electrodes formed on the surface thereof; and one of the semiconductor substrate and the insulating substrate. On the substrate,
Forming a resist pattern having a plurality of openings having different diameters exposing a part of the conductive surface of the electrical connection part or the wiring electrode; and a conductive part exposed in the plurality of openings on the one substrate. Contacting the conductive surface with a plating solution to form pillars, and a step of face-down bonding one of the substrates on which the pillars are formed and the other substrate, and connecting to an electrical connection portion having a high surface height A method of manufacturing a face-down bonding semiconductor device, wherein a diameter of a pillar to be connected is smaller than a diameter of a pillar to be connected to an electric connection portion having a low surface height. 6. The method of manufacturing a face-down bonding semiconductor device according to claim 5, wherein said step of forming a resist pattern includes a step of applying a resist layer on said one substrate a plurality of times. 7. The method for manufacturing a face-down bonding semiconductor device according to claim 6, wherein the step of forming the resist pattern includes a step of performing contact exposure or proximity exposure on the resist layer applied a plurality of times. 8. The method of manufacturing a face-down bonding semiconductor device according to claim 5, wherein said plating step performs electrolytic plating. 9. The method of manufacturing a face-down bonding semiconductor device according to claim 5, wherein said plating step performs electroless plating. 10. The plating step according to claim 5, further comprising the step of forming monitor pillars having different heights, further inspecting the bonding state of the monitor pillars, and judging the quality of the bonding. Of manufacturing a face-down bonding semiconductor device.