JPH1065507A - Switch circuit and logic circuit - Google Patents

Abstract

(57) [Problem] To provide a switch circuit capable of reducing deterioration of signal amplitude passing through a transfer gate and clearly separating input and output signals. SOLUTION: A first nMOS enhancement type transistor having a source connected to a signal input terminal and a drain connected to a signal output terminal, and a first nMOS enhancement type transistor having a source connected to a control terminal and a drain connected to the first nMOS enhancement type transistor. And a second nMOS enhancement type transistor having a gate connected to a power supply and a body of the first nMOS enhancement type transistor and a body of the second nMOS enhancement type transistor floating. Switch circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a switch circuit and a logic circuit using only an nMOS enhancement type transistor or a pMOS enhancement type transistor as a transfer gate.

[0002]

2. Description of the Related Art A transfer gate is used as a partial circuit of a logic circuit having a pass transistor structure, or as a switch between wires capable of bidirectional propagation.

FIG. 7 is a circuit diagram showing a conventional switch circuit SW0 in a case where a transfer gate is constituted only by nMOS transistors. FIG. 8 is a diagram showing operation waveforms of the conventional switch circuit SW0.

Next, the operation of the conventional switch circuit SW0 will be described. In the switch circuit SW0, when a high-level signal is input to the control terminal c, the input terminal i
When the signal n changes from a low level signal to a high level signal, the potential of the output terminal out rises, and the potential of the transistor TR2 rises while preserving the potential difference applied to the source-gate overlap capacitance of the transistor TR2, Eventually, it exceeds the power supply voltage. Therefore, even if the potential of the output terminal out rises to near the power supply voltage, the transistor TR2 does not turn off.
As shown in (5), the potential of the output terminal out can surely rise to the power supply voltage.

However, if the signal at the control terminal c is changed from a low-level signal to a high-level signal while a high-level signal is being input to the input terminal in, the voltage between the source and the gate is not preserved. The gate potential does not increase. Therefore, in this case, when the output terminal out drops by the threshold voltage from the power supply voltage, the transistor TR2 is turned off, and as shown in FIG. 8A, the potential of the output terminal out can be raised to the power supply voltage. Can not.

On the other hand, when a bulk nMOS transistor in which the potential of the body is fixed to the ground potential is applied to the switch circuit, the decrease in the amplitude of the signal passing through the switch circuit exceeds the threshold voltage due to the body effect. It occurs when encouraged.

The operation when the pMOS transistor is used instead of the nMOS transistor in the above conventional example is the same as the operation in the above conventional example using the nMOS transistor.

[0008]

At a low power supply voltage, the ratio of the threshold voltage to the power supply voltage becomes large, so that the deterioration of the signal amplitude is further increased, which causes a problem in the operation of the circuit. In order to reduce such signal amplitude deterioration,
Even lower threshold transistors must be used.

However, if a transistor having a low threshold value is used as a depletion type transistor, the input / output signals of the switch circuit cannot be separated, and the circuit malfunctions. Therefore, since a depletion type transistor cannot be used, the threshold has a lower limit. That is, in the above-described conventional example, there is a problem that the amplitude of the signal passing through the transfer gate is greatly deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a switch circuit and a logic circuit capable of reducing the deterioration of the amplitude of a signal passing through a transfer gate and clearly separating input and output signals.

[0011]

According to the present invention, there is provided a first nMOS enhancement type transistor having a source connected to a signal input terminal and a drain connected to a signal output terminal, and a source controlled by the first nMOS enhancement type transistor. Connected to the terminal,
A second nMOS enhancement transistor having a drain connected to a gate of the first nMOS enhancement transistor and having a gate connected to a power supply, a body of the first nMOS enhancement transistor and a second nMOS transistor; This is a switch circuit in which the body of the enhancement transistor is floating.

The invention according to claims 4 to 6 is the invention according to claims 1 to 3.
In the described invention, a pMOS enhancement transistor is used in place of the nMOS enhancement transistor.

According to a seventh aspect of the present invention, there is provided a logic circuit using the first aspect of the present invention as a transfer gate, wherein a threshold voltage of the first and second transistors is one of transistors included in the logic circuit. The logic circuit is smaller than the threshold voltages of the transistors other than the first and second transistors.

According to an eighth aspect of the present invention, there is provided a logic circuit using the fourth aspect of the invention as a transfer gate, wherein a threshold voltage of the first and second transistors is one of the transistors constituting the logic circuit. The logic circuit is smaller than the threshold voltages of the transistors other than the first and second transistors.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing a switch circuit SW1 according to one embodiment of the present invention.

The switch circuit SW1 includes a first nMOS enhancement type transistor TR11 and a second nM
OS enhancement type transistor TR12. First nMOS enhancement type transistor T
R11 has its source connected to the signal input terminal in,
The gate is connected to the drain of the second nMOS enhancement type transistor TR12, and the drain is connected to the signal output terminal out. Also, the second n
The source of the MOS enhancement transistor TR12 is connected to the control terminal c, the gate is fixed to the power supply voltage VDD, and the bodies of the nMOS enhancement transistors TR11 and TR12 are floating. Note that the control terminal c is a control terminal that controls on / off of the switch circuit SW1.

Next, the operation of the switch circuit SW1 will be described.

First, the control terminal c is set to a high level to turn on the switch circuit SW1, and the control terminal c is set to a low level to turn it off. Switch circuit S
When a high level signal is propagated with W1 turned on,
First nMOS enhancement type transistor TR1
The first gate becomes floating, and the gate-source voltage of the first nMOS enhancement transistor TR11 is maintained at a value equal to or higher than the threshold voltage. As a result, a high-level signal can be propagated without a voltage drop by the threshold voltage, and the transition time is shortened.

In the switch circuit SW1, the transistors TR11, TR constituting the switch circuit SW1
By using the SOI structure 12, a static leak current between the source and the drain can be suppressed. Also,
By making the transistors TR11 and TR12 of the SOI structure fully depleted, while suppressing the body effect,
This makes it possible to lower the threshold voltage, reduce the deterioration of the signal amplitude at the output, and satisfactorily separate the input and output signals of the transfer gate.

FIG. 2 is a diagram showing a switch circuit SW2 according to another embodiment of the present invention.

The switch circuit SW2 includes a first pMOS enhancement transistor TR21 and a second pMO
And an S enhancement type transistor TR22. First pMOS enhancement type transistor T
R21 has its source connected to the signal input terminal in,
The gate is connected to the drain of the second pMOS enhancement transistor TR22, and the drain is connected to the output terminal out. Also, the second pMO
The source of the S enhancement type transistor TR22 is connected to the control terminal c, and the gate is fixed to the ground potential. The bodies of the first and second pMOS enhancement transistors TR21 and TR22 are floating.

Next, the operation of the switch circuit SW2 will be described.

When the switch SW2 is turned on, the control terminal c is maintained at a low level. When the switch SW2 is turned off, the control terminal c is set at a high level. When transmitting a low-level signal with the switch SW2 turned on, the first
The gate of the pMOS enhancement transistor TR21 becomes floating, and the gate-source voltage of the first pMOS enhancement transistor TR21 is maintained at a value equal to or higher than the threshold voltage. Therefore, the low-level signal propagates without the voltage of the threshold voltage dropping, and the transition time is shortened.

In addition, since the transistors TR21 and TR22 forming the switch circuit SW2 have an SOI structure, a static leakage current between the source and the drain can be suppressed. Also, the transistors TR21, TR2
By making SOI 2 a fully depleted SOI structure,
It is possible to lower the threshold voltage while suppressing the effect, reduce the deterioration of the signal amplitude at the output, and satisfactorily separate the input and output signals of the transfer gate.

FIG. 3 is a diagram showing a logic circuit LC according to another embodiment of the present invention.

The logic circuit LC is an embodiment in which the switch circuit SW1 is applied as a transfer gate for carry propagation of a Manchester-carry type full adder.

FIG. 4 is a block diagram showing a logic circuit LCa according to still another embodiment of the present invention.

The logic circuit LCa shown in FIG. 4 is a 4-bit adder, and has the same full adders LC0 and L as the logic circuit LC.
This is an adder using C1, LC2, and LC3. In the logic circuit LCa, the input signals A0, A1, A2, A3,
When B0, B1, B2, and B3 are applied simultaneously, the gate signal (the signal at the control terminal c) of each transfer gate in the full adders LC1, LC2, and LC3 in the second and lower stages is an input signal (the input signal at the input terminal in). ), The signal of the full swing can be passed to the overflow OVF. That is, it is possible to reduce the deterioration of the amplitude of the signal passing through the transfer gate.

The two transistors TR11 and TR12 constituting the switch circuit SW1 used in the logic circuits LC and LCa are constituted by low threshold transistors, and the other parts are constituted by high threshold transistors. Also, two transistors T constituting the switch circuit SW2 used in the logic circuits LC and LCa
R21 and TR22 are composed of low threshold transistors, and the other parts are composed of high threshold transistors. That is, a low threshold transistor is used only for the critical path.

As described above, by using low-threshold transistors only in the critical path portion and using high-threshold transistors in other portions, the same propagation delay time as when all portions are constituted by low-threshold transistors is obtained. The power consumption due to the leakage current during operation can be reduced as compared with the case where all the parts are configured by the low-threshold transistors while maintaining the same.

According to the above embodiment, when the switch circuit SW1 using the nMOS enhancement type transistor is used as a transfer gate, a signal reaching the gate (control terminal c) of the transfer gate is supplied to the input terminal in of the transfer gate. When the signal arrives earlier than the signal input to the (source) and the high-level signal propagates, the gate-source voltage of the nMOS enhancement type transistor that propagates the signal is maintained at or above the threshold voltage. , A switch circuit having a low ON resistance can be realized. Even when a switch circuit SW2 using a pMOS enhancement type transistor is used as a transfer gate, a switch circuit having a low on-resistance and having a low threshold voltage at the time of high-level output is realized as described above. Can be.

Even when the above-mentioned input conditions are not satisfied, the threshold voltage can be reduced by using a fully depleted transistor having an SOI structure of the transfer gate. Therefore, the influence of the drop of the threshold voltage can be reduced as compared with the case of the high threshold voltage.

FIG. 5 shows n having a relatively high threshold voltage.
FIG. 11 is a diagram illustrating a result of calculating a signal applied to an input terminal in and a control terminal c and a signal waveform of an output terminal out by simulation in a switch circuit SW1 using a MOS transistor.

As shown in FIG. 5A, when the signal at the control terminal c arrives later than the signal at the input terminal in, the output terminal out does not rise to the power supply potential. On the other hand, as shown in FIG. 5B, when the signal at the control terminal c arrives earlier than the signal at the input terminal in, the output terminal out is output.
Signal rises to the power supply potential.

FIG. 6 shows n having a relatively low threshold voltage.
FIG. 11 is a diagram illustrating a result of a simulation of a signal applied to an input terminal in and a control terminal c and a signal waveform of an output terminal out in a switch circuit SW1 using a MOS transistor.

When the signal at the control terminal c arrives later than the signal at the input terminal in, a low threshold voltage transistor is used as the transfer gate transistor, so that the high threshold shown in FIG. Compared to
As shown in FIG. 6B, the effect of the voltage drop can be suppressed.

[0037]

According to the present invention, it is possible to reduce the deterioration of the amplitude of the signal passing through the transfer gate and to clarify the input / output separation.

[Brief description of the drawings]

FIG. 1 shows a switch circuit SW according to a first embodiment of the present invention.
FIG.

FIG. 2 shows a switch circuit SW according to a second embodiment of the present invention.
FIG.

FIG. 3 is a diagram illustrating a logic circuit LC according to a third embodiment of the present invention.

FIG. 4 shows a logic circuit L according to a fourth embodiment of the present invention.
It is a figure which shows Ca.

FIG. 5 shows a signal applied to an input terminal in and a control terminal c in a switch circuit SW1 using an nMOS transistor having a relatively high threshold voltage, and an output terminal out.
FIG. 9 is a diagram showing a result of calculating the signal waveform of FIG.

FIG. 6 shows a switch circuit using an nMOS transistor having a relatively low threshold voltage (inset), a signal applied to an input terminal in, a control terminal c, and an output terminal ou.
FIG. 9 is a diagram illustrating a result of calculating a signal waveform of t by simulation.

FIG. 7 shows a conventional switch circuit SW0 in a case where a transfer gate is constituted only by nMOS transistors.
FIG.

FIG. 8 is a diagram showing operation waveforms of the conventional switch circuit SW0.

[Explanation of symbols]

SW1, SW2: switch circuit (transfer gate), TR11: first nMOS enhancement type transistor, TR12: second nMOS enhancement type transistor, TR21: first pMOS enhancement type transistor, TR22: second pMOS enhancement type transistor , LC, LC0 to LC3 ... logic circuit (full adder), LCa ... logic circuit (4-bit adder).

Claims (8)

[Claims] A first nMOS enhancement transistor having a source connected to the signal input terminal and a drain connected to the signal output terminal; a source connected to the control terminal and a drain connected to the first nMOS enhancement type transistor. A second nMOS enhancement transistor connected to the gate of the transistor and having a gate connected to the power supply; a body of the first nMOS enhancement transistor and the second nMOS
A switch circuit, wherein a body of an enhancement transistor is floating. 2. The transistor of claim 1, wherein the first nMOS enhancement type transistor is
The switch circuit, wherein the second nMOS enhancement type transistor is a transistor having an SOI structure. 3. The transistor according to claim 2, wherein the first nMOS enhancement type transistor comprises:
The switch circuit, wherein the second nMOS enhancement type transistor is a fully depleted type. A first pMOS enhancement transistor having a source connected to the signal input terminal and a drain connected to the signal output terminal; a gate connected to the ground potential, a source connected to the control terminal, and a drain connected to the control terminal. Comprises a second pMOS enhancement transistor connected to the gate of the first pMOS enhancement transistor, and a body of the first pMOS enhancement transistor and the second pM
A switch circuit, wherein a body of an OS enhancement type transistor is floating. 5. The transistor according to claim 4, wherein the first pMOS enhancement type transistor is provided.
The second pMOS enhancement type transistor is a transistor having an SOI structure. 6. The first pMOS enhancement type transistor according to claim 5, wherein
The switch circuit, wherein the second pMOS enhancement type transistor is a completely depleted type. 7. A first nMOS enhancement type transistor having a source connected to the signal input terminal and a drain connected to the signal output terminal, a source connected to the control terminal, and a drain connected to the first nMOS enhancement type transistor. A second nMOS enhancement transistor connected to the gate of the transistor and having a gate connected to the power supply, wherein the body of the first nMOS enhancement transistor and the body of the second nMOS enhancement transistor are A logic circuit using a floating switch circuit as a transfer gate, wherein a threshold voltage of the first nMOS enhancement type transistor and a threshold voltage of the second nMOS enhancement type transistor constitute the logic circuit Logic circuits being smaller than the threshold voltage of the transistors other than that of the first nMOS enhancement type transistor and the second nMOS enhancement transistor among the transistors. 8. A first pMOS enhancement type transistor having a source connected to the signal input terminal and a drain connected to the signal output terminal, a gate connected to the ground potential, a source connected to the control terminal, and a drain connected to the control terminal. Has a second pMOS enhancement type transistor connected to the gate of the first pMOS enhancement type transistor, and has a body of the first pMOS enhancement type transistor and the second pMOS enhancement type transistor.
A logic circuit using a switch circuit in which a body of an S enhancement type transistor is floating as a transfer gate, wherein a threshold voltage of the first pMOS enhancement type transistor and a threshold voltage of the second pMOS enhancement type transistor are equal to the logic value. A logic circuit characterized by being smaller than threshold voltages of transistors other than the first pMOS enhancement type transistor and the second pMOS enhancement type transistor among transistors constituting the circuit.