JPH1065541A - A/d converter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an A/D converter circuit for a high speed application with less components. SOLUTION: In the case of encoding high-order bits, a high-order comparison reference potential storage sample-and-hold circuit 10 and a low-order comparison reference potential storage sample-and-hold circuit 11 store respectively a high-order and a low-order comparison reference potential closest to a potential of analog input data, and output voltages from the sample-and-hold circuits are fed to a high potential terminal and a low potential terminal of a comparison reference potential application resistor group 6 in the case of encoding low-order bits so as to reduce the required number of comparators and comparison reference potential application resistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly, to an A / D converter for reducing the number of elements and reducing the chip area.
The present invention relates to a conversion circuit.

[0002]

2. Description of the Related Art Conventionally, an A / D conversion circuit of a parallel comparison system has been used as a high-speed A / D conversion circuit suitable for application in video signal processing and measurement fields. In the parallel comparison type AD conversion circuit, when n bits are configured, 2 ⁿ resistors are connected in series between the power supply and the ground, and a comparison circuit (comparator) for comparing each connection point of the resistors with an input signal is 2 ^{If n} -1 bits are required and higher-order bits are used, there is a problem that the circuit becomes complicated and the chip area increases when an IC is formed. As an improvement of the parallel comparison type A / D conversion circuit, an upper bit is encoded based on a comparison result of an upper bit comparison circuit between a reference potential of a predetermined connection point of a resistor string and an input signal, and based on the encoding result. A series-parallel comparison method in which a switch group connected to a predetermined connection point of a resistor string is selected, a reference potential from the switch group and an input signal encode a comparison result from a lower bit comparison circuit and a lower bit is output. Although there is an A / D conversion circuit, there is a problem that the number of elements becomes very large when the number of high-order bits is increased.
No. 8).

[0003]

As described above, in the conventional high-speed A / D conversion circuit, the parallel comparison method generally requires too many components to realize high resolution accuracy. A comparison method is used. However, the number of components is still large, and it is difficult to achieve high resolution accuracy (for example, in the case of a 16-bit configuration, 510 comparison circuits and 65536 resistors are required).

Incidentally, Japanese Patent Application Laid-Open No. Hei 2-205618 discloses a first reference circuit as shown in FIG. A plurality of resistors (first resistor group) connected between the power supply terminal 14 and the second reference power supply terminal 15, and a plurality of resistors for comparing an analog input signal 18 with a voltage obtained at a connection point of the plurality of resistors. A comparison circuit 17, an encoder 19 for encoding the output of the comparison circuit, a first register 20 and a second register 21 for storing an output signal of the encoder 19, a first and a second register 20,
21, a first reference power supply terminal 1 according to an output signal
As means for switching the voltages applied to the first and second resistors 20 and 21, the second resistor group 22 is connected between the reference voltage Vref and the ground. (A selection circuit 26 for outputting a signal for turning on / off a group of switches for selecting a connection point of the second register 21). There has been proposed an A / D conversion circuit that generates a digital signal of lower bits at an output terminal. However, this method is not practical in terms of accuracy and has a problem that the number of required elements is still large.

The reason is described in the above-mentioned Japanese Patent Application Laid-Open No. 2-205618.
In the method disclosed in the publication, the first resistor group 15 is added in parallel to the second resistor group 22, so that the comparison reference potential to the comparator 16 deviates from a desired value (error occurs). That's because).

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above circumstances, and has as its object to provide a parallel comparison type A / D conversion circuit which performs high-speed conversion with high accuracy and a small number of required elements. Is to provide.

[0007]

In order to achieve the above object, an A / D conversion circuit according to the present invention comprises a first reference power supply terminal,
A plurality of resistor elements connected in series between the second reference power supply terminal, a plurality of comparators for comparing a voltage obtained at a connection point between the plurality of resistor elements and an analog input signal, and an output signal of the comparator; An encoder for encoding, a sample-and-hold circuit for holding an upper-side comparison reference potential and a lower-side comparison reference potential closest to an analog input signal by an output of the encode, and a switch for switching a reference potential given to the sample-and-hold circuit. A switch, a switch for enabling an external reference constant voltage or an output from the sample-and-hold circuit to be supplied to the first reference power supply terminal and the second reference power supply terminal, and a switch for the switch And a control circuit for controlling

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. In a preferred embodiment of the present invention, a plurality of resistance elements (6 in FIG. 1) connected in series between a first reference power supply terminal and a second reference power supply terminal, and a connection point of the plurality of resistance elements , A plurality of comparators (7 in FIG. 1) for comparing the voltage obtained by the above with an analog input signal, an encoder (8 in FIG. 1) for encoding an output signal of the comparator (7 in FIG. 1), Sample and hold circuits (10 and 11 in FIG. 1) for holding the upper comparison reference potential and the lower comparison reference potential closest to the analog input signal by output, and these sample and hold circuits (10 and 11 in FIG. 1) A switch (9 in FIG. 1) for switching the reference potential given to the first and second reference power supply terminals and a reference voltage (2 in FIG. 1) or a sample and hold circuit (FIG. Changeover switch for providing an output from the 10, 11) (SWU in Fig. 1
1, SWL1, SWU2, SWL2) and a control circuit for controlling the switching of these switches (8 in FIG. 1)
And

According to the embodiment of the present invention, in the high-speed parallel comparison A / D conversion circuit, two sample-and-hold circuits provided separately from the sample-and-hold circuit (5 in FIG. 1) for holding input analog data. Circuit (10, 1 in FIG. 1)
1) First, in the upper stage of the upper stage determination step, the upper and lower comparison reference potentials closest to the input analog data are held.

Next, the potentials held by the two sample and hold circuits (10 and 11 in FIG. 1) are supplied to the upper and lower ends of a group of resistors to provide a comparison reference potential for lower bit determination.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Referring to FIG. 1, analog data input to analog data input terminal 1 is held by analog input data holding sample / hold circuit 5 until encoding into a digital value is completed.

The output of the sample and hold circuit 5 for holding analog input data is input to one input terminals of a plurality of comparators 7, and the other input terminals of the plurality of comparators 7 are connected to a reference voltage supply resistor group 6 for comparison. The potential of each connection point is input, the comparison result output signal of the plurality of comparators 7 is input to the encoder / controller 8, the encoded bit output signal is output to the digital signal output terminal 4, and the encoder / controller 8 A plurality of switches respectively connected between the side comparison reference potential holding sample / hold circuit 10 and the lower side reference reference potential holding sample / hold circuit 11 and each connection point of the comparison reference voltage supply resistor group 6 An on / off control signal for the switch 9 for switching the comparison reference potential is output.

The output of the sample hold circuit 10 for holding the upper comparison reference potential and the sample hold circuit 11 for holding the lower comparison reference potential are connected to the switches SWU2 and SWL2.
Are connected to the high-order terminal and the low-order terminal of the reference voltage supply resistor group 6 for comparison.

First, in the first step, the switches SWU1 and SWL1 are closed to the high-potential side terminal of the resistor group 6 for supplying the reference potential, and the reference constant voltage is applied to the VREF input terminal 2.
And a switch 9 for switching the comparison reference potential is set at the low potential side terminal of the comparison reference potential supply resistor group 6 so as to be grounded to GND.

In this state, each of the comparators 7 compares the analog input data held in the analog input data holding sample / hold circuit 5 with the comparison reference potential supply resistor group 6.
And the comparison reference potential supplied by the connection point of
The circuit of the encoder / controller 8 which receives the output of the comparator 7 as input determines the upper bits of the analog input data.

Next, the encoder / controller 8 controls the comparison reference potential changeover switch 9 based on the judgment result of the comparator 7, and the sample hold circuit 10 for holding the upper comparison reference potential and the lower comparison reference potential for holding the lower comparison reference potential. The sample hold circuit 11 holds the upper and lower comparison reference potentials closest to the potential of the analog input data.

Further, the encoder / controller 8
Switch SWU of switch 9 for switching comparison reference potential
2, SWL2 is controlled to provide a comparative reference potential supply resistor group 6
The output of the sample hold circuit 10 for holding the upper-side comparison reference potential and the sample-hold circuit 11 for holding the lower-side comparison reference potential are connected to the high potential side terminal and the low potential side terminal of The comparison reference potential supplied from the connection point of the reference potential supply resistor group 6 is compared, and the lower bit of the analog input data is determined by the circuit of the encoder / controller 8 at the next stage of the comparator 7.

Next, a second embodiment of the present invention will be described.

In the above embodiment, the analog input data is encoded into a digital value by dividing it into two steps. However, the number of steps can be set to an arbitrary number of three or more. In this case, the conversion speed is reduced, but the resolution can be increased even with the same element configuration.

Further, it is possible to vary the resolution while using the same circuit.

[0022]

As described above, according to the present invention,
The following effects are obtained.

(1) The first effect is that the resolution and accuracy are improved.

The reason is that the resistance group for supplying the reference voltage according to the present invention differs from the method described in the above-mentioned JP-A-2-205618 in that the first resistance group is added in parallel to the second resistance group. This is because, in principle, no error occurs in the comparison reference potential supplied to the comparator.

(2) The second effect is that the required area is reduced due to the reduction in the number of elements used.

The reason for this is that only one resistor group is required.
It can be realized with half the number of resistors in the system of JP 2005618.

(3) The third effect is that high resolution is realized.

The reason is that in the present invention, an arbitrary resolution can be realized by dividing the encoding into an arbitrary number of times from the upper bits to the lower bits. Also, this is because the resolution can be varied even with the same circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a conventional A / D conversion circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Analog data input terminal 2 VREF input terminal 3 CLK input terminal 4 Digital data output terminal 5 Sample hold circuit for holding analog input data 6 Resistor group for supplying comparison reference potential 7 Comparator 8 Encoder / controller 9 Switch for switching comparison reference potential 10 Sample hold circuit for holding upper-side comparison reference potential 11 Sample-hold circuit for holding lower-side comparison reference potential 14 First reference power supply terminal 15 Second reference power supply terminal 16 First resistor group 17 Comparison circuit group 19 Encoder 20 First register 21st 2 register 22 second resistor group 26 selection circuit 90 reference voltage generation circuit

Claims (3)

[Claims] 1. A plurality of resistance elements connected in series between a first reference power supply terminal and a second reference power supply terminal, and a voltage obtained at a connection point of the plurality of resistance elements is compared with an analog input signal. A plurality of comparators; an encoder for encoding an output signal of the comparator; a sample and hold circuit for holding an upper comparison reference potential and a lower comparison reference potential closest to the analog input signal by an output of the encoder; A switch for switching a reference potential supplied to the sample and hold circuit; and a switch for supplying an external reference constant voltage or an output from the sample and hold circuit to the first reference power supply terminal and the second reference power supply terminal. An A / D conversion circuit, comprising: a control circuit that controls switching of the switch. 2. A high-order bit is output by encoding a comparison result of a plurality of comparators for comparing an input analog signal with a voltage of a predetermined tap of a resistor string connected between a first reference voltage and a second reference voltage. Setting the first and second reference voltages to upper and lower voltages close to the input analog signal based on the encoding result, encoding a comparison result of the plurality of comparators, and outputting the result as lower bits. A / D conversion circuit characterized by the above-mentioned. 3. The A / D conversion circuit according to claim 1, further comprising a circuit for sampling and holding the analog input signal.