JPH1075251A - ATM switching equipment - Google Patents

Abstract

(57) [Summary] [Problem] There is a problem that a large number of packets being assembled are accumulated in a packet buffer memory of a receiving device, and subsequent cells overflow from the packet buffer memory and are discarded. SOLUTION: A selection control circuit 25a to 25n checks all output queues for the presence or absence of an ATM cell including the end of packet data transferred between ATM communication terminals, and outputs a packet to one or more output queues. A including the end of data
If there is a TM cell, one is selected from the output queue, and the ATM cell is output to the output port from the first ATM cell in the output queue to the ATM cell including the last packet data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchronous Transfer Mode) switching device.

[0002]

2. Description of the Related Art FIG. 19 shows, for example, "ATM Switching System with Bandwidth Control Function", IEICE Transactions BI Vo1. J76-BI No. 11 (19
1993) is a configuration diagram showing a conventional ATM switching device, in which 1 is an ATM switching device, 7a to 7n
Is an input port for receiving ATM cells (hereinafter simply referred to as cells) from another ATM communication device connected to the ATM switching device 1, and 2 is an ATM cell switch for exchanging cells input from the input ports 7a to 7n. ATMs 3a-3n
An output buffer memory unit for holding cells output from the cell switch 2, and 8a to 8n are output buffer memory units 3a.
This is an output port for transmitting cells output from 〜3n.

In the output buffer memory units 3a to 3n, 6aa to 6nm and the like 6 transfer cells output from the ATM cell switch 2 to a logical connection route (hereinafter referred to as a virtual connection) set between ATM communication terminals. Call)
Virtual connection queue (for each
VC queues), 9a to 9n are band control tables for storing information on data transfer bands allocated for each virtual connection between ATM communication terminals, and 4a to 4n are band control circuits. For example, the band control circuit 4a , Periodically selects one of the VC queues 6aa to 6am based on the band information held in the band control table 9a, and extracts cells from the selected VC queues 6aa to 6am.

[0005] 5a to 5n and the like 5 are selection circuits. For example, the selection circuit 5a operates according to the instruction of the band control circuit 4a.
The connection between the C queues 6aa to 6am and the output port 8a is switched. The VC queues 6aa to 6nm are first-in first-out (hereinafter referred to as FIFO) memories provided for each virtual connection.
Logically, all the VC queues 6aa to 6nm may be configured on one common memory so as to operate as a FIFO memory provided for each VC.

Next, the operation will be described. For example, an ATM communication device for transmitting cells (hereinafter referred to as a transmission device) is connected to an input port 7n of the ATM switching device 1, and an ATM communication device for receiving cells (hereinafter referred to as a reception device) is connected to an output port 8a. It is assumed that a virtual connection is set between the transmitting device and the receiving device. The transmitter sets the cell to AT at a rate equal to the pre-allocated band.
It transmits to the M switching device 1. The cell transmitted by the transmitting device is
ATM cell switch 2 is input from input port 7n
Is input to the VC queue corresponding to the virtual connection in the output buffer memory unit 3a, for example, 6aa. The band control circuit 4a selects the VC queue 6aa based on the flowchart described below and operates the selection circuit 5a to transmit the cell from the output port 8a to the receiving device.

FIG. 20 is a flowchart briefly showing the operation of band control circuits 4a to 4n. Hereinafter, the band control circuit 4a will be described as an example. The band control circuit 4a periodically selects one of the VC queues 6aa to 6am, for example, the VC queue 6aa in ascending order of the number assigned to the VC queues 6aa to 6am (step ST10). Hereinafter, this selection procedure is referred to as round robin. Next, the band control circuit 4a refers to the band information stored in the band control table 9a for the selected VC queue 6aa, extracts the number of cells according to the band information from the VC queue 6aa, and transmits the cell from the output port 8a. The selection circuit 5a is operated (step ST11).

In the above description, a case has been described in which the transmitting device connected to the ATM switching device 1 transmits cells to the receiving device connected to the ATM switching device 1 at a rate equal to the band allocated in advance. Next, the transmitting apparatus performs TCP / I communication, which is a communication procedure of the local area network.
Consider a case where packet data such as P (hereinafter simply referred to as a packet) is divided into cells and transmitted within a range of a pre-assigned upper limit speed. The cell receiving operation of the receiving device at that time will be described. The cells constituting the packet received by the receiving device are reassembled into packets on the packet buffer memory. At this time, the first cell and the middle cell constituting the packet are held in the packet buffer memory until the last cell constituting the packet arrives and the packet is assembled. The assembled packet is moved from the packet buffer memory to the main memory, and is processed by a higher-level communication procedure such as TCP / IP. The packet buffer memory is usually a small-capacity memory, and the main memory is a large-capacity memory holding various data such as programs.

[0008]

Since the conventional ATM switching device is configured as described above, the transmitting device divides a packet into cells and transmits the cells within a range of a pre-assigned upper limit speed. , The ATM switching apparatus 1 does not consider the delimitation of packets and, for example, each VC queue 6.
Since the cells belonging to aa to 6am are transmitted fairly, the probability that a cell belonging to a packet of a certain virtual connection arrives at the receiving device in a mixed manner with a cell belonging to a packet of another virtual connection increases. The arrival time interval between the first cell and the last cell to which the cell belongs becomes wider. As a result, there is a problem that many packets in the course of assembling stay in the packet buffer memory of the receiving device, the packet buffer memory becomes empty, and subsequent cells overflow from the packet buffer memory and are discarded. Further, when the transmitting device retransmits a packet due to cell discard, there is a problem that the throughput between the transmitting device and the receiving device is reduced. Further, in order to solve the above-mentioned problem, there is a problem that the capacity of a packet buffer memory built in the receiving device must be increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain an ATM switching device that reduces the capacity of a packet buffer memory of a connected receiving device.

[0010]

According to a first aspect of the present invention, there is provided an ATM switching apparatus, comprising: a selection control circuit for an ATM including an end of packet data transferred between ATM communication terminals for all output queues. If there is an ATM cell including the end of the packet data in one or more output queues as a result of the inspection, one is selected from the output queue, and the first ATM cell in the output queue is selected. The ATM cell is output to the output port up to the ATM cell including the end of the packet data. If there is no ATM cell including the end of the packet data in all the output queues as a result of the inspection, one is selected from all the output queues. , Head A of the output queue
ATM cells are output to output ports from the TM cell to the last ATM cell.

According to the second aspect of the present invention, in the ATM switching apparatus, when there is an ATM cell including the last packet data in one or more output queues, the selection control circuit is arranged in ascending order of the number assigned to the output queue. Then, one is selected from the output queue.

According to a third aspect of the present invention, in the ATM switching apparatus, the selection control circuit includes a step of, when one or more output queues include an ATM cell including the tail of the packet data, from the output queue to the tail of the packet data. The output queue having the largest number of ATM cells including the output queue is selected.

According to a fourth aspect of the present invention, in the ATM switching apparatus, the selection control circuit includes an output queue among the output queues when one or more output queues include an ATM cell including the last packet data. The output queue having the smallest number of ATM cells from the first cell to the ATM cell including the end of the first packet data is selected.

According to a fifth aspect of the present invention, there is provided an ATM switching apparatus comprising: a selection control circuit which, when one or more output queues include an ATM cell including the end of packet data, The presence or absence of an ATM cell including the head of packet data transferred between ATM communication terminals is checked. As a result of the check, A including the end of packet data is checked.
When there is an ATM cell including the head of packet data at the head of all output queues including TM cells, one is selected from the output queue in ascending order of the number assigned to the output queue, and as a result of the inspection, If there is no ATM cell including the head of the packet data at the head of one or more output queues including the ATM cell including the tail of the packet data, one of the output queues is assigned in ascending order of the number assigned to the output queue. Is selected.

According to a sixth aspect of the present invention, in the ATM switching device, when one or more output queues include an ATM cell including the last packet data, one of the output queues is selected. , The top ATM of the output queue
An ATM cell is output to an output port from a cell to an ATM cell including the end of packet data, and an ATM cell including the end of the packet data is included in the output queue. It is a cell.

According to a seventh aspect of the present invention, in the ATM switching apparatus, the selection control circuit selects one of the output queues when one or more output queues include an ATM cell including the last packet data. , The top ATM of the output queue
Outputting an ATM cell from a cell to an ATM cell including the end of packet data to an output port, and outputting an ATM cell including the end of the last packet in the output queue to the ATM cell including the end of the last packet; It is a cell.

According to an eighth aspect of the present invention, in the ATM switching apparatus, when there is no ATM cell including the end of the packet data in all output queues, the selection control circuit performs all the selections in ascending order of the number assigned to the output queue. This is to select one from the output queue.

According to a ninth aspect of the present invention, in the ATM switching apparatus, when there is no ATM cell including the end of the packet data in all output queues, the selection control circuit sets the head of packet data to all output queues. If there is an ATM cell including the head of packet data in all output queues, one is selected from all output queues in ascending order of the number assigned to the output queue. As a result of the inspection, when there is no ATM cell including the head of the packet data in one or more output queues, one is selected from the output queue in ascending order of the number assigned to the output queue. is there.

According to a tenth aspect of the present invention, in the ATM switching apparatus, when there is no ATM cell including the last packet data in all output queues, the selection control circuit selects one from all output queues and outputs the selected data. Every time one cell is taken out of the queue, all output queues are rechecked for the presence or absence of an ATM cell including the end of packet data.
If there is no ATM cell including the end of the packet data in all the output queues, the original output queue is selected again, and as a result of the recheck, there is an ATM cell including the end of the packet data in one or more output queues. In this case, one of the output queues is selected, ATM cells are output to the output port from the top ATM cell of the output queue to the ATM cell including the end of packet data, and all output queues include the end of packet data. After the ATM cells are exhausted, the original output queue is selected again.

According to an eleventh aspect of the present invention, in the ATM switching apparatus, when there is no ATM cell including the last packet data in all output queues, the selection control circuit selects one from all output queues and outputs the selected data. Every time one cell is taken out of the queue, all output queues are rechecked for the presence or absence of an ATM cell including the end of packet data.
If there is no ATM cell including the end of the packet data in all the output queues, the original output queue is selected again, and as a result of the recheck, there is an ATM cell including the end of the packet data in one or more output queues. In this case, one of the output queues is selected, ATM cells are output to the output port from the top ATM cell of the output queue to the ATM cell including the end of packet data, and all output queues include the end of packet data. After the ATM cells are exhausted, the next output queue is selected without returning to the original output queue again.

According to a twelfth aspect of the present invention, in the ATM switching apparatus, the selection control circuit selects one from all output queues in ascending order of the number assigned to the output queue, and sends a packet to the output queue. The presence / absence of an ATM cell including the end of data is checked. If the result of the check indicates that there is an ATM cell including the end of packet data in the output queue,
Outputting an ATM cell from the head ATM cell of the output queue to the ATM cell including the end of the packet data to the output port, and as a result of the inspection, when there is no ATM cell including the end of the packet data in the output queue, ATM from top ATM cell to last ATM cell in output queue
The cell is output to the output port.

According to a thirteenth aspect of the present invention, in the ATM switching apparatus, when the selected output queue includes an ATM cell including the tail of the packet data, the selection control circuit transmits the packet data from the head ATM cell of the output queue to the selected output queue. The ATM cell is output to the output port until the ATM cell including the tail,
And an ATM cell including the end of the packet data is
The output queue is an ATM cell including the end of the first packet.

According to a fourteenth aspect of the present invention, in the ATM switching apparatus, when the selected output queue includes an ATM cell including the tail of the packet data, the selection control circuit transmits the packet data from the top ATM cell of the output queue. The ATM cell is output to the output port until the ATM cell including the tail,
And an ATM cell including the end of the packet data is
The output queue is an ATM cell including the end of the last packet.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 shows A according to Embodiment 1 of the present invention.
FIG. 2 is a configuration diagram showing a TM switching device. In the drawing, reference numeral 20 denotes an ATM switching device, and 7a to 7n receive ATM cells (hereinafter, simply referred to as cells) from other ATM communication devices connected to the ATM switching device 20. The input port 2 is an ATM cell switch for exchanging cells input from the input ports 7a to 7n, and 24 is an ATM cell switch 24 such as 24a to 24n.
This is an output buffer memory unit that holds cells output from.

The output buffer memory units 24a to 24
n, 6aa to 6nm and the like 6 are virtual connection queues (6) for holding cells output from the ATM cell switch 2 for each logical connection route (hereinafter referred to as a virtual connection) set between ATM communication terminals. Output queue: hereinafter referred to as VC queue), 25a to 25n
Reference numeral 25 denotes a selection control circuit.
“a” is for selecting one from the VC queues 6aa to 6am and extracting cells from the selected VC queues 6aa to 6am. 5a to 5n and the like 5 are selection circuits. For example, the selection circuit 5a operates according to an instruction from the selection control circuit 25a.
The connection between the queues 6aa to 6am and the output port 8a is switched. 8a to 8n are output buffer memory units 24a to 24
n is an output port for transmitting cells output from n. Further, similarly to the conventional example, the VC queues 6aa to 6nm are FIFO memories provided for each virtual connection, but logically all VC queues 6aa to 6nm are operated as FIFO memories provided for each VC. It may be configured on one common memory.

FIG. 2 shows output buffer memory sections 24a to 24a.
24 is a detailed H / W configuration diagram showing an N. 24, etc., in which end cells 84a to 84m are end-of-packet cells which are the last cells of packets transferred between ATM communication terminals with respect to input cells. A first EOP identification circuit for identifying a cell (hereinafter, referred to as an EOP), 85a to 85m are second EOP identification circuits for identifying an EOP for cells input from the VC queues 6a to 6m, and 86a to 86m are a second EOP identification circuit. One E
An EOP counter that increments the count value by an instruction from the OP identification circuits 84a to 84m and decrements the count value by an instruction from the second EOP identification circuits 85a to 85m. Reference numeral 82 denotes a VC queue 6a selected by the selection control circuits 25a to 25n. ~ 6
This is a queue pointer register that holds any one of the numbers m.

FIG. 3 is an explanatory diagram showing a relationship between a protocol data unit of an ATM adaptation layer (hereinafter referred to as AAL) type 5 common part, a packet and a cell which are transmitted and received between a transmitting device and a receiving device. It is. 40
Reference numeral 46 denotes an AAL type 5 common part protocol data unit. Reference numeral 46 denotes a payload which is a data storage part of the AAL type 5 common part protocol data unit 40, which stores a packet used by an upper layer protocol. 45 is the protocol of the AAL type 5 common part.
Trailer 44a-44j of data unit 40 is A
This is a protocol data unit of a cell disassembly sublayer obtained by disassembling the payload 46 of the AL type 5 common part, and corresponds to a cell payload. 41a to 41j are cell headers, and 43a to 43j are cells. In particular, cell 4
3a is a Beginning of Packet Cell (hereinafter BOP)
), And the cell 43j is referred to as an EOP in distinction from other cells.

Next, the operation will be described. ATM for transmitting cells to, for example, input port 7n of ATM switching device 20
A communication device (hereinafter, referred to as a transmission device) is connected, an ATM communication device (hereinafter, referred to as a reception device) for receiving cells is connected to the output port 8a, and a virtual connection is set between the transmission device and the reception device. Consider the case. The transmitting device transmits cells at a rate equal to the pre-allocated band to A
The message is transmitted to the TM switching device 20. The cell transmitted by the transmitting device is input from the input port 7n, and is input by the ATM cell switch 2 to a VC queue corresponding to the virtual connection in the output buffer memory unit 24a, for example, a VC queue 6aa. The selection control circuit 25a selects the VC queue 6aa based on the flowchart described below, operates the selection circuit 5a, and transmits the cell from the output port 8a to the receiving device.

FIG. 4 is a flow chart showing the operation of the selection control circuits 25a to 25n and the like 25 included in the output buffer memory section of the ATM switching device. Here, the cell transmission operation in the output buffer memory unit will be described in detail with reference to FIGS. The selection control circuit 25 first initializes the queue pointer register 82 (step ST6).
0). Next, the selection control circuit 25 sets the EOP counter 86
The count values of a to 86m are checked, and all VC queues 6a to
The presence or absence of EOP within 6 m is identified (step ST6).
1). Here, the EOP counter, for example, the EOP counter 86a is composed of the first EOP identification circuit 84a and the second EOP
According to the instruction of the identification circuit 85a, the number of EOPs input to the VC queue 6a is held. For example, when the count value of the EOP counter 86a is 0, the VC queue 6a
Has no EOP and the count value is 1 or more, it indicates that the VC queue 6a has an EOP.

First, as a result of step ST61, one or more VC queues, for example, VC queues 6a to 6c are EO
If there is P (step ST62), the selection control circuit 25
Reads the queue pointer register 82 (step ST63), and selects one of the VC queues 6a to 6c including the EOP, for example, 6a, from the read VC queue number and other conditions (step ST64). Other conditions include, for example, the priority set for each virtual connection, in addition to the condition described in the second embodiment described later. The selection control circuit 25 writes the number of the selected VC queue 6a into the queue pointer register 82 (step ST65). The selection control circuit 25 operates the selection circuit 5 to take out cells in order from the head cell in the selected VC queue 6a to EOP. Selection control circuit 2
5 recognizes that the EOP has been transmitted by the decrease in the count value of the EOP counter 86a (step ST).
66). Here, when there are a plurality of EOPs in the selected VC queue 6a, the EOP is selected under the conditions described in the third embodiment, and cells are taken out until the EOP. EO accordingly
P may be selected and cells may be taken out until the EOP.
When the selection control circuit 25 finishes outputting the cells, the process returns to step ST61 again, and the EOs in all the VC queues 6a to 6m are returned.
Check for the presence of P.

Next, as a result of step ST61, all V
When there is no EOP in the C queues 6a to 6m (step ST
62), the selection control circuit 25 reads the queue pointer register 82 (step ST67) and, based on the read VC queue number and other conditions, stores one of all the VC queues 6a to 6m, for example, the VC queue 6m. Select (step ST68). Other conditions include, for example, the priority set for each virtual connection, in addition to the condition described in the fourth embodiment described later. The selection control circuit 25 writes the number of the selected VC queue 6m into the queue pointer register 82 (step ST6).
9). The selection control circuit 25 operates the selection circuit 5 to take out the cells in order from the first cell to the last cell in the selected VC queue 6m (steps ST70 and ST71). After finishing outputting the cells, the selection control circuit 25 returns to step ST61 again, and checks whether or not there is an EOP in all the VC queues 6a to 6m.

As described above, A according to the first embodiment
By adopting the ATM cell switching method, the TM switching apparatus can transmit cells belonging to one packet to EOP as much as possible without mixing cells belonging to other packets.

Embodiment 2 FIG. AT in Embodiment 1
In the M switching device, when there is an EOP in a plurality of VC queues, the selection control circuit selects one from the VC queues. In the ATM switching device according to the second embodiment,
The selection control circuit selects one from the VC queue according to any one of first to fourth procedures described below.

In the second embodiment, the configuration of the ATM switching device, the configuration of the output buffer memory unit, and the relationship between packets and cells are the same as those in FIGS. 1 to 3 shown in the first embodiment.
In the ATM switching device 20, the selection control circuit 25
Except for the operations a to 25n, the operation of each part is the same as the operation described in the first embodiment.

Next, the operation will be described. First, the first cell transmission operation in the output buffer memory unit according to the second embodiment is described with reference to FIG. 2 and the selection control circuits 25a to 25n.
5 will be described with reference to FIG.
The operation of each step except step ST200 in FIG. 5 is the same operation as the step denoted by the same step number in FIG. As a result of step ST61, EOP is stored in one or more VC queues, for example, VC queues 6a to 6c.
If there is (step ST62), the selection control circuit 25
Reads the queue pointer register 82 (step ST63). For example, assuming that the number of the read VC queue is the number of the VC queue 6a, the number is read from the VC queues 6a to 6c including the EOP by round robin. Then, the VC queue 6b to which a number subsequent to the above is assigned is selected (step ST200).

Next, the second cell transmission operation in the output buffer memory unit according to the second embodiment will be described with reference to FIG. 2 and a flow chart showing the operation of the selection control circuits 25a to 25n and the like 25. Step ST in FIG.
The operation of each step except 201 is the same operation as the step denoted by the same step number in FIG. As a result of step ST61, one or more VC queues, for example, V
When there is an EOP in the C queues 6a to 6c (step ST
62), the selection control circuit 25 reads the queue pointer register 82 (step ST63). The selection control circuit 25 checks the count values of the EOP counters 86a to 86c again. For example, if the number of the read VC queue is the number of the VC queue 6a, the VOP including the EOP is
From the C queues 6a to 6c, a VC queue including the largest number of EOPs, for example, the VC queue 6b is selected from the numbers following the above number (step ST201).

Next, the third cell transmitting operation in the output buffer memory unit according to the second embodiment will be described with reference to FIG. 2 and a flowchart 7 showing the operation of the selection control circuits 25a to 25n and the like 25. Step ST in FIG.
The operation of each step except 202 is the same operation as the step denoted by the same step number in FIG. As a result of step ST61, one or more VC queues, for example, V
When there is an EOP in the C queues 6a to 6c (step ST
62), the selection control circuit 25 reads the queue pointer register 82 (step ST63). The selection control circuit 25, for example, assuming that the number of the read VC queue is the number of the VC queue 6a,
From the queues 6a to 6c,
A VC queue having the smallest number of cells from the head cell of each VC queue to the first EOP cell, for example, 6b is selected (step ST202).

Finally, the fourth cell transmission operation in the output buffer memory unit according to the second embodiment will be described with reference to FIG. 2 and a flowchart FIG. 8 showing the operation of the selection control circuits 25a to 25n and the like 25. Step S in FIG.
The operation of each step excluding step ST223 from T220 is the same operation as the step denoted by the same step number in FIG. As a result of step ST61, EOP is stored in one or more VC queues, for example, VC queues 6a to 6c.
If there is (step ST62), the selection control circuit 25
Reads the queue pointer register 82 (step ST63), and then the selection control circuit 25 checks whether or not the head cell is a BOP with respect to the VC queues 6a to 6c (step ST220). Here, the selection control circuit 25 determines that, in each VC queue, for example, the VC queue 6a, the cell output immediately before from the VC queue 6a is EOP.
And if a cell is currently stored in the VC queue 6a, it is recognized that the head cell of the VC queue 6a is a BOP. As a result of step ST220, when there is a BOP at the head of all the VC queues 6a to 6c including the EOP (step ST221), for example, the step ST221
The number of the VC queue read at 63 is the VC queue 6
Assuming that the number is a, the round robin selects the VC queue 6b to which a number following the number is assigned from the VC queues 6a to 6c (step ST22).
3). As a result of step ST220, one or more of the VC queues 6a to 6c including the EOP, for example, 6a,
6b does not have a BOP at the beginning (step ST22)
1) For example, V read in step ST63
Assuming that the number of the C queue is the number of the VC queue 6a, the VC queues 6a and 6b are
A VC queue 6b to which a number following the above number is assigned is selected (step ST222). Note that any two or three of the second to fourth operations of the selection control circuit shown in the second embodiment may be performed in combination.

As described above, A according to the second embodiment
When selecting one of the VC queues in ascending order of the number assigned to the VC queue, the TM switching device can equally grant the transmission right for each logical connection route. In the case of selecting a VC queue having the largest number of ATM cells including the tail of the VC queue, the transmission right can be preferentially given to a logical connection route with a high load. When selecting the VC queue having the smallest number of ATM cells from the cell to the ATM cell including the end of the first packet data, the number of packets that are remaining in the packet buffer memory of the receiving device and being assembled can be reduced. Further, if there is an ATM cell including the head of packet data at the head of all VC queues including the ATM cell including the tail of packet data, the ATM queue is added to the VC queue. Was the young order of number, select one from the VC queue, A, including the tail end of the packet data
If there is no ATM cell including the head of packet data at the head of one or more VC queues including TM cells, and if one of the VC queues is to be selected in ascending order of the number assigned to the VC queue, the receiving device Thus, there is an effect that the number of packets that are remaining in the packet buffer memory and being assembled can be reduced.

Embodiment 3 AT in Embodiment 1
The M switching device, when there is an EOP in a plurality of VC queues,
The selection control circuit selects one from the VC queue and takes out from the head cell of the selected VC queue to the EOP. In the ATM switching apparatus according to the third embodiment, the selection control circuit In accordance with one of the second procedures, the selected VC queue is fetched from the head cell to the EOP.

In the third embodiment, the configuration of the ATM switching apparatus, the configuration of the output buffer memory unit, and the relationship between packets and cells are the same as those in the first embodiment shown in FIGS. In the ATM switching device 20, the operation of each part except the operation of the selection control circuits 25a to 25n is the same as the operation described in the first embodiment.

Next, the operation will be described. First, the first cell transmission operation in the output buffer memory unit according to the third embodiment will be described with reference to FIG. 2 and the flowchart of FIG. The operation of each step except for steps ST204 and ST205 in FIG. 9 is the same operation as the step denoted by the same step number in FIG. As a result of step ST61, one or more VC queues, for example, VC queues 6a to 6a to
6c has an EOP (step ST62), as in the first embodiment, the selection control circuit 25 returns to step ST6.
The process proceeds from step 3 to step ST65, and selects one of the VC queues 6a to 6c including the EOP, for example, the VC queue 6a. The selection control circuit 25 operates the selection circuit 5 to take out the head cell of the selected VC queue 6a. At this time, the selection control circuit 25 determines whether or not the EOP has been output from the VC queue 6a based on the notification from the second EOP identification circuit 85a. The selection control circuit 25 takes out the head cell of the selected VC queue 6a until receiving the notification. As a result, up to the EOP of the first packet included in the VC queue 6a is output (Steps ST204 and ST20).
5).

Next, the second cell transmitting operation in the output buffer memory unit according to the third embodiment will be described with reference to FIG. 2 and a flowchart 10 showing the operation of the selection control circuits 25a to 25n and the like 25. The operation of each step except step ST206 in FIG.
Is the same operation as the step described with the same step number. As a result of step ST61, when there is an EOP in one or more VC queues, for example, the VC queues 6a to 6c (step ST62), as in the first embodiment, the selection control circuit 25 proceeds from step ST63 to step ST65.
To select one of the VC queues 6a to 6c including the EOP, for example, the VC queue 6a. The selection control circuit 25
By operating the selection circuit 5, the head cell of the selected VC queue 6a is taken out. At that time, the selection control circuit 25
When the count value of the counter 86a becomes 0,
It is determined whether all EOPs have been output from the VC queue 6a. The selection control circuit 25 takes out the head cell of the selected VC queue 6a until the count value becomes zero. As a result, output is performed up to the EOP of the last packet included in the VC queue 6a (steps ST204 and ST204).
6).

The operation of the selection control circuit shown in the third embodiment may be implemented in combination with the operation of the selection control circuit shown in the second embodiment.

As described above, A according to the third embodiment
The TM switching device performs an ATM operation including an end of packet data.
If the cell is an ATM cell including the end of the first packet in the VC queue, the transmission right can be given equally to each logical connection route, and the end of the packet data can be assigned. If the ATM cell including the last packet is the ATM cell including the end of the last packet in the VC queue, there is an effect that the transmission right can be given by giving priority to a high-load logical connection route. .

Embodiment 4 FIG. AT in Embodiment 1
In the M switching device, when there is no EOP in all the VC queues, the selection control circuit selects one from all the VC queues. In the ATM switching device according to the fourth embodiment, the selection control circuit is as follows. According to one of the first and second procedures, one is selected from all the VC queues.

In the fourth embodiment, the configuration of the ATM switching device, the configuration of the output buffer memory unit, and the relationship between packets and cells are the same as those in the first embodiment shown in FIGS. In the ATM switching device 20, the operation of each part except the operation of the selection control circuits 25a to 25n is the same as the operation described in the first embodiment.

Next, the operation will be described. First, a first cell transmission operation in the output buffer memory unit according to the fourth embodiment will be described with reference to FIG. 2 and a flowchart 11 showing operations of the selection control circuits 25a to 25n and the like 25. The operation of each step except step ST210 in FIG. 11 is the same operation as the step denoted by the same step number in FIG. As a result of step ST61,
If there is no EOP in all the VC queues 6a to 6m (step ST62), the selection control circuit 25 reads the queue pointer register 82 (step ST67). For example, the number of the read VC queue is equal to the number of the VC queue 6a. As a number, all the VC queues 6
a to 6m, the number following the above number is assigned to V
The C queue 6b is selected (step ST210).

Next, the second cell transmission operation in the output buffer memory unit according to the fourth embodiment will be described with reference to FIG. 2 and a flowchart 12 showing the operation of the selection control circuits 25a to 25n and the like 25. The operation of each step except step ST211 to step ST214 in FIG. 12 is the same operation as the step denoted by the same step number in FIG. As a result of step ST61, all V
When there is no EOP in the C queues 6a to 6m (step ST
62), the selection control circuit 25 reads the queue pointer register 82 (step ST67). Next, the selection control circuit 25 checks whether or not the head cell is a BOP for all the VC queues 6a to 6m (step ST21).
1). If there is a BOP at the head of all VC queues as a result of step ST211 (step ST212), for example,
Assuming that the number of the VC queue read in step ST67 is the number of the VC queue 6a, the round-robin selects the VC queue 6b to which the number subsequent to the number is assigned from all the VC queues 6a to 6m. (Step ST214). As a result of step ST211, if there is no BOP at the head of each of one or more VC queues, for example, the VC queues 6a to 6c (step ST212), for example, the number of the VC queue read in step ST67 is the VC queue 6a. Assuming that the number is a round robin, a VC queue 6b to which a number subsequent to the number is assigned is selected from the VC queues 6a to 6c (step ST213).

The operation of the selection control circuit shown in the fourth embodiment may be performed in combination with the operation of the selection control circuit shown in the first to third embodiments.

As described above, A according to the fourth embodiment
When there is no ATM cell including the end of the packet data in all the VC queues, the TM switching apparatus selects each one from all the VC queues in ascending order of the number assigned to the VC queue. If the transmission right can be equally assigned to each connection route, and there are ATM cells including the head of the packet data in all the VC queues, one from all the VC queues is assigned in ascending order of the number assigned to the VC queue. Select and ATM that includes the beginning of packet data in one or more VC queues
If there is no cell, and if one of the VC queues is selected in ascending order of the number assigned to the VC queue, there is an effect that the number of packets remaining in the packet buffer memory of the receiving device and being assembled can be reduced.

Embodiment 5 FIG. AT in Embodiment 1
In the M switching device, when there is no EOP in all VC queues, the selection control circuit selects one from all VC queues,
From the first cell to the last cell of the selected VC queue, the selection is performed by the selection control circuit in accordance with one of the first and second procedures described below. The VC cell is extracted from the first cell to the last cell of the VC queue.

In the fifth embodiment, the configuration of the ATM switching device, the configuration of the output buffer memory unit, and the relationship between packets and cells are the same as those in FIGS. 1 to 3 shown in the first embodiment. In the ATM switching device 20, the operation of each part except the operation of the selection control circuits 25a to 25n is the same as the operation described in the first embodiment.

Next, the operation will be described. First, the first cell transmission operation in the output buffer memory unit according to the fifth embodiment will be described with reference to FIG. 2 and a flowchart 13 showing the operation of the selection control circuits 25a to 25n and the like 25. Steps S102 to S102 in FIG.
The operation of each step except T105 is the same operation as the step denoted by the same step number in FIG. As a result of step ST61, EO is stored in all VC queues 6a to 6m.
If there is no P (step ST62), as in the first embodiment, the selection control circuit 25 proceeds from step ST67 to step ST69, and selects one of all the VC queues 6a to 6m,
For example, the VC queue 6a is selected. Selection control circuit 25
Operates the selection circuit 5 to take out the first cell of the selected VC queue 6a (step ST70). The selection control circuit 25 confirms the availability of the VC queue 6a every time one cell is taken out (step ST71). As a result of step ST71, when there is no cell in the VC queue 6a, the selection control circuit 25 returns to step ST61 again, and
Check the presence or absence of EOP within a to 6 m. Step ST7
As a result of 1, if there is a cell in the VC queue 6a, the selection control circuit 25 re-examines the presence or absence of EOP in all the VC queues 6a to 6m (step ST102). Step ST1
02, there is an EOP in one or more VC queues, for example, VC queues 6b and 6c (step ST10).
3) One VC queue, for example, VC queue 6b is selected from VC queues 6b and 6c (step ST104),
By operating the selection circuit 5, cells are taken out in order from the top cell to the EOP in the selected VC queue 6b (step S).
T105). Here, as a condition for selecting a VC queue, the condition described in the second embodiment, such as selecting a VC queue containing the most EOP, may be applied.
The operation from step ST102 to step ST105 is
Repeat for the C queue 6c. Step ST102
As a result, if there is no EOP in all the VC queues (step ST103), the process returns to step ST70 again to take out the head cell of the VC queue 6a.

Next, the second cell transmission operation in the output buffer memory unit according to the fifth embodiment will be described with reference to FIG. 2 and a flowchart FIG. 14 showing the operation of the selection control circuits 25a to 25n and the like 25. The operation of each step except step ST106 in FIG.
This is the same operation as the step described with the same step number in No. 3. As a result of step ST61, all VC queues 6
If there is no EOP in a to 6m (step ST62), as in the first embodiment, the selection control circuit 25 proceeds to step S62.
The process proceeds from T67 to step ST69, where all VC queues 6a
6m, for example, the VC queue 6a. The selection control circuit 25 operates the selection circuit 5 to select the selected VC.
The head cell of the queue 6a is taken out (step ST7).
0). The selection control circuit 25 outputs VC
The availability of the queue 6a is confirmed (step ST71). As a result of step ST71, when there is no cell in the VC queue 6a, the selection control circuit 25 returns to step ST61 again and checks whether or not there is an EOP in all the VC queues 6a to 6m. As a result of step ST71, when there is a cell in the VC queue 6a, the selection control circuit 25 determines that all the VC queues 6a to 6a
The presence or absence of EOP in m is checked again (step ST10).
2). As a result of step ST102, when there is an EOP in one or more VC queues, for example, 6b and 6c (step S102).
T103), one VC queue, for example, the VC queue 6b is selected from the VC queues 6b and 6c (step ST10).
4), the number of the VC queue 6b is written into the queue pointer register 82 (step ST106), and the selection circuit 5 is operated to take out the cells in order from the top cell to the EOP in the selected VC queue 6b (step ST10).
5). Here, as a condition for selecting a VC queue, for example, the VC including the largest number of EOPs described in the second embodiment is used.
Conditions such as selection of a queue may be applied. The selection control circuit 25 does not return to the VC queue 6a again,
Proceeding to T61, the presence or absence of EOP in all the VC queues 6a to 6m is checked. As a result of step ST102, all VCs
If there is no EOP in the queue (step ST103), the process returns to step ST70 again to take out the head cell of the VC queue 6a.

The operation of the selection control circuit shown in the fifth embodiment may be implemented in combination with the operation of the selection control circuit shown in the first to fourth embodiments.

As described above, A according to the fifth embodiment
As a result of the re-examination, if there is an ATM cell including the end of the packet data in one or more VC queues, the TM switching apparatus selects one from the VC queue, and selects the first A of the VC queue.
An ATM cell is output to the output port from the TM cell to the ATM cell including the tail of the packet data. After all the VC queues have no ATM cell including the tail of the packet data, the original VC queue is selected again. If you do
It is possible to reduce the number of packets in the packet buffer memory of the receiving device that are remaining in the assembly process and that all the VCs
If the queue does not return to the original VC queue after the ATM cells including the end of the packet data are lost, the next VC queue is selected. The number of packets in the middle can be reduced, the processing is simple, and there is an effect that it can be configured with simple hardware.

Embodiment 6 FIG. In the sixth embodiment, A
5 shows another form of the TM switching device. In the sixth embodiment, the configuration of the ATM switching device, the configuration of the output buffer memory unit, and the relationship between packets and cells are the same as those in FIGS. 1 to 3 shown in the first embodiment. In the ATM switching device 20, the operation of each part except the operation of the selection control circuits 25a to 25n is the same as the operation described in the first embodiment.

Next, the operation will be described. First, the cell transmission operation in the output buffer memory unit according to the sixth embodiment will be described in detail with reference to FIG. 2 and a flowchart of FIG.

The selection control circuit 25 first initializes the queue pointer register 82 (step ST120).
Next, the selection control circuit 25 sets the queue pointer register 8
2 is read (step ST121). For example, assuming that the number of the read VC queue is the number of the VC queue 6a, all the VC queues 6a to 6c are round robined.
From 6m, a VC queue 6b to which a number following the above number is assigned is selected (step ST122). Next, the selection control circuit 25 writes the number of the selected VC queue 6b into the queue pointer register 82 (step ST12).
3). The selection control circuit 25 refers to the count value of the EOP counter 86b and checks whether there is an EOP in the VC queue 6b (step ST124). Step ST1
As a result of step 24, when there is an EOP in the VC queue 6b (step ST125), the selection control circuit 25 operates the selection circuit 5 to start from the top cell in the selected VC queue 6b.
Cells are taken out in order up to the OP (step ST126).
As a result of step ST124, EO is stored in the VC queue 6b.
If there is no P (step ST125), the selection control circuit 2
5 operates the selection circuit 5 to select the selected VC queue 6b.
The cells are taken out in order from the first cell to the last cell (steps ST127 and ST128). Selection control circuit 25
Returns to step ST121 after reading the cell, and reads the queue pointer register 82.

As described above, A according to the sixth embodiment
The TM switching device selects one from all the VC queues in ascending order of the number assigned to the VC queue, checks the VC queue for the presence or absence of an ATM cell including the end of packet data, and checks the result. , If there is an ATM cell containing the end of the packet data in the VC queue,
From the TM cell to the ATM cell including the end of the packet data, the ATM cell is output to the output port.
If there is no ATM cell containing the end of packet data in the C queue, the last AT cell from the VC queue to the last AT cell
Since the ATM cells are output to the output port up to the M cells, the transmission right can be equally given to each logical connection route.

Embodiment 7 AT in Embodiment 6
In the M switching device, when the selected VC queue has an EOP, the selection control circuit takes out from the head cell of the selected VC queue to the EOP. In the ATM switching device according to the seventh embodiment, the selection control circuit According to one of the following first and second procedures, the selected VC queue is extracted from the head cell to the EOP. In the seventh embodiment, the configuration of the ATM switching apparatus and the relationship between packets and cells are the same as those in FIGS. 1 and 3 described in the first embodiment.
In the ATM switching device 20, the basic cell switching operation except for the operation of the output buffer memory units 24a to 24n is the same as the operation described in the first embodiment.

Next, the operation will be described. First, a first cell transmission operation in the output buffer memory unit according to the seventh embodiment will be described. FIG. 16 is a detailed configuration diagram showing the output buffer memory units 24a to 24n. In the figure, each part has the same function as the part denoted by the same reference numeral in FIGS. 1 and 2 of the first embodiment. . FIG. 16 is different from FIG. 2 in that the first EOP identification circuit and the EOP counter are not included, and the second EOP identification circuits 85a to 85m
The selection control circuit is notified that the EOP has been output from the queues 6a to 6m. Next, FIG. 16 and the selection control circuit 25a
The operation of 25 to 25n will be described with reference to FIG. The operation of each step except for step ST130 and step ST131 in FIG. 17 is the same as the operation described in the sixth embodiment with the same step number in FIG. As a result of step ST124, when there is an EOP in the VC queue, for example, the VC queue 6b (step ST125), the selection control circuit 25 operates the selection circuit 5 until the notification is received from the second EOP identification circuit 85b. The head cell of the queue 6b is taken out. As a result, up to the EOP of the first packet included in the VC queue 6b is output (steps ST130 and ST13).
1).

Next, the second cell transmission operation in the output buffer memory unit according to the seventh embodiment will be described. The detailed configuration of output buffer memory units 24a to 24n is the same as that shown in FIG. 2 shown in the first embodiment. In output buffer memory units 24a to 24n, selection control circuits 25a to 2n
Except for the operation of 5n, the operation of each part is the same as the operation described in the first embodiment. Next, FIG. 2 and the selection control circuit 2
FIG. 18 is a flowchart showing the operations of 25 such as 5a to 25n.
It will be described according to. Step ST132 in FIG.
The operation of each step except for the steps shown in FIG.
This is the same operation as Step 5 described with the same step number in FIG. As a result of step ST124, the VC queue, for example, VC queue 6
If b has an EOP (step ST125), the selection control circuit 25 operates the selection circuit 5 to take out the top cell of the VC queue 6b until the count value of the EOP counter 86b becomes 0. As a result, output is performed up to the EOP of the last packet included in the VC queue 6b (steps ST130 and ST132).

As described above, A according to the seventh embodiment
When there is an ATM cell including the end of the packet data in the selected VC queue, the TM switching apparatus determines the ATM cell including the end of the packet data from the top ATM cell of the VC queue.
When an ATM cell is output to the output port up to the cell and the ATM cell including the end of the packet data is the ATM cell including the end of the first packet in the VC queue, each logical cell is The transmission right can be equally given to each connection route, and the processing is the simplest, and there is an effect that it can be configured with simple hardware. If the ATM cell containing the tail of the packet data is the ATM cell containing the tail of the last packet in the VC queue,
There is an effect that the transmission right can be given by giving priority to a high-load logical connection route.

[0066]

As described above, according to the first aspect of the present invention, the selection control circuit is provided for all output queues in the ATM.
The presence or absence of an ATM cell including the end of packet data transferred between communication terminals is checked. If the result of the check indicates that there is an ATM cell including the end of packet data in one or more output queues, the output queue is checked. And outputs an ATM cell from the head ATM cell of the output queue to the ATM cell including the end of the packet data to the output port. As a result of the check, the output queue includes the end of the packet data in all the output queues When there is no ATM cell, one is selected from all the output queues and the ATM cells are output to the output port from the first ATM cell to the last ATM cell of the output queue. The arrival time interval between the first cell and the last cell belonging to the packet can be shortened. In addition, the number of packets that are remaining in the packet buffer memory of the receiving device and that are being assembled can be reduced, and the packet buffer memory can be used effectively. In addition, it is possible to reduce cell discard due to overflow of a subsequent cell from the packet buffer memory.
Furthermore, when the same cell loss rate is achieved, there is an effect that the mounting capacity of the packet buffer memory of the receiving device can be reduced.

According to the second aspect of the present invention, when one or more output queues include ATM cells including the end of the packet data, the selection control circuit performs the above-described operation in the order of the number assigned to the output queue in ascending order. Since the configuration is such that one is selected from the output queues, it has the same effect as the first aspect of the present invention, and the ATM cell including the last packet data in the output queue as compared with the first aspect of the present invention. In this case, there is an effect that the transmission right can be equally given to each logical connection route.

According to the third aspect of the present invention, when there is an ATM cell including the end of packet data in one or more output queues, the selection control circuit can determine whether the ATM cell includes the end of packet data from the output queue. Since the output queue having the largest number of cells is selected, it has the same effect as the first aspect of the present invention. In addition, compared with the first aspect of the present invention, the end of the packet data is stored in the output queue. When there is an ATM cell including the ATM cell, there is an effect that the transmission right can be given by giving priority to the logical connection path with a high load.

According to the present invention, when one or more output queues include an ATM cell including the tail of packet data, the selection control circuit includes:
Since the output queue having the smallest number of ATM cells from the first cell of the output queue to the ATM cell including the end of the first packet data is selected, the same effect as that of the first aspect of the present invention is obtained. Compared with the first aspect of the present invention, when there is an ATM cell including the last packet data in the output queue, there is an effect that the number of packets that are remaining in the packet buffer memory of the receiving device and are being assembled can be reduced.

According to the fifth aspect of the present invention, when the ATM cell including the tail of the packet data is present in one or more output queues, the selection control circuit is provided for the ATM communication terminal with respect to the head of the output queue. The presence / absence of an ATM cell including the head of packet data transferred between the packets is checked. As a result of the check, the ATM including the head of the packet data is added to the head of all output queues including the ATM cells including the tail of the packet data. If there is a cell, one of the output queues is selected in ascending order of the number assigned to the output queue, and as a result of the inspection, the top of one or more output queues including ATM cells including the tail of packet data is determined. When there is no ATM cell including the head of the packet data, one is selected from the output queue in ascending order of the number assigned to the output queue. It has the same effect as the first aspect of the present invention, and, when compared with the first aspect of the present invention, when there is an ATM cell including the last packet data in the output queue, the packet buffer memory of the receiving apparatus stays. This has the effect of reducing the number of packets during assembly.

According to the present invention, when one or more output queues include an ATM cell including the end of packet data, the selection control circuit selects one of the output queues and outputs the selected ATM cell. An ATM cell is output to an output port from the top ATM cell of the queue to the ATM cell including the end of packet data, and the ATM cell including the end of the packet data is output from the end of the first packet in the output queue. Since it is configured to be an ATM cell including a tail, it has the same effect as the invention of claim 1, and
Compared with the first aspect of the present invention, when there is an ATM cell including the end of the packet data in the output queue, the transmission right can be equally imparted to each logical connection route.

According to the seventh aspect of the present invention, when there is an ATM cell including the end of packet data in one or more output queues, the selection control circuit selects one of the output queues and outputs the selected ATM cell. An ATM cell is output to an output port from the top ATM cell of the queue to the ATM cell including the end of packet data, and the ATM cell including the end of the packet data is output to the end of the last packet in the output queue. Since it is configured to be an ATM cell including a tail, it has the same effect as the invention of claim 1, and
Compared with the first aspect of the invention, when there is an ATM cell including the end of the packet data in the output queue, there is an effect that the transmission right can be given by giving priority to a logical connection path with a high load.

According to the eighth aspect of the present invention, the selection control circuit controls the output queue including the end of the packet data in all output queues.
When there is no TM cell, one is selected from all output queues in ascending order of the number assigned to the output queue, so that the present invention has the same effect as the invention of claim 1 and also has the same effect as in claim 1. Compared with the invention of the first aspect, when there is no ATM cell including the end of the packet data in all output queues, there is an effect that the transmission right can be equally assigned to each logical connection route.

According to the ninth aspect of the present invention, the selection control circuit controls the output queue including the end of the packet data in all output queues.
If there is no TM cell, all output queues are checked for the presence of ATM cells including the head of packet data, and as a result of the check, if there are ATM cells including the head of packet data in all output queues, the output queue is checked. One is selected from all the output queues in ascending order of the number assigned to the output queue, and as a result of the inspection, if there is no ATM cell including the head of the packet data in one or more output queues, the number assigned to the output queue is Since one of the output queues is selected in the younger order, it has the same effect as the first aspect of the present invention, and has the same effect as the first aspect of the present invention. When there is no ATM cell including the tail, there is an effect that it is possible to reduce the number of packets that are remaining in the packet buffer memory of the receiver and being assembled.

According to the tenth aspect of the present invention, when there is no ATM cell including the end of the packet data in all the output queues, the selection control circuit selects one from all the output queues, and selects one from the output queue. Every time a cell is taken out, all output queues are re-examined for the presence of ATM cells containing the end of packet data, and as a result of the re-examination, there is no ATM cell containing the end of packet data in all output queues , Again selecting the original output queue, and as a result of the retest,
When there is an ATM cell including the end of packet data in one or more output queues, one is selected from the output queue and the ATM cells are selected from the top ATM cell of the output queue to the ATM cell including the end of packet data. Is output to the output port, and after the ATM cells including the tail of the packet data are lost in all the output queues, the original output queue is selected again, so that the same effect as the invention of claim 1 is obtained. AT that includes the end of packet data in all output queues as compared with the first embodiment.
When there is no M cell, there is an effect that the number of packets that are remaining in the packet buffer memory of the receiver and being assembled can be reduced.

According to the eleventh aspect of the present invention, when there is no ATM cell including the end of the packet data in all output queues, the selection control circuit selects one from all output queues, and selects one from the output queue. Every time a cell is taken out, all output queues are re-examined for the presence of ATM cells containing the end of packet data, and as a result of the re-examination, there is no ATM cell containing the end of packet data in all output queues , Again selecting the original output queue, and as a result of the retest,
When there is an ATM cell including the end of packet data in one or more output queues, one is selected from the output queue and the ATM cells are selected from the top ATM cell of the output queue to the ATM cell including the end of packet data. Is output to the output port, and after all the output queues have no ATM cells including the end of the packet data, the next output queue is selected without returning to the original output queue again. In addition to having the same effect as the first aspect of the present invention, when there is no ATM cell including the last packet data in all output queues compared to the first aspect of the present invention, the packet buffer memory of the receiving apparatus is stagnated. There is an effect that the number of packets on the way can be reduced. Further, as compared with the tenth aspect, the processing is simple, and there is an effect that it can be configured with simple hardware.

According to the twelfth aspect of the present invention, the selection control circuit selects one from all the output queues in ascending order of the number assigned to the output queue, and
The presence / absence of an ATM cell including the tail of the packet data is checked. If the result of the check indicates that there is an ATM cell including the tail of the packet data in the output queue, the end of the packet data is read from the head ATM cell of the output queue. A including
ATM cells up to the TM cell are output to the output port. If there is no ATM cell including the end of the packet data in the output queue as a result of the inspection, the first AT of the output queue is output.
Since the configuration is such that the ATM cells from the M cell to the last ATM cell are output to the output port, the same effect as that of the first aspect of the present invention is obtained, and the first to eleventh aspects are provided.
As compared with the invention of the third aspect, there is an effect that the transmission right can be equally imparted to each logical connection route.

According to the thirteenth aspect of the present invention, when the selected output queue includes an ATM cell including the end of the packet data, the selection control circuit determines whether or not the selected output queue has a head A of the output queue.
An ATM cell is output to an output port from the TM cell to the ATM cell including the tail of the packet data, and the ATM cell including the tail of the packet data includes the tail of the first packet in the output queue. Since it is configured to be an ATM cell, it has the same effect as the invention of claim 12 and the effect that transmission rights can be equally imparted to each logical connection route as compared with the invention of claim 12. There is. Further, as compared with the inventions of claims 1 to 12,
The simplest processing has the effect of being able to be configured with simple hardware.

According to the fourteenth aspect of the present invention, when the selected output queue includes an ATM cell including the end of the packet data in the selected output queue, the selection control circuit may determine whether the selected output queue has a head A of the output queue.
An ATM cell is output to an output port from a TM cell to an ATM cell including the end of packet data, and the ATM cell including the end of the packet data includes the end of the last packet in the output queue. Since it is configured to be an ATM cell, it has the same effect as the invention of claim 12, and also gives a transmission right by giving priority to a logical connection path with a higher load compared to the invention of claim 12. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an ATM switching device according to Embodiment 1 of the present invention.

FIG. 2 is an H / W configuration diagram of an output buffer memory unit in the ATM switching device according to the first embodiment of the present invention.

FIG. 3 shows an AAL type 5 common part protocol transmitted and received between ATM communication devices according to the first embodiment of the present invention.
FIG. 4 is an explanatory diagram showing the relationship between data units, packets, and cells.

FIG. 4 is a flowchart showing an operation of a selection control circuit in the ATM switching device according to the first embodiment of the present invention.

FIG. 5 is a flowchart showing an operation of a selection control circuit in the ATM switching device according to the second embodiment of the present invention.

FIG. 6 is a flowchart showing an operation of a selection control circuit in an ATM switching device according to a second embodiment of the present invention.

FIG. 7 is a flowchart showing an operation of a selection control circuit in the ATM switching device according to the second embodiment of the present invention.

FIG. 8 is a flowchart showing an operation of a selection control circuit in the ATM switching device according to the second embodiment of the present invention.

FIG. 9 is a flowchart showing an operation of a selection control circuit in an ATM switching device according to a third embodiment of the present invention.

FIG. 10 is a flowchart showing an operation of a selection control circuit in an ATM switching device according to Embodiment 3 of the present invention.

FIG. 11 is a flowchart showing an operation of a selection control circuit in an ATM switching device according to a fourth embodiment of the present invention.

FIG. 12 is a flowchart showing an operation of a selection control circuit in an ATM switching device according to a fourth embodiment of the present invention.

FIG. 13 is a flowchart showing an operation of a selection control circuit in an ATM switching device according to a fifth embodiment of the present invention.

FIG. 14 is a flowchart showing an operation of a selection control circuit in an ATM switching device according to a fifth embodiment of the present invention.

FIG. 15 is a flowchart showing an operation of a selection control circuit in an ATM switching device according to Embodiment 6 of the present invention.

FIG. 16 is an H / W configuration diagram of an output buffer memory unit in an ATM switching device according to a seventh embodiment of the present invention.

FIG. 17 is a flowchart showing an operation of the selection control circuit in the ATM switching device according to the seventh embodiment of the present invention.

FIG. 18 is a flowchart showing an operation of a selection control circuit in an ATM switching device according to a seventh embodiment of the present invention.

FIG. 19 is a configuration diagram showing a conventional ATM switching device.

FIG. 20 is a flowchart showing the operation of a band control circuit in a conventional ATM switching device.

[Explanation of symbols]

2 ATM cell switch, 6aa-6nm, 6a-6m
VC queue (output queue), 7a-7n input port, 8a-8n output port, 20 ATM switching equipment,
25, 25a to 25n Selection control circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) The inventor, Manabu Terauchi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) The inventor Kazuki Odaka 2-3-2, Marunouchi, Chiyoda-ku, Tokyo (72) Inventor ▲ or ▼ Kazuyuki Shima 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Sanishi Electric Co., Ltd.

Claims (14)

[Claims] A plurality of input ports for receiving ATM cells, an ATM cell switch for exchanging ATM cells input to the plurality of input ports, and a method for logically connecting ATM cells output from the ATM cell switches. A plurality of output queues held for each path, a selection control circuit for selecting one output queue and extracting ATM cells from the selected output queue, and a plurality of output ports for transmitting ATM cells extracted from the output queue Wherein the selection control circuit inspects all output queues for the presence or absence of an ATM cell including the end of packet data transferred between ATM communication terminals, and as a result of the inspection, When there is an ATM cell including the end of packet data in one or more output queues, one is selected from the output queue and the output queue is selected. The ATM cell is output to the output port from the first ATM cell of the packet to the ATM cell including the end of the packet data, and as a result of the inspection, if there is no ATM cell including the end of the packet data in all the output queues, the entire output queue is output. Of the output queue, and
An ATM switching device for outputting ATM cells from an M cell to the last ATM cell to an output port. 2. When one or more output queues include ATM cells including the end of packet data, a selection control circuit selects one of the output queues in ascending order of the number assigned to the output queue. 2. The ATM switching device according to claim 1, wherein: 3. The selection control circuit, when there is an ATM cell including the end of packet data in one or more output queues, the output queue having the largest number of ATM cells including the end of packet data from the output queue. 2. The ATM switching device according to claim 1, wherein said ATM switching device is selected. 4. When one or more output queues include an ATM cell including the end of the packet data, the selection control circuit determines the end of the first packet data from the head cell of the output queue in the output queue. 2. The ATM switching device according to claim 1, wherein an output queue having the smallest number of ATM cells up to the ATM cell including the following is selected. 5. When one or more output queues include an ATM cell including the end of packet data, a selection control circuit determines a packet data transferred between ATM communication terminals with respect to a head of the output queue. The presence or absence of the ATM cell including the head is checked. As a result of the check, at the head of all output queues including the ATM cell including the tail of the packet data,
If there is an ATM cell including the head of the packet data, one is selected from the output queue in ascending order of the number assigned to the output queue, and as a result of the inspection, one including the ATM cell including the tail of the packet data is selected. 2. The method according to claim 1, wherein, when there is no ATM cell including the head of the packet data at the head of one or more output queues, one is selected from the output queue in ascending order of the number assigned to the output queue.
An ATM switching device as described. 6. The selection control circuit, when there is an ATM cell including the end of packet data in one or more output queues, selects one from the output queue, and selects a packet data from a head ATM cell of the output queue. A including the tail of
An ATM cell that outputs an ATM cell up to a TM cell to an output port, and the ATM cell including the end of the packet data is the ATM cell including the end of the first packet in the output queue.
The ATM switching device according to any one of claims 1 to 5, wherein the ATM switching device is a cell. 7. When one or more output queues include an ATM cell including the end of packet data, the selection control circuit selects one of the output queues, and selects a packet data from a head ATM cell of the output queue. A including the tail of
An ATM cell which outputs an ATM cell up to a TM cell to an output port, and the ATM cell including the end of the packet data is the ATM cell including the end of the last packet in the output queue.
The ATM switching device according to any one of claims 1 to 5, wherein the ATM switching device is a cell. 8. The selection control circuit selects one of all output queues in ascending order of the number assigned to the output queue when there is no ATM cell including the end of the packet data in all output queues. The ATM switching device according to any one of claims 1 to 7, wherein 9. When all output queues do not have ATM cells including the end of packet data, the selection control circuit checks all output queues for the presence of ATM cells including the head of packet data. As a result, when there are ATM cells including the head of packet data in all output queues, one is selected from all the output queues in ascending order of the number assigned to the output queue, and as a result of the inspection, one or more output queues are output. If there is no ATM cell containing the head of packet data in the queue,
8. The ATM switching device according to claim 1, wherein one of the output queues is selected in ascending order of the number assigned to the output queue. 10. When there is no ATM cell including the end of packet data in all output queues, the selection control circuit selects one from all output queues, and every time one cell is taken out of the output queue, all output queues are selected. In response to this, the presence or absence of an ATM cell including the end of the packet data is re-examined, and as a result of the re-examination, if there is no ATM cell including the end of the packet data in all the output queues, the original output queue is selected again. As a result of the recheck, if there is an ATM cell including the end of the packet data in one or more output queues, one is selected from the output queue and the first AT of the output queue is selected.
It outputs ATM cells from the M cell to the ATM cell including the tail of the packet data to the output port, and selects the original output queue again after all the output queues have no ATM cells including the tail of the packet data. The ATM according to any one of claims 1 to 9, characterized in that:
Exchange equipment. 11. The selection control circuit, when there is no ATM cell including the end of packet data in all output queues, selects one from all output queues and every time one cell is taken out from the output queue, all output queues are selected. In response to this, the presence or absence of an ATM cell including the end of the packet data is re-examined, and as a result of the re-examination, if there is no ATM cell including the end of the packet data in all the output queues, the original output queue is selected again. As a result of the recheck, if there is an ATM cell including the end of the packet data in one or more output queues, one is selected from the output queue and the first AT of the output queue is selected.
From the M cell to the ATM cell including the tail of the packet data, the ATM cell is output to the output port. After the ATM queue including the tail of the packet data is lost in all the output queues, the ATM cell does not return to the original output queue again, and The ATM switching apparatus according to any one of claims 1 to 9, wherein the output queue in the order of (1) is selected. 12. A plurality of input ports for receiving ATM cells, an ATM cell switch for exchanging ATM cells input to the plurality of input ports, and a method for logically connecting ATM cells output from the ATM cell switches. A plurality of output queues held for each path, a selection control circuit for selecting one output queue and extracting ATM cells from the selected output queue, and an ATM extracted from the output queue
In an ATM switching apparatus having a plurality of output ports for transmitting cells, the selection control circuit selects one from all output queues in ascending order of the number assigned to the output queue, and Checking whether there is an ATM cell including the end of the packet data; and, as a result of the check, if there is an ATM cell including the end of the packet data in the output queue, from the head ATM cell of the output queue to the end of the packet data. ATM cells up to the ATM cell including the tail are output to the output port. As a result of the inspection, if there is no ATM cell including the tail of the packet data in the output queue, the ATM cell from the head ATM cell of the output queue to the last ATM cell is output.
An ATM switching device for outputting an ATM cell to an output port up to the cell. 13. The selection control circuit outputs an ATM cell from a head ATM cell of the output queue to an ATM cell including the tail of the packet data when the selected output queue includes an ATM cell including the tail of the packet data. A that outputs to the port and includes the end of the packet data
13. The ATM switching device according to claim 12, wherein the TM cell is an ATM cell including the end of the first packet in the output queue. 14. The selection control circuit, when there is an ATM cell including the end of packet data in the selected output queue, outputs the ATM cell from the top ATM cell of the output queue to the ATM cell including the end of packet data. A that outputs to the port and includes the end of the packet data
13. The ATM switching device according to claim 12, wherein the TM cell is an ATM cell including the end of the last packet in the output queue.