JPH1075253A - Atm cell synchronism establishing system utilizing multilevel orthogonal amplitude modulation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce costs by reducing circuit scale for establishing the synchronism of ATM cells. SOLUTION: This system is provided with a plurality of symbol/8-bit converting parts 22 for converting symbol data 20 sent out of a multi-level orthogonal amplitude modulation part and provided with a plurality of bits to 8-bit parallel data 26 provided with a plurality of patterns, a plurality of synchronizing detecting parts 23 for detecting synchronization respectively while regarding the 8-bit parallel data 26 provided with the plurality of patterns as ATM cells and for outputting a control signal 28 corresponding to the contents of synchronization detection, discriminating part 25 for inputting the plurality of control signals 28 and generating an external control signal 29, and selection part 24 for selecting the 8-bit parallel data of any pattern out of the 8-bit parallel data 26 of the plurality of patterns while using the external control signal 29, and for sending these data to an ATM cell reception circuit part as an ATM cell 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system for transferring ATM cells, and more particularly to an ATM cell synchronization establishment system.

[0002]

2. Description of the Related Art As an example of the prior art, Japanese Patent Laid-Open Publication No.
There is an invention of a carrier recovery circuit for multilevel amplitude modulation described in Japanese Patent No. 8459. The invention described in the above publication discloses a carrier recovery circuit for A / D converting a multi-level amplitude modulation signal.

In a conventional communication system for transferring ATM cells using multi-level quadrature amplitude modulation, an ATM
The cell synchronization establishment method is not specified. In a communication system for transferring ATM cells using multi-level quadrature amplitude modulation, a method of converting symbol data after multi-level quadrature amplitude demodulation into 1-bit serial data (hereinafter referred to as one column data) and using the same. And using the symbol data as it is.

[0004]

In a conventional communication system for transferring ATM cells utilizing multi-level quadrature amplitude modulation, when symbol data is converted into one column of data and used, data synchronization is detected. Although it is possible to perform the conversion by the conventional technique, there is a problem that the frequency for performing the conversion process is increased, and the circuit scale is increased.

When the symbol data is used as it is, there is a problem that the conventional synchronous detection function using the symbol data as it is has low versatility, becomes a special function in the ATM communication, and increases the cost. .

An object of the present invention is to reduce the circuit scale for establishing ATM cell synchronization and reduce the cost.

[0007]

In order to achieve the above-mentioned object, an ATM cell synchronization establishing system using multi-level quadrature amplitude modulation according to the present invention comprises an ATM cell transmitting circuit (11) and 8-bit parallel data converted to symbol data. 8 bits to convert to
Symbol converter (12) and multi-level quadrature amplitude modulator (13)
A multi-level quadrature amplitude demodulation section (15) and an ATM cell receiving circuit section (17), and a communication network between the multi-level quadrature amplitude modulation section (13) and the multi-level quadrature amplitude demodulation section (15). A multi-bit quadrature amplitude demodulation section (15) transmits symbol data (20) having a plurality of bits to 8-bit parallel data (26) having a plurality of patterns. ), And each of the 8-bit parallel data (26) having the plurality of patterns output from the plurality of symbol / 8-bit converters (22) is converted to an ATM. Assuming that each cell is a synchronous cell,
A plurality of synchronization detectors (23) for outputting a control signal (28) according to the content of the synchronization detection, and the control signal (28) output from each of the plurality of synchronization detectors (23) are inputted. The external control signal (2) input to the selection unit (24)
9), and the external control signal (2)
9), selecting one of the 8-bit parallel data of the plurality of 8-bit parallel data (26) having the plurality of patterns output from the plurality of synchronization detectors (23), and selecting the ATM cell. And a selector (24) for transmitting the signal to the receiving circuit (17).

The ATM cell synchronization establishing system using multi-level quadrature amplitude modulation according to the present invention employs an ATM cell transmission circuit (11) and an 8-bit symbol converter (12) for converting 8-bit parallel data into symbol data. ), Multi-level quadrature amplitude modulator (13), multi-level quadrature amplitude demodulator (15), and A
A full ATM communication system including a TM cell receiving circuit unit (17) and performing data communication between the multi-level quadrature amplitude modulation unit (13) and the multi-level quadrature amplitude demodulation unit (15) via a communication network Wherein the symbol data (20) having a plurality of bits transmitted from the multi-level quadrature amplitude demodulator (15) is converted into 8-bit parallel data (26) having a plurality of patterns.
Symbol / 8-bit conversion unit (22)
And a control signal (28) output from the synchronization detection unit (23) and an external control signal (2) input to the selection unit (24).
9), and the external control signal (2)
9), the plurality of symbol / 8-bit conversion units (2
The selector (24) for selecting any one of the 8-bit parallel data of the 8-bit parallel data (26) having the plurality of patterns output from 2);
Then, the selected 8-bit parallel data output from the selecting section (24) is regarded as an ATM cell (21), synchronization is detected, and the synchronization is transmitted to the ATM cell receiving circuit section (17). The control signal (2
8) and a synchronization detecting section (23) for outputting the same.

In the ATM cell synchronization establishment method using multi-level quadrature amplitude modulation according to the present invention, the method for detecting synchronization is described as follows:
EC (Header Error Check) synchronization detection can be performed.

As described above, since the symbol / 8-bit conversion unit for converting the symbol data into the 8-bit parallel data is used, the synchronization can be easily detected using the conventional general-purpose 8-bit parallel data synchronization detection circuit. Can be performed, and A using multi-level quadrature amplitude modulation
It is possible to shorten the time for establishing TM cell synchronization.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a communication system for transferring ATM cells using multilevel quadrature amplitude modulation according to an embodiment of the present invention.

The communication system shown in FIG. 1 includes an ATM cell transmission circuit unit 11, an 8-bit symbol conversion unit 12,
A multi-level quadrature amplitude modulation section 13, an optical WDM communication network 14, a multi-level quadrature amplitude demodulation section 15, an ATM cell establishing section 16,
The configuration includes a TM cell receiving circuit section 17.
The ATM cell transmitting circuit 11 transmits 8-bit parallel data 18 in the form of an ATM cell, and the 8-bit / symbol converter 12 converts the 8-bit parallel data 18 to convert the symbol data 19 into a multilevel quadrature amplitude modulator. 13. Further, the multi-level quadrature amplitude demodulation unit 15 sends out the symbol data 20, and the ATM cell establishing unit 16 converts the symbol data 20 into an ATM cell 21 in the ATM cell receiving circuit unit 1.
7

In FIG. 1, an ATM cell transmitting circuit 11
The 8-bit parallel data 18 sent from the optical WDM communication network 14 is converted from the ATM cell format into symbol data 19 by the 8-bit / symbol converter 12 and then modulated by the multilevel quadrature amplitude modulator 13. Sent to. Data output from the optical WDM communication network 14 is received by the multi-level quadrature amplitude demodulation unit 15 and demodulated into symbol data 20.
After being converted into the TM cell 21, the ATM cell receiving circuit 17
, The ATM cell 21 is received.

FIGS. 2 and 3 are diagrams showing the configuration of the ATM cell establishing section of the communication system shown in FIG.

The synchronization establishing section shown in FIG. 2 includes a plurality of symbol / 8-bit converting sections 22, a plurality of synchronization detecting sections 23,
The configuration includes a selector unit 24 and a synchronization determination unit 25. Further, a plurality of symbol / 8-bit conversion units 22
Are converted from the symbol data 20 to 8
The bit-parallel data 26 is transmitted, the plurality of synchronization detectors 23 respectively input the plurality of 8-bit parallel data 26, perform synchronization detection, and transmit the data to the selector 24. The plurality of transmitted 8-bit parallel data 26 is input, and one of them is selected. Further, each of the plurality of synchronization detecting sections 23 outputs a control signal 28 and inputs the control signal 28 to the synchronization determining section 25, and the synchronization determining section 25 outputs a selector switching control signal 29 and inputs the same to the selector section 24.

The synchronization establishing section shown in FIG. 3 has a configuration including a plurality of symbol / 8-bit converting sections 22, a selector section 24, a synchronization detecting section 23, and a synchronization determining section 25. Further, each of the plurality of symbol / 8-bit conversion units 22 converts the symbol data 20 and sends out the respective 8-bit parallel data 26, and the selector unit 24 inputs the plurality of 8-bit parallel data 26, and outputs any one of them. Is selected and sent to the synchronization detection unit 23, and the synchronization detection unit 2
Numeral 3 detects the synchronization of the 8-bit parallel data 26 selected by the selector 24. Further, the synchronization detection section 23 outputs a control signal 28 and inputs the control signal 28 to the synchronization determination section 25, and the synchronization determination section 25 outputs a selector switching control signal 29 and inputs the same to the selector section 24.

The outline of the functions shown in FIGS.
Is to select synchronized 8-bit parallel data 26 from the symbol data 20 output from the multi-level quadrature amplitude demodulation unit 15 shown in FIG.

In FIG. 2, the symbol data 20 transmitted from the multi-level quadrature amplitude demodulator 15 includes a plurality of symbol data.
The data is input to the 8-bit conversion unit 22, and a plurality of 8-bit parallel data 2
The 8-bit parallel data 26 is input to the plurality of synchronization detectors 23 assuming that the data is an ATM cell, and is then input to an HEC (Header Error Check).
Synchronization detection and generation of the control signal 28 are performed. And
A plurality of 8-bit parallel data 26 whose synchronization has been detected are input to the selector 24, and the control signal 28
5 is input. In synchronization determination section 25, control signal 2
8, the synchronization of each of the synchronization detectors 23 is determined, a selector switching control signal 29 is generated and input to the selector 24 at the subsequent stage of the synchronization detector 23, and the selector 24 is controlled. In the selector section 24, one of the plurality of 8-bit parallel data 26 detected in synchronization is selected by the selector switching control signal 29, and the AT
The data is input to the ATM cell receiving circuit unit 17 as the M cell 21. With these functions, the symbol data 20 output from the multi-level quadrature amplitude demodulation unit 15 is converted into a plurality of 8-bit parallel data 26, and synchronized 8-bit parallel data is selected.

In FIG. 3, symbol data 20 sent from multi-level quadrature amplitude demodulation section 15 is composed of a plurality of symbol data.
The data is input to the 8-bit conversion unit 22, and a plurality of 8-bit parallel data 2
6 and any one of the data is selected in the selector 24 at the subsequent stage. Thereafter, in the synchronization detecting section 23, the selected 8-bit parallel data 26
Is regarded as an ATM cell and input, and HEC (Head
er Error Check) Synchronous detection and control signal 2
8 is performed. Then, the detected 8-bit parallel data 26 is input to the ATM cell receiving circuit unit 17 as the ATM cell 21, and the control signal 28 is input to the synchronization determination unit 25. In the synchronization determination section 25, the synchronization determination of the synchronization detection section 23 is performed by the control signal 28, and the selector switching control signal 29 is generated.
And the selector 24 is controlled.

The control of the selector 24 will be described. Assume that the selector 24 first selects one of the 8-bit parallel data 26. Post-Synchronization Detector 23
In the case where the synchronization detection result is normal, if the synchronization detection result is normal, the selector switching control signal 29 of the selector unit 24 is immobilized. If the synchronization detection result is abnormal, the selector switching control signal 29 is changed to switch the selector unit 24. Is done,
The data output from the selector 24 is changed to any other 8-bit parallel data 26. With these functions, the symbol data 20 output from the multi-level quadrature amplitude demodulation unit 15 is converted into a plurality of 8-bit parallel data 26.
, And synchronized 8-bit parallel data is selected.

The number of blocks of the plurality of symbol / 8-bit converters 22 shown in FIGS. 2 and 3 is uniquely determined by the symbol data 20 of the multilevel quadrature amplitude modulation.
{(Least common multiple of symbol data value and 8) / (symbol data value)}.

An example of the number of the symbol / 8-bit conversion units 22 will be described below. (1) In the case of 16-level quadrature amplitude modulation, since the symbol data value is 4, the number of blocks of the symbol / 8-bit conversion unit 22 is represented by the following equation (1).

(Least common multiple of 4 and 8) / 4 = 8/4 = 2 blocks (1) (2) In the case of 64-ary quadrature amplitude modulation, the symbol data value is 6, so the symbol is 8 bits. The number of blocks of the conversion unit 22 is represented by the following equation (2).

(Least common multiple of 6 and 8) / 6 = 24/6 = 4 blocks (2) (3) In the case of 128-level quadrature amplitude modulation, the symbol data value is 8, so the symbol is 8 bits. The number of blocks of the conversion unit 22 is represented by the following equation (3).

(Least common multiple of 8 and 8) / 8 = 8/8 = 1 block (3)

[0027]

Next, an embodiment of the present invention will be described with reference to the drawings, using 16-ary quadrature amplitude modulation (hereinafter referred to as 16QAM) of symbol data value 4 as multi-level quadrature amplitude modulation.

FIG. 4 is a diagram showing a 16Q according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a communication system that transfers ATM cells using AM_MODEM, and is a configuration diagram in which the multilevel quadrature amplitude modulation illustrated in FIG. 1 is applied to 16QAM.

The communication system shown in FIG. 4 comprises an ATM cell transmitting circuit 11, an 8-bit / 4-bit converter 42,
16QAM modulation section (hereinafter, 16QAM_MOD)
43), the optical WDM communication network 14, and the 16Q
The configuration includes an AM demodulation unit (hereinafter, referred to as a 16QAM_DEM unit) 45, an ATM cell establishment unit 16, and an ATM cell reception circuit unit 17. Also,
The ATM cell sending circuit 11 sends out the 8-bit parallel data 18 in the form of an ATM cell, and the 8-bit / 4-bit converter 42 converts the 8-bit parallel data 18 and sends out 4-bit parallel data 49, and 16QAM_MOD.
It is sent to the unit 43. Further, the 16QAM_DEM unit 45
Transmits quaternary symbol data, and uses this as 4-bit parallel data 50.
6 sends the 4-bit parallel data 50 as ATM cells 21 to the ATM cell receiving circuit unit 17.

In FIG. 4, an 8-bit / 4-bit conversion unit 42 corresponds to the 8-bit symbol conversion unit 12 shown in FIG. 1, a 16QAM_MOD unit 43 corresponds to the multi-level quadrature amplitude modulation unit 13, and a 16QAM_DEM unit. Numeral 45 corresponds to the multi-level quadrature amplitude demodulator 15 and the 4-bit / 8-bit converter 5
2 corresponds to the symbol / 8-bit conversion unit 22.

In FIG. 4, the ATM cell transmitting circuit 11
The 8-bit parallel data 18 transmitted from the ATM cell is converted by the 8-bit / 4-bit conversion unit 42 from the ATM cell format to the 4-bit parallel data 4 as shown in FIG.
After being converted to 9, the signal is modulated in the 16QAM_MOD unit 43 and transmitted to the optical WDM communication network 14. Light W
Data output from the DM communication network 14 is 16QAM_D
The data is received by the EM unit 45 and demodulated into 4-bit parallel data 50.
After being converted into the cell 21, the ATM cell receiving circuit 17 receives the ATM cell 21.

FIGS. 5 and 6 are diagrams showing the configuration of the ATM cell establishing section of the communication system shown in FIG. Also,
FIG. 5 is a functional diagram in which the multilevel quadrature amplitude modulation shown in FIG. 2 is 16QAM, and FIG. 6 is a functional diagram in which the multilevel quadrature amplitude modulation shown in FIG. 3 is 16QAM.

The synchronization establishing section shown in FIG. 5 includes two 4-bit / 8-bit converting sections 52, two synchronization detecting sections 23,
The configuration includes a selector unit 24 and a synchronization determination unit 25. Also, two 4-bit / 8-bit conversion units 52
Convert the 4-bit parallel data 50 to 8
The two parallel detection units 23 input the 8-bit parallel data 56 and 57, respectively, detect the synchronization, and transmit the same to the selector unit 24. The selector unit 24 outputs the two parallel detection units. The 8-bit parallel data 56 and 57 sent from the controller 23 are input and one of them is selected. Further, the two synchronization detectors 23 each output a control signal 28 to output the synchronization determination unit 25.
And the synchronization determination unit 25 outputs the selector switching control signal 2
9 is output to the selector 24.

The synchronization establishing section shown in FIG. 6 has two 4-bit / 8-bit converting sections 52, a selector section 24, a synchronization detecting section 23, and a synchronization determining section 25. Further, each of the two 4-bit / 8-bit conversion units 52 converts the 4-bit parallel data 50 and sends out 8-bit parallel data 56 and 57, and the selector unit 24 receives the 8-bit parallel data 56 and 57 and One of them is selected and sent to the synchronization detector 23, and the synchronization detector 23 detects the synchronization of one of the 8-bit parallel data 56 and 57 selected by the selector 24. Further, the synchronization detection section 23 outputs a control signal 28 and inputs the control signal 28 to the synchronization determination section 25, and the synchronization determination section 25 outputs a selector switching control signal 29 and inputs the same to the selector section 24.

The outline of the functions shown in FIGS.
Is to select synchronized 8-bit parallel data 56 and 57 from the 4-bit parallel data 50 output from the 16QAM_DEM unit 45 shown in FIG.

In FIG. 5, 16QAM_DEM unit 45
Is transmitted to two 4-bit / 8-bit converters 52, and is converted into two types of 8-bit parallel data 56, 57 in each 4-bit / 8-bit converter 52. Two synchronization detectors 2
3, each of the 8-bit parallel data 56 and 57 is regarded as an ATM cell and is input to the HEC (Hea).
der ErrorCheck) Synchronous detection and control signal 2
8 is performed. Then, the detected 8-bit parallel data 56 and 57 are input to the selector 24, and the control signal 28 is input to the synchronization determiner 25. In the synchronization determination section 25, the synchronization determination of each synchronization detection section 23 is performed by the control signal 28, and the selector switching control signal 2
9 is generated and the selector unit 24 at the subsequent stage of the synchronization detection unit 23 is generated.
And the selector 24 is controlled. In the selector unit 24, one of the 8-bit parallel data 56 and 57 detected in synchronization is selected by the selector switching control signal 29, and the ATM cell 21
The signal is input to the M cell receiving circuit unit 17. With these functions, the 4-bit parallel data 50 output from the 16QAM_DEM unit 45 is converted into two types of 8-bit parallel data 56 and 57, and synchronized 8-bit parallel data is selected.

In FIG. 6, 16QAM_DEM unit 45
Is transmitted to two 4-bit / 8-bit converters 52, and is converted into two types of 8-bit parallel data 56, 57 in each 4-bit / 8-bit converter 52. Subsequent selector unit 2
In step 4, either data is selected. Thereafter, in the synchronization detection unit 23, the selected 8-bit parallel data 56 or 57 is regarded as an ATM cell and input, and the HEC (Header Error Check) is input.
k) Synchronous detection and generation of the control signal 28 are performed. Then, the detected 8-bit parallel data 56 or 57 is converted to the ATM cell 21 as the ATM cell 21 by the ATM cell receiving circuit unit 17.
, And the control signal 28 is input to the synchronization determination unit 25. In the synchronization determination unit 25, the synchronization determination of the synchronization detection unit 23 is performed by the control signal 28, and the selector switching control signal 29 is generated and input to the selector unit 24, thereby controlling the selector unit 24.

The control of the selector 24 will be described. It is assumed that the selector unit 24 first selects the 8-bit parallel data 56. Synchronization detection is performed in the subsequent synchronization detection unit 23. If the synchronization detection result is normal, the selector switching control signal 29 of the selector unit 24 is immobilized. If the synchronization detection result is abnormal, the selector switching control signal 29 is changed. The switching of the selector unit 24 is performed by the
4 is 8-bit parallel data 57
Is changed to With these functions, 16QAM_D
4-bit parallel data 50 output from the EM unit 45
Is converted into two types of 8-bit parallel data 56 and 57, and synchronized 8-bit parallel data is selected.

FIG. 7 is a diagram showing 8-bit / 4-bit conversion of the 8-bit parallel data shown in FIG.
An outline of data when the 8-bit parallel data 18 transmitted from the cell transmission circuit unit 11 is converted into 4-bit parallel data 49 by the 8-bit / 4-bit conversion unit 42 is shown. AT sent from ATM sending circuit 11
The M cell is divided into four bits from the beginning, and the lump of each four bits is A, B, C, ‥‥‥ from the beginning of the ATM cell.

FIG. 8 is a diagram showing 4-bit / 8-bit conversion of the 4-bit parallel data shown in FIG.
Two types of 8-bit parallel data 5 obtained by inverting the 4-bit parallel data 50 sent from the AM_DEM unit 45 every 4 bits in the 4-bit / 8-bit conversion unit 52
6 shows an outline of data in the case of conversion to 6,57. As in FIG. 7, the chunks of 4 bits transmitted from the 16QAM_DEM unit 45 are denoted by A, B, C,.

This 4-bit block is converted by the 4-bit / 8-bit conversion unit 52 to obtain 8-bit parallel data 56.
And the 8-bit parallel data 57 are transmitted. For example, the 4-bit / 8-bit conversion unit 52 selects the 8-bit parallel data 57 based on the initial value, and the result of the synchronization detection of the 8-bit parallel data 57 by the synchronization detection unit 23 in the ATM cell receiving circuit unit 17 is normal. In this case, ATM cells can be transmitted and received without any problem. However, the 4-bit / 8-bit conversion unit 52 selects the 8-bit parallel data 57 based on the initial value, and the result of the synchronization detection of the 8-bit parallel data 57 by the synchronization detection unit 23 in the ATM cell reception detection unit 17 indicates an error. In some cases, the data is changed (inverted) to 8-bit parallel data 56. In the conversion between the 8-bit parallel data 56 and the 8-bit parallel data 57, the data is inverted by changing the selector switching control signal 29 output from the synchronization determination unit 25.

In the present invention, an optical WDM is used as a communication network.
Although a communication network is used, other communication networks can be used.

As a method of detecting synchronization in the synchronization detecting section 23, HEC (Header Error Check) is used.
k) Although synchronization detection is used, other synchronization detection methods can be used.

[0044]

The first effect is that the symbol data is converted into 8-bit parallel data by using a symbol / 8-bit conversion unit for converting the symbol data into 8-bit parallel data before inputting the data to the synchronization detection unit. By regarding the cell as an ATM cell, synchronization can be easily detected, and the cost can be reduced. The reason is that the conventional highly versatile ATM cell synchronization detection circuit can be used as it is.

The second effect is that the synchronization pull-in time is several tens of microseconds and the synchronization pull-in time is required by using HEC synchronization detection as a method of synchronization detection using a symbol / 8-bit conversion unit. That is, the condition can be satisfied, synchronization can be easily established, and the circuit scale can be reduced. The reason is that a circuit (ATM cell establishing unit) for establishing the synchronization of ATM cells can be realized only by the logic of changing the selector switching control signal and converting a plurality of 8-bit parallel data.

Thus, there is an effect that the circuit scale for establishing the ATM cell synchronization can be reduced and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a communication system for transferring ATM cells using multilevel quadrature amplitude modulation according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a synchronization establishing unit of the communication system shown in FIG.

FIG. 3 is a diagram showing a configuration of a synchronization establishing unit of the communication system shown in FIG. 1;

FIG. 4 shows 16QAM_MOD in one embodiment of the present invention.
The figure which shows the structure of the communication system which transfers the ATM cell using EM

FIG. 5 is a diagram showing a configuration of a synchronization establishing unit of the communication system shown in FIG.

6 is a diagram showing a configuration of a synchronization establishing unit of the communication system shown in FIG.

FIG. 7 is a diagram showing 8-bit / 4-bit conversion of the 8-bit parallel data shown in FIG. 4;

FIG. 8 is a diagram showing 4-bit / 8-bit conversion of the 4-bit parallel data shown in FIG. 4;

[Explanation of symbols]

 Reference Signs List 11 ATM cell transmission circuit section 12 8-bit symbol conversion section 13 Multi-level quadrature amplitude modulation section 14 Optical WDM communication network 15 Multi-level quadrature amplitude demodulation section 16 ATM cell establishment section 17 ATM cell reception circuit section 18, 26, 56, 57 8 bit parallel data 19,20 symbol data 21 ATM cell 22 symbol / 8 bit conversion unit 23 synchronization detection unit 24 selector unit 25 synchronization determination unit 28 control signal 29 selector switching control signal 42 8 bit / 4 bit conversion unit 43 16QAM_MOD (module Rate) part 45 16QAM_DEM (demodulation) part 49,50 4-bit parallel data 52 4-bit / 8-bit conversion part

Claims (3)

[Claims] 1. An ATM cell transmitting circuit, an 8-bit symbol converter for converting 8-bit parallel data into symbol data, a multi-level quadrature amplitude modulator, a multi-level quadrature amplitude demodulator, and an ATM cell receiver circuit. A full ATM communication system for performing data communication between the multi-level quadrature amplitude modulator and the multi-level quadrature amplitude demodulator via a communication network, comprising a plurality of bits transmitted from the multi-level quadrature amplitude demodulator; A plurality of symbol / 8-bit conversion units for converting the symbol data into 8-bit parallel data having a plurality of patterns; and a plurality of 8-bit parallel data having the plurality of patterns output from the plurality of symbol / 8-bit conversion units Is regarded as an ATM cell, and respective synchronization detections are performed.
A plurality of synchronization detectors that output control signals according to the content of the synchronization detection, and a determination that the control signals output from each of the plurality of synchronization detectors are input and an external control signal that is input to the selector is generated. And selecting one of the 8-bit parallel data of the plurality of 8-bit parallel data output from the plurality of synchronization detectors using the external control signal and receiving the ATM cell. An ATM cell synchronization establishment method using multi-level quadrature amplitude modulation, comprising: a selection unit for sending to a circuit unit. 2. An ATM cell transmitting circuit, an 8-bit symbol converter for converting 8-bit parallel data into symbol data, a multi-level quadrature amplitude modulator, a multi-level quadrature amplitude demodulator, and an ATM cell receiving circuit are provided. A full ATM communication system for performing data communication between the multi-level quadrature amplitude modulator and the multi-level quadrature amplitude demodulator via a communication network, comprising a plurality of bits transmitted from the multi-level quadrature amplitude demodulator; A plurality of symbol / 8-bit conversion units for converting the symbol data into 8-bit parallel data having a plurality of patterns; a determination unit for receiving a control signal output from the synchronization detection unit and generating an external control signal for input to the selection unit And any one of 8-bit parallel data including the plurality of patterns output from the plurality of symbol / 8-bit conversion units using the external control signal. The selector for selecting 8-bit parallel data of the pattern; and the selected 8-bit parallel data output from the selector is regarded as an ATM cell to perform synchronization detection and perform the AT.
The synchronization detection unit that sends the control signal according to the content of the synchronization detection that is sent to the M cell reception circuit unit,
ATM cell synchronization establishment method using multilevel quadrature amplitude modulation. 3. The method according to claim 1, wherein the synchronization detection method is HEC (Hea).
3. The AT using multi-level quadrature amplitude modulation according to claim 1 or 2, wherein the AT is der error check) synchronization detection.
M cell synchronization establishment method.