JPH1075411A - Gradation display method - Google Patents

Abstract

(57) [Summary] An object of the present invention is to reduce a deterioration in image quality peculiar to gradation display due to a combination of subframes without reducing the number of gradations. SOLUTION: One frame F is n-weighted with luminance.
A floor in which (n ≧ 3) subframes sf1 to sf4 are divided, and the necessity of light emission of a display element is set by line scanning for each subframe such that the luminance of one frame becomes a value corresponding to the gradation level. At the time of the tonal display, among the n sub-frames, for m (1 ≦ m <n) specific sub-frames sf4 selected in descending order of the luminance weight, k (k ≧ 2) fields sf41, 42 And the necessity of light emission of the display element is set in a k-to-1 interlaced scanning format.
For the other sub-frames sf1 to sf3, the necessity of light emission of the display element is set line by line in a non-interlaced scanning format.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a gradation display method suitable for a PDP (Plasma Display Panel).

[0002] The luminance of a display by a PDP depends on the number of discharges per unit time. Therefore, halftone can be reproduced by appropriately setting the number of discharges in one frame for each display element (pixel or subpixel) of the matrix display. Color display is a type of gradation display, and is realized by changing the luminance ratio of three primary colors.

[0003]

2. Description of the Related Art In an AC type PDP of a matrix display type, line-sequential addressing for forming a charged state according to display contents is performed after resetting for uniform charging state, and thereafter, wall charges are used. Sustaining is performed to periodically generate a discharge. If the discharge cycle is shortened, an apparently continuous light emission state can be obtained. Normally, the discharge cycle depending on the frequency of the sustain pulse is constant, and the brightness is determined by the length of the sustain period.

FIG. 8 is a block diagram of a conventional frame. PD
As a gradation display method of P, one frame is composed of a plurality of subframes weighted by the number of discharges, and addressing is performed for each subframe to set the total number of discharges of one frame (intra-frame modulation method). Is widely known. For example, as shown in FIG. 8A, the frame F is divided into four sub-frames sf1 to sf4, and the ratio of the lengths of the sustain periods TS is 1: 2: 4: 8. That is,
So-called "binary weighting" is performed on each of the subframes sf1 to sf4 using a geometric progression having a common ratio of "2". The display period of each of the sub-frames sf1 to sf4 is a reset period TR, an address period TA, and a sustain period TS
Consists of In the example of FIG. 8A, the gradation level is “0” to
Display of 16 gradations of "15" is possible. Note that the frame F is actually composed of 6 to 8 subframes.
The display of four gradations, 128 gradations, or 256 gradations is performed.

[0005] In the method of reproducing the halftone by the combination of the luminance in the sub-frame unit, the flicker between the gray scales and the false contour occur. Inter-gradation flicker is a flicker phenomenon at a specific gradation boundary, and is caused by a large change in a lighting (light emission) sequence. False contour is a phenomenon in which an observer separates and recognizes subframes in a portion where a gradation changes smoothly in a moving image display, and perceives light and shade different from the display content. This is caused by apparent motion that is recognized as motion by continuously chasing moving images that are projected. Especially for skin-colored images,
Color false contours having different colors and luminances occur in portions where the gradation changes smoothly, and the display quality is significantly reduced. The false contour also becomes more remarkable as the change in the lighting sequence increases. For example, 25
In the case of six gradations, relatively between gradation levels 191 and 192, between gradation levels 127 and 128, and between gradation levels 63 and 64 False contours are significant.

Conventionally, a method called a superposition method has been proposed as a gradation display method effective for reducing flicker between gradations and false contours (Japanese Patent Laid-Open No. Hei 7-17543).
No. 9). This is because, as shown in FIG. 8B, among a plurality of subframes sf1 to sf4 obtained by dividing the frame F, a single or a plurality of subframes sf having a relatively large luminance weight.
4 is composed of two divided sub-frames sf4a and sf4b, and the divided sub-frames sf4a and b are arranged so as to be separated from each other in the frame. This is to prevent continuation. In the example of FIG. 8B, the sub-frame sf4 having the maximum luminance in FIG. 8A is divided.

[0007]

The conventional superposition method has a problem that the number of gradations is reduced. That is, by dividing the subframe, the number of times of addressing in the display of one frame increases, and the frame cycle becomes longer. However, in a normal use represented by a television display, since the frame period is specified, the number of times of addressing cannot be increased. In a PDP having 480 or more lines, the time required for one addressing operation is as long as or longer than the longest sustain period. Therefore, it is difficult to compensate for the increased addressing by shortening the sustain. Therefore,
With the division of sub-frames with large luminance weight,
Omission of other sub-frames is inevitable, and reduction of the number of gradations is inevitable.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce a deterioration in image quality peculiar to gradation display by a combination of subframes without reducing the number of gradations.

[0009]

In order to reduce the deterioration of the image quality, a sub-frame having the maximum luminance or a plurality of sub-frames including the sub-frame is divided in the same manner as in the conventional superposition method. That is, a subframe is composed of a plurality of fields. Even if each divided sub-frame is continuous, addressing is inserted between the light-emitting periods of each divided sub-frame, so that the light-emitting periods are effectively dispersed and the image quality is reduced. Is reduced. However, in order to enhance the effect, it is preferable to display the divided subframes at appropriate time intervals. That is, it is desirable that the frame configuration be such that the display periods of the divided sub-frames are not continuous in the frame period.

In order not to reduce the number of gradations, that is, to avoid extending the total addressing time due to the division of the subframes, the divided subframes are addressed in an interlaced scanning format according to the number of divisions. For example, when the image is divided into two, a two-to-one interlaced scanning format in which the screen is scanned at a ratio of one line to two lines is adopted. In 2: 1 interlaced scanning, the number of scanning lines is halved compared to non-interlaced scanning.
The time required for each addressing is halved. Therefore, as a whole, the total addressing time does not change before and after dividing the subframe. Note that, for example, AC
When the reset period is provided immediately before the address period in the type PDP, the frame period is extended by the reset period. However, the reset period is sufficiently shorter than the address period. Extension can be avoided.

In the case of performing interlaced scanning, if attention is paid to one line, the number of times of light emission is reduced to 1 / divided number in comparison with the case of non-interlaced scanning, simply considered.
Therefore, when addressing by interlaced scanning, the same number of lines as the number of subframe divisions of the line to be scanned and the line to be skipped are set as one group.
The display contents of the lines belonging to one set are the same. As a result, it is possible to avoid a decrease in luminance due to interlaced scanning. In a PDP, the light emission intensity of a cell depends on the number of light emitting cells in a screen, and the relationship is usually nonlinear. However, by simultaneously illuminating the cells in the same number of lines as the number of divisions, in the entire subframe including a plurality of fields, the increase / decrease of the luminous intensity of the cells between the fields is offset, and the same as in the case of non-interlaced scanning Brightness can be obtained.

In the case where the interlaced scanning is performed and the display content is made common to a plurality of lines as described above, the display in which the gradation level is inverted at the gradation boundary portion where the presence or absence of light emission of the divided sub-frames differs between fields. Disturbance occurs. In order to reduce the disturbance, when display elements having different gradation levels that cause disturbance are adjacent to each other, the gradation levels of these display elements are unified to the representative level. As the representative level, a maximum value, a minimum value, an average value or the like among the original gradation levels can be adopted. By unifying the gradation levels, at least a large disturbance in which the gradation levels are inverted is eliminated.

In the method according to the first aspect of the present invention, when a screen is displayed by a matrix display device including display elements capable of binary light emission control, n (n ≧ 3) subframes in which one frame is weighted for luminance. And the necessity of light emission of a display element is set by line scanning for each sub-frame so that the luminance of one frame becomes a value corresponding to the gradation level. Of the frames, for m (1 ≦ m <n) specific subframes selected in descending order of luminance weight, each specific subframe is composed of k (k ≧ 2) fields and k to 1 interface The necessity of light emission of the display element is set in the race scan format. At that time, the same setting is performed for each of the k lines in each field. For the other subframes, one line is set in the non-interlace scan format. It is for setting the necessity of emission of the display element.

According to a second aspect of the present invention, k fields corresponding to the same specific subframe are displayed at a time interval from each other. The method according to the third aspect of the present invention is configured such that when the necessity of light emission of the specific sub-frame in the k display elements in the same column is different between k lines forming a group in interlaced scanning, the k lines are set to the k lines. The representative level is calculated based on the gradation levels of the display elements, and for the k display elements, the n sub-frames are set so that the luminance of one frame becomes a value corresponding to the calculated representative level. Is set as to whether or not light emission is required.

[0015]

FIG. 1 is a configuration diagram of a plasma display device 100 according to the present invention. Plasma display device 100
Is an AC type PDP1 which is a matrix type color display device, and a large number of cells (display elements) constituting a screen.
And a drive unit 90 for selectively turning on the light emitting device, which is used as a wall-mounted television receiver, a monitor of a computer system, or the like.

The PDP 1 has a pair of sustain electrodes X and Y
Are surface discharge type PDPs arranged in parallel, and each cell has a sustain electrode X, Y and an address electrode A corresponding to each other.
It has an electrode matrix with an electrode structure. The sustain electrodes X and Y extend in the display line direction, and one of the sustain electrodes Y is used as a scan electrode for selecting a cell for each line at the time of addressing. The address electrodes A are data electrodes for selecting cells in column units, and extend in the column direction.

The drive unit 100 includes a controller 9
1, frame memory 92, data processing unit 93, sub-frame memory 94, data transfer unit 95, X driver circuit 9
6, Y driver circuit 97 and address driver circuit 9
Eight. Multi-valued video data DR, DG, and DB indicating the RGB luminance level (gray level) of each pixel are input to the drive unit 100 from an external device together with various synchronization signals. Video data DR, DG, DB
After being temporarily stored in the frame memory 92, the subframe data R0-3, G0-3,
The data is converted into B0 to B3 and stored in the subframe memory 94. Subframe data R0-3, G0-3, B0
Reference numeral 3 denotes a set of binary data indicating whether or not light emission of cells is required in each subframe obtained by dividing one frame. In the present embodiment, the sub-frame data R0-3, G0-
3, the number of bits of B0 to 3 is 4. That is, the number of divisions of one frame is four, and for each of R, G, and B, “0” to “1”
5 "are possible 16 gray scale brightness setting of 16 ^three-color display according to.

At the time of addressing, the data transfer unit 9
5 reads the sub-frame data R0-3, G0-3, B0-3 from the sub-frame memory 94 line by line and transfers them to the address driver circuit 98. As described later, in the case of non-interlaced scanning, data of all lines is sequentially transferred from the first line, and in the case of interlaced scanning, data of a predetermined number of lines is sequentially transferred. The address driver circuit 98 selectively applies an address pulse to the address electrode A1 according to the transferred sub-frame data R0-3, G0-3, B0-3.
In parallel with this, the Y driver circuit 95 applies a scan pulse to each sustain electrode (scan electrode) Y according to an instruction from the controller. In a sustain period after the addressing, the X driver circuit 96 applies a sustain pulse to all the sustain electrodes X in common, and the Y driver circuit 97 applies a sustain pulse to all the sustain electrodes Y in common. However, the application is performed alternately on the sustain electrodes X and the sustain electrodes Y.

FIG. 2 is a perspective view showing the internal structure of the PDP according to the present invention. On the inner surface of the glass substrate 11 on the front side, a pair of sustain electrodes X and Y are arranged for each line L. The sustain electrodes X and Y each include a transparent conductive film 41 and a metal film 42, and are covered with a dielectric layer 17 for AC driving. Mg is applied to the surface of the dielectric layer 17.
A protective film 18 made of O is deposited. An underlayer 22, an address electrode A,
An insulating layer 24, partition walls 29, and phosphor layers 28R, 28G, 28B of three colors (R, G, B) for color display are provided. Each partition 29 is linear in plan view. These partition walls 29 divide the discharge space 30 in the line direction for each sub-pixel (display element), and the gap size of the discharge space 30 is defined to a constant value. Display 1
The pixel is composed of three sub-pixels arranged in the line direction. Since the arrangement pattern of the partition walls 29 is a stripe pattern, a portion of the discharge space 30 corresponding to each column is continuous in the column direction across all the lines.
The emission colors of the sub-pixels in each column are the same. The structure within each sub-pixel is a cell.

In the PDP 1, the setting (addressing) of lighting (light emission) / non-lighting of the sub-pixels as described above
An address electrode A and a sustain electrode Y are used. That is, screen scanning (line selection) is performed by applying a scan pulse to N (N is the number of lines) sustain electrodes Y, and the sustain electrodes Y and the address electrodes A selected according to the display content are connected to the sustain electrodes Y. A predetermined charge state is formed for each line L by the opposing discharge (address discharge) between the two. At this time, the subframe data R0 to 3 are provided in the column of R, and the subframe data G0 to 3 are provided in the column of G.
However, the subframe data B0 to B3 are applied to the column B. After the addressing, when a sustain pulse having a predetermined peak value is alternately applied to the sustain electrode X and the sustain electrode Y, a surface discharge (sustain discharge) occurs in a cell in which a predetermined amount of wall charge exists at the end of the addressing.

Next, a method of driving the PDP 1 will be described. FIG. 3 is a diagram showing a configuration of a frame. In order to perform gradation display, basically, the frame F is divided into four subframes sf1 to sf4 as shown in FIG. The display period of each of the subframes sf1 to sf4 is a reset period TR,
It consists of an address period TA and a sustain period TS.
Weighting is performed so that the relative ratio of luminance in each of the subframes sf1 to sf4 is 1: 2: 4: 8, and the number of light emission in the sustain period TS of each of the subframes sf1 to sf4 is set. Display of 16 gradations is possible by combining the presence or absence of light emission in subframe units. Each bit of the above-described subframe data R0-3, G0-3, B0-3 indicates the presence or absence of light emission of one subframe. That is, the least significant bit corresponds to subframe sf1, the second bit corresponds to subframe sf2, the third bit corresponds to subframe sf3, and the most significant bit corresponds to subframe sf4.

In order to prevent false contours and flicker between gradations, the sub-frame sf4 having the maximum luminance is composed of two divided sub-frames sf41 and sf42. Subframe s
f4 is a specific subframe in the present invention. FIG.
As shown in (B), sf1 → sf41 → sf3 → sf42 →
The display period of each subframe is arranged in the order of sf2. Thereby, the display of the divided sub-frames sf41 and sf42 is temporally separated. Each divided subframe sf41, sf
The length of the sustain period TS of the subframe sf
4 is almost half the length of the sustain period TS. That is, the luminance weight of each of the divided sub-frames sf41 and sf42 is “2”. It should be noted here that the subframe data R0-3, G0-3, B0-3 are data in subframe units, and
This is commonly applied to f41 and sf42.

When the sub-frame sf4 is divided into two, the number of times of addressing for one frame increases by one. In order to avoid extending the total addressing time, the subframe sf4 is divided into subframes sf41 and sf42.
The addressing is performed in a two-to-one interlaced scanning format in which is a field. In the divided sub-frame sf41, the sub-frame data R0-3, G0-3, B
Lighting presence / absence is set according to 0 to 3, and in the divided subframe sf42, the subframe data R0 to R0 of the even-numbered line is set.
3, lighting on / off is set according to G0-3, B0-3. In addition, in order to compensate for a decrease in luminance due to a decrease in the number of times of light emission of each cell, sub-frame data R0 to R0 for one line
3, G0-3, B0-3 are applied to two lines, and the presence or absence of lighting is set for each two lines. By performing the interlaced scanning, the time required for addressing the entire frame is the same as before the subframe sf4 is divided. In the sub-frames sf1 to sf1 other than the sub-frame sf4 (these frames are usually referred to as sub-frames), addressing is performed in a non-interlaced scanning format. Note that the frame period is extended by one reset in accordance with the division of the subframe sf4. However, this extension is a short time that can be compensated for by a slight shortening of the sustain period TA.

FIG. 4 is a waveform diagram of an applied voltage in a normal subframe, and FIG. 5 is a waveform diagram of an applied voltage in a specific subframe. In FIG. 4, the reset period TR is a period in which wall charges in the effective display region are erased (entirely erased) in order to prevent the influence of the previous lighting state. In response to the rise of the write pulse PW, a strong surface discharge is generated in all lines, and wall charges are temporarily accumulated in the dielectric layer 17. However, in response to the fall of the write pulse PW, so-called self-discharge occurs due to wall charges, and the wall charges of the dielectric layer 17 disappear. The pulse Paw is applied to suppress accumulation of wall charges on the back wall surface of the discharge space 30.

The address period TA is a period in which line-sequential addressing is performed. The sustain electrodes X are biased to the positive potential Vax with respect to the ground potential, and all the sustain electrodes Y are biased to the negative potential Vsc. In this state,
Select each line in order from the top line one by one,
A scan pulse Py of negative polarity is applied to the sustain electrode Y. At the same time as selecting the line, the subframe data R0
A positive address pulse Pa having a peak value Va is applied to the address electrodes A corresponding to the cells to be turned on indicated by 〜3, G0-3, and B0-3. In the selected line, in the cell to which the address pulse Pa is applied, an address discharge occurs between the sustain electrode Y and the address electrode A. Since the sustain electrode X is biased to a potential having the same polarity as the address pulse Pa, the bias cancels the address pulse Pa and no discharge occurs between the sustain electrode X and the address electrode A.

The sustain period TS is a period in which the lighting state set by addressing is maintained in order to secure luminance according to the gradation level. In order to prevent the counter discharge, all the address electrodes A are biased to a positive potential (for example, Vs / 2), and first, a positive sustain pulse Ps having a peak value Vs is applied to all the sustain electrodes Y. Thereafter, the sustain electrode X and the sustain electrode Y
, A positive sustain pulse Ps having a peak value Vs is alternately applied. Each time the sustain pulse Ps is applied, surface discharge occurs in the cell in which the wall charges are accumulated in the address period TA.

The drive sequence of the address period TA differs between the normal subframe and the specific subframe.
That is, in the case of a specific sub-frame, adjacent odd lines and even lines are grouped as shown in FIG. 5, that is, the (2i-1) -th (i = 1, 2,.
3) and the 2i-th line as a set,
Line scanning is performed line by line. In parallel with this, in the case of the divided sub-frame sf41, an address pulse Pa is applied to the address electrode A in accordance with the sub-frame data R0-3, G0-3, B0-3 of the odd-numbered line, and In this case, an address pulse Pa is applied to the address electrode A according to the sub-frame data R0-3, G0-3, B0-3 of the even-numbered line.

FIG. 6 is a diagram for explaining the function of the data processing section 93. In the figure, black circles (●) indicate lighting when addressing is performed line by line in an interlaced scanning format, and white circles (○) indicate subordinate lighting by addressing two lines at a time.

As described above, when the addressing for setting the necessity of lighting every two lines in the interlaced scanning format is performed, the change of the gradation may be disturbed. For example, FIG.
As shown in (A), the cells in the same column from the (2i-1) -th odd line to the (2i + 4) -th even line are set as 10, 9, 8, and
Consider the case where 7, 6, and 5 are given. (2i-
In the 1) th line, since the gradation level is 10,
For example, if the cell of interest is an R cell, the subframe data R0 to R3 require lighting of the subframe sf2 (weight 2) and the subframe sf4 (weight 8). But,
Since the (2i-1) -th line is an odd-numbered line, the sub-frame data R0 to 3 become invalid in the divided sub-frame sf42 corresponding to the even-numbered line. From these facts, the subframe data R of the (2i-1) th line
On the basis of 0 to 3, the (2i-1) -th line and the 2i-th line paired with the (2i-1) -th line in the divided sub-frame sf41 are turned on, and the (2i-th) line is displayed in the sub-frame sf2.
-1) The first line is turned on. On the other hand, since the gradation level of the 2i-th line is 9, the sub-frame data R
0 to 3 request lighting of the subframe sf1 (weight 1) and the subframe sf4 (weight 8). Since the 2i-th line is an even-numbered line, the sub-frame data R0 to R0 in the divided sub-frame sf41 corresponding to the odd-numbered line
3 becomes invalid. From these facts, based on the sub-frame data R0 to 3 of the 2i-th line, the 2i-th line is turned on in the divided sub-frame sf1, and the (2i-1) -th and 2nd in the divided sub-frame sf42.
The ith line lights up. As a result of such addressing, a correct luminance level corresponding to the gradation level can be obtained for the entire frame.

On the other hand, the (2i + 1) -th and (2i
In the (+2) th line, not only the gradation level is different from the luminance level but also the tendency of the change is reversed, so that a remarkable disturbance occurs in a smooth gradation change. This means that, at the gradation level 8, the sub-frame data R0 to 3 requires lighting of the sub-frame sf4 which is the specific sub-frame, whereas at the gradation level 7, the sub-frame data R0 to 3 This is because lighting is not required. That is, it is because the necessity of light emission of the specific sub-frame is different.

Therefore, the data processing unit 93 sets the 2
When the necessity of light emission of a specific sub-frame in a cell in the same column differs between the two lines, a representative level is calculated based on the gray level of the two cells, and the representative level is calculated for the two cells. The sub-frame data R0-3, G0-3, and B0-3 requesting corresponding lighting are generated and output to the address driver circuit 98.

The calculation of the representative level is described in detail in FIG.
(B) As in (C), this is a process of selecting the larger or smaller gradation level of the two cells. Note that the average value of the gradation levels may be used as the representative level.

FIG. 7 is a block diagram of the data processing section 93. The data processing unit 93 includes a buffer 930 for delaying data for one line, a logic circuit 931 for determining whether data conversion is necessary, and a filter 93 for calculating a representative level.
6 and a data selector 937.

The data processing unit 93 includes video data DR0 to DR0 converted to the same bit format as the subframe data.
3, DG0 to 3, DG0 to 3, and DB0 to 3 are input in the order of pixel arrangement. The filter 936 includes video data DR0-3, DG0-3, and DB0 delayed by the buffer 930.
3 and video data DR0-3 and DG0 that are not delayed
, And DB0-3 are input in parallel. That is,
Two lines of video data DR forming a group of interlaced scanning
0-3, DG0-3, and DB0-3 are input simultaneously.

The logic circuit 931 includes a total of three 2-input XOR circuits 9 provided one for each of R, G, and B colors.
32 to 934, and an OR circuit 935 for calculating the logical sum of the outputs of the XOR circuits 932 to 934. Each of the XOR circuits 932 to 934 has video data DR0 to 3 and DG0 to before and after the delay by the buffer 930, respectively.
3, the most significant bits of DB0 to DB3 are input. The most significant bit indicates whether it is necessary to light the sub-frame sf4 having the maximum luminance, which is the specific sub-frame in the present embodiment. J-th (j = 1, 2, 3,...) Of each of two lines forming a set
When the necessity of lighting of the sub-frame sf4 is different among the cells, the output of the OR circuit 935 becomes active.
In this case, the data selector 937 converts the representative level calculated by the filter 936 into the sub-frame data R0.
-3, G0-3, B0-3. OR circuit 9
When the output of the buffer 35 is inactive, the data selector 937 converts the video data DR0-3, DG0-3, and DB0-3 delayed by the buffer 936 into the sub-frame data R0-3, G0-3, B0 Output as 3.

In the above embodiment, the example of 16 gradations has been described, but the number of gradations may be 32, 64, 128, 256 or more. The luminance weight of the sub-frame does not necessarily have to be a binary weight. One subframe may be composed of three or more k divided subframes. In that case, addressing is performed in a k-to-1 interlace format in which each divided subframe is a field. Two or more subframes selected in descending order of luminance from maximum luminance may be divided.

[0037]

According to the first to third aspects of the present invention,
It is possible to reduce deterioration in image quality peculiar to gradation display due to a combination of subframes without reducing the number of gradations.

According to the second aspect of the present invention, it is possible to more reliably reduce the deterioration of the image quality. According to the third aspect of the invention, it is possible to make the gradation reproduction disturbance caused by sharing the display contents of a plurality of lines inconspicuous.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a plasma display device according to the present invention.

FIG. 2 is a perspective view showing an internal structure of a PDP according to the present invention.

FIG. 3 is a diagram showing a configuration of a frame.

FIG. 4 is a waveform diagram of an applied voltage in a normal subframe.

FIG. 5 is a waveform diagram of an applied voltage in a specific subframe.

FIG. 6 is a diagram for explaining a function of a data processing unit.

FIG. 7 is a block diagram of a data processing unit.

FIG. 8 is a configuration diagram of a conventional frame.

[Explanation of symbols]

 1 PDP (matrix display device) F frame sf1 to 4 subframe sf4 Specific subframe sf41 Divided subframe (field) sf42 Divided subframe (field)

Claims (3)

[Claims] When a screen is displayed by a matrix display device comprising display elements capable of binary light emission control, one frame is divided into n (n.gtoreq.3) subframes weighted with luminance, and one frame is divided into n (n.gtoreq.3) subframes. A gradation display method for setting necessity of light emission of a display element by line scanning for each sub-frame so that luminance has a value corresponding to a gradation level, the method comprising: , M (1 ≦ m <n) specific subframes are selected in descending order, each specific subframe is composed of k (k ≧ 2) fields, and the display elements of the display elements are k-to-1 interlaced scanning format. The necessity of light emission is set. At this time, the same setting is performed for each of the k lines in each field. Gradation display method and setting. 2. The k fields corresponding to the same specific sub-frame are displayed at a time interval from each other.
The gradation display method described. 3. The k which forms a set during interlaced scanning
When the necessity of light emission of the specific subframe in the k display elements in the same column differs between the book lines, a representative level is calculated based on the gray level of the k display elements, and 3. The floor according to claim 1, wherein the necessity of light emission in the n subframes is set so that the luminance of one frame has a value corresponding to the calculated representative level for the k display elements. 4. Key display method.