JPH1079407A - Dry etching damage detection device and semiconductor device diagnosis method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device of detecting dry etching damage, capable of monitoring a process with high sensitivity, based on the deterioration of an insulation film in the dry etching process and in an actual device structural state of the device, and a method of diagnosing semiconductor device using them. SOLUTION: A semiconductor device is formed by a metal wire 106 connected to a gate electrode of MOS-type capacitor and a metal wire 110 adjoining the metal wire 106 at a distance less than 1μm and connected to a semiconductor substrate through diode, and a damage to the metal wire 106 caused by the presence of the metal wire 110 is calculated. This enables detecting dry etching damage with high sensitivity and sensitive to process variation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device (dry etching damage detecting device), and more particularly, to a method for monitoring a dry etching process in manufacturing based on an insulating film damage, and a method for monitoring the dry etching process. Provided is a method for diagnosing a MOS semiconductor device, which can prevent deterioration in an etching process at a design stage.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor integrated circuits has been greatly advanced.
With the miniaturization of transistor elements, the thickness of gate insulating films has been reduced. As a result, specifically, 0.
In the 25 μm rule, a thin gate insulating film of 6 to 8 nm is being used.

When manufacturing a semiconductor device having a thin gate insulating film as described above, there is a problem of damage to the gate insulating film occurring during the manufacturing process. Furthermore, the charge injected into the wiring pattern in the dry etching process is increasing with the changes in process conditions such as higher aspect ratio of the wiring pattern due to the miniaturization of devices and furthermore, higher density of plasma. is there. Therefore,
In the dry etching process, the destruction and deterioration of the gate insulating film and the deterioration of the transistor characteristics (threshold voltage fluctuation and saturation current value decrease) caused by the flow of the charge injected into the wiring pattern through the gate insulating film are as follows. However, with miniaturization, it becomes a big problem.

As a conventional technique for solving such a problem, the amount of electric charge injected into a wiring pattern has been minimized by optimizing a process condition in a dry etching process.

[0005]

In optimizing the dry etching process conditions, a technique for quantitatively evaluating the damage is very important. FIG. 10 shows a conventional dry etching damage evaluation.
A TEG (Test
Element Group) is used, and the antenna T
When the antenna length or the antenna aspect ratio of the EG is changed, the evaluation of the change in the characteristic value of the MOS transistor, the reliability life of the gate insulating film, and the like has been performed.

However, such an antenna wiring TEG including only a metal wiring connected to the gate electrode has a problem in terms of its damage detection performance. For example,
When an antenna wiring electrically connected to a semiconductor substrate is adjacent to a gate electrode wiring over a relatively wide area, there is a phenomenon that damage to a transistor is amplified. Such an adjacency between the gate electrode wiring and the wiring electrically connected to the semiconductor substrate is composed of only the conventional gate electrode wiring, despite the fact that the wiring is very frequently present in a wiring layout in an actual device. Antenna T
The evaluation using the EG cannot evaluate the damage caused by such a layout. Therefore, in the method using the conventional antenna TEG, it has been difficult to optimize the process according to the actual device.

Further, it is considered that the damage caused by the wiring electrically connected to the adjacent semiconductor substrate is caused by a local non-uniformity of the plasma potential. Is very susceptible to When the dry etching process is monitored and managed by using the conventional antenna TEG consisting only of the gate electrode wiring, it is used for the monitor even though the damage in the actual device is increased due to the process variation. There is a problem that the damage on the antenna TEG does not fluctuate much.

Accordingly, in view of the above problems, the present invention provides a method for monitoring a dry etching process based on deterioration of a gate insulating film due to charge injection in the dry etching process with high sensitivity and in accordance with an actual device structure. It is an object of the present invention to provide a method for performing the method and a method for diagnosing a wiring layout for preventing deterioration in the dry etching step at a design stage in advance.

[0009]

In order to achieve the above object, there is provided a high-sensitivity dry etching damage detecting device in which a wiring connected to a semiconductor substrate is arranged adjacent to a gate electrode wiring, thereby realizing a practical device. Process optimization and process management assuming the amount of damage of the semiconductor integrated circuit. The present invention provides a technique for diagnosing from the viewpoint of sex deterioration.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments.

According to the present invention, as described above, a MOS transistor received from a second metal wiring electrically connected to a semiconductor substrate which exists separately from a first metal wiring electrically connected to an electrode of a MOS capacitor is provided. The influence on the capacitor is taken into consideration, and the above-mentioned influence depends on the size of the wiring, such as the height. However, when the distance between the first metal wiring and the second metal wiring is 1 μm or less, Occur.

As described above, even when the distance between the first metal wiring and the second metal wiring is 1 μm or less, the insulating film area of the MOS capacitor is particularly reduced to S [μm
2] When the height of the metal wiring is H [μm] and the length of the portion of the first metal wiring adjacent to the second metal wiring is 100 × S / H or more, A large impact.

(Embodiment 1) FIG. 1 shows a structural view of a dry etching damage detecting apparatus according to Embodiment 1 of the present invention. FIG. 1A is a plan view of a semiconductor device, and FIG. 1B is an MO corresponding to AA ′ in FIG.
It is sectional drawing of an S-type transistor and a diode.

In FIG. 1, reference numeral 101 denotes a P-type semiconductor substrate 1
The element isolation region formed on the reference numeral 00 is an N-type MOS
A gate insulating film constituting the transistor 103, 104 is a gate electrode, 105 is an interlayer insulating film formed on the semiconductor element, and a metal wiring 106 is connected to the gate electrode 104 of the N-type MOS transistor via a contact plug 107. ing. 108 denotes a P-type semiconductor substrate 100
An N-type semiconductor region formed therein;
9 are formed. The metal wiring 110 is connected to the diode 109 via a contact plug 111.

According to the present embodiment, the gate electrode 104
Wiring 110 adjacent to the metal wiring 106 connected to
The damage to the gate insulating film 103 is greatly amplified by the presence of (connected to the diode 109). FIG. 2 shows the correlation between the aspect ratio between the metal wiring 106 and the metal wiring 110 during dry etching and the deterioration of the reliability of the gate insulating film. For comparison, the results for the case where the metal wiring 112 not connected to the diode is adjacent as shown in FIG. 3 are also shown. It can be seen that the damage increases due to the adjacent diode connection wires, and the difference tends to increase as the aspect ratio increases. Therefore, dry etching damage can be monitored with high sensitivity by using the antenna TEG described in this embodiment.

In this embodiment, the metal wiring connected to the diode is used. However, the same effect can be obtained when a metal wiring which is in resistive contact with the semiconductor substrate is used.

(Embodiment 2) FIG. 4 is a flowchart showing a method of monitoring dry etching damage in Embodiment 2 of the present invention. In step 200 in the figure, an apparatus for detecting the dry etching damage of the N-th layer metal wiring and an apparatus for evaluating the reference as shown in FIGS. 5 and 7 are installed on the same wafer as the product. Step 201
In the above, a resist removal process on the wafer used in the dry etching process is performed. Step 20
In 2, charge injection is performed at a constant current density of, for example, 100 mA / cm 2 into the insulating film of the reference evaluation device and the dry etching damage detection device using a device as shown in FIG. And Qbd1 [C / cm2] and Qb
d2 [C / cm2] is measured. Step 20
In No. 3, the difference between the Qbd2 and the Qbd1 is calculated to calculate the damage amount ΔQbd [C / cm2].
Is calculated.

According to the present embodiment, by using the high-sensitivity dry etching damage detection device provided on the same wafer as the product, the amount of damage in the dry etching step can be performed simultaneously with the N-th layer dry etching of the product. , And very high sensitivity and high precision damage monitoring can be performed.

In this embodiment, the insulating film of the dry etching damage detecting device is formed simultaneously with the gate insulating film of the MOS transistor of the product, so that the dry etching damage suitable for the actual product can be detected. It has become.

In this embodiment, Qbd1 is measured for each wafer. However, since the fluctuation of Qbd1 is usually sufficiently small compared to the fluctuation of Qbd2, the values measured at appropriate intervals and stored in a database are used. It may be used as Qbd1.

In this embodiment, the damage quantification evaluation is performed immediately after the resist is removed after the dry etching of the N-th layer metal wiring for evaluating the amount of damage. Even after performing the above-mentioned processing, the same damage evaluation can be performed by adding a step of exposing the N-th layer metal wiring to the surface as necessary.

(Embodiment 3) FIG. 8 is a flowchart showing a wiring layout diagnosis method according to Embodiment 3 of the present invention. In step 300 in FIG.
The contact for connecting the layer and the N-th layer is formed by the connection mode with the semiconductor substrate in the wiring layer of the N-th layer or lower according to (1)
A contact connected only to the gate electrode, (2) a contact having a resistive or rectifying connection with the semiconductor substrate,
(3) The contacts are classified into three types: contacts that are not connected to any of them. In step 301, independent wiring patterns are extracted from the wiring layout data in the Nth wiring layer, and K wiring patterns independent of each other are obtained. In step 302, the step 3
From the results of 00 and 301, (1) the wiring patterns A1, A2,... Connected only to the gate electrodes based on the connection form with the semiconductor substrate in the wiring layers below the Nth layer from all the Nth wiring patterns. Ak (for each wiring, total gate insulating film area information S of transistors connected to each wiring,
1, S2..., Sk), and (2) a wiring pattern B having a resistive or rectifying connection with the semiconductor substrate is extracted. Subsequently, the wiring pattern A connected only to the k independent gate electrodes extracted in the step 302
The calculations in steps 303 to 305 are performed for the wirings of 1, A2,. In step 303, the shortest distance x from an arbitrary side wall point of the wiring pattern An (n = 1 to k) to the wiring pattern B is calculated.
In step 304, the coefficients A and B obtained in advance
Is used to calculate a value y such that y = Aexp (B / x).
In step 305, the amount of damage Yn [C] is calculated by calculating and integrating the y value over the entire area of the wiring pattern An. Finally, step 30
6, in any of the Y wirings of the k wirings,
For example, “NG” is output if there is a material of Sn [cm 2] × 10 or more, and “OK” is output if there is no material (here, the height of the N-th layer metal wiring is H [μm] And). That is, in the present embodiment, the first wiring pattern connected to the gate electrode of the MOS transistor
After extracting a second wiring pattern having a resistive or rectifying connection with the semiconductor substrate, a shortest distance x to the second wiring pattern at an arbitrary point of the first wiring pattern is calculated. The dependent damage amount y is obtained, and y is integrated.

In the present embodiment, step 303
To 304, the amount of damage introduced into the gate electrode wiring due to the presence of the wiring pattern electrically connected to the semiconductor substrate is reduced by Aex according to the distance x between the metal wirings.
It can be calculated by the equation p (B / x). Therefore, according to the present embodiment, it can be diagnosed by computer processing of the wiring layout whether or not the increase in the reliability of the gate insulating film in the dry etching step exceeds the specified value.

In the present embodiment, it is used that the dry etching damage can be approximated by a relation of y = Aexp (B / x). Therefore, the coefficients A and B used in the present embodiment are obtained by changing the distance x [μm] between the gate electrode wiring and the substrate connection wiring in the dry etching damage detection apparatus shown in FIG. The amount of deterioration of Qbd [C / cm2], that is, the amount of charge injected into the insulating film is obtained, and the amount of charge Q [C] injected per unit adjacent wiring length is calculated as Q = Aexp (B / x). By fitting based on the relationship, the coefficient A,
B can be obtained.

(Embodiment 4) FIG. 9 is a flowchart showing a method of diagnosing a wiring layout according to Embodiment 4 of the present invention. In step 400 in FIG.
The contact for connecting the layer and the N-th layer is formed by the connection mode with the semiconductor substrate in the wiring layer of the N-th layer or lower according to (1)
A contact connected only to the gate electrode, (2) a contact having a resistive or rectifying connection with the semiconductor substrate,
(3) The contacts are classified into three types: contacts that are not connected to any of them. In step 401, independent wiring patterns are extracted from the wiring layout data in the Nth wiring layer, and K wiring patterns independent of each other are obtained. In step 402, the step 4
From the results of 00 and 401, (1) the wiring patterns A1, A2,... Connected only to the gate electrodes based on the connection form with the semiconductor substrate in the wiring layers below the Nth layer from all the Nth wiring patterns. Ak (for each wiring, total gate insulating film area information S of transistors connected to each wiring,
1, S2..., Sk), and (2) a wiring pattern B having a resistive or rectifying connection with the semiconductor substrate is extracted. Subsequently, in step 403, the wiring pattern area B is expanded on the computer by, for example, at most 1 μm to obtain an area B ′. In step 404, the wiring patterns A1, A connected to only the k independent gate electrodes obtained in step 402 are connected.
.., Ak are ANDed with the area B ′ to obtain areas E1, E2,. In step 405, the lengths of the regions E1, E2,..., Ek are calculated, and for one of the k wirings, for example, Sn
(NG) is output if there is any of (n = 1 to k) × 100 / H [μm] or more, and “OK” is output otherwise. Here, the height of the N-th layer metal wiring is H [μ
m]).

In the present embodiment, step 403
In this case, a region B ′ is obtained as a region having a distance of 1 μm or less from a wiring electrically connected to the semiconductor substrate, that is, a region where damage in a dry etching step is particularly increased. Therefore, when the length of the region included in the region B ′ exceeds, for example, Sn (n = 1 to k) × 100 / H [μm], the reliability of the gate insulating film of the transistor in the dry etching process is deteriorated. Since the value exceeds the specified value, its existence can be known in step 405. Therefore, according to the present embodiment,
Regarding whether the increase in transistor gate insulating film reliability degradation in the dry etching process exceeds the specified value,
Computer processing of the wiring layout enables simple diagnosis.

[0027]

As described above, the present invention provides a high-sensitivity dry etching damage detection device in which a wiring connected to a semiconductor substrate is arranged adjacent to a gate electrode wiring, thereby reducing the damage amount in an actual device. Assumed process optimization and dry etching damage management sensitive to process variation can be realized. Further, based on the evaluation result using the dry etching damage detection device, the wiring layout of each wiring layer of the semiconductor integrated circuit is diagnosed from the viewpoint of deterioration of the reliability of the gate insulating film due to the loss of the wiring electrically connected to the substrate. It provides a method for doing so.

[Brief description of the drawings]

FIG. 1 is a structural diagram of a dry etching damage detection device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing characteristics of a dry etching damage detection device.

FIG. 3 is a structural diagram of a dry etching damage detection device not including a diode used for comparison in the first embodiment of the present invention.

FIG. 4 is a process chart of a method for diagnosing a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a structural diagram of a dry etching damage detection device according to a second embodiment of the present invention.

FIG. 6 is a structural diagram of a dry etching damage detection device not including a diode used for comparison in Embodiment 2 of the present invention.

FIG. 7 is a schematic diagram of a constant current TDDB evaluation device.

FIG. 8 is a process chart of a method for diagnosing a semiconductor device according to a third embodiment of the present invention;

FIG. 9 is a process chart of a method for diagnosing a semiconductor device according to a fourth embodiment of the present invention;

FIG. 10 is a structural diagram of a conventional dry etching damage detection device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 P-type semiconductor substrate 101 Device isolation region 102 Gate oxide film 103 N-type MOS transistor 104 Gate electrode 105 Interlayer insulating film 106 Metal wiring connected to gate electrode 107 Contact plug 108 N-type semiconductor region 109 Diode 110 Diode connected Metal wiring 111 Contact plug 112 Metal wiring 113 Pad area 114 Resist mask 115 Semiconductor substrate 116 Insulating film 117 Electrode 118 Interlayer film 119 Contact 120 Measurement pad 121 Wafer chuck 122 Probe 123 Voltmeter 124 Current source 125 Control system

Claims (6)

[Claims] A first metal wiring connected to an electrode of a MOS capacitor formed on a semiconductor substrate; and a first metal wiring formed adjacent to the first metal wiring at a distance of 1 μm or less, and electrically connected to the semiconductor substrate. A dry etching damage detection device having a second metal wiring electrically connected. 2. An insulating film area of a MOS capacitor is S (μm
2) When the height of the metal wiring is H (μm), the length of a portion of the first metal wiring adjacent to the second metal wiring at a distance of 1 μm or less is 100 × S / H. 2. The dry etching damage detection device according to claim 1, wherein: 3. A semiconductor device comprising: a first metal wiring connected to an electrode of a MOS capacitor formed on a semiconductor substrate; and a first metal wiring formed adjacent to the first metal wiring at a distance of 1 μm or less, and electrically connected to the semiconductor substrate. Simultaneously dry-etching the second metal wiring which is electrically connected, and forming a constant current TDDB (Time Dependen) on the insulating film of the MOS capacitor.
e. a step of evaluating by a Dielectric Breakdown test. 4. A first wiring pattern connected to a gate electrode of a MOS transistor by extracting wiring patterns independent of each other from wiring layout data, and connecting the independent wiring patterns to a semiconductor substrate by a connection mode with a semiconductor substrate. Extracting a second wiring pattern having a resistive or rectifying connection with the semiconductor substrate, and calculating a shortest distance from the second wiring pattern at an arbitrary point of the first wiring pattern; Calculating the damage amount depending on the shortest distance, calculating the damage amount over the entire area of the first wiring pattern, and calculating an integrated value thereof, and comparing the integrated value with a preset reference value A method for diagnosing a semiconductor device having steps. 5. A first wiring pattern connected to a gate electrode of a MOS transistor, wherein independent wiring patterns are extracted from wiring layout data, and the independent wiring patterns are connected to a semiconductor substrate by a connection form with a semiconductor substrate. Extracting a second wiring pattern having a resistive or rectifying connection with the semiconductor substrate; expanding the area of the second wiring pattern by a specific distance to obtain a third area; A step of extracting a portion 1 included in the third region from the outline of the first wiring pattern; and a step of comparing the length of the extracted portion 1 with a preset reference value. Diagnostic method. 6. The diagnostic method according to claim 5, wherein the area of the second wiring pattern is extended by a distance of 1 μm or less to obtain a third area.