JPH1079421A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: In a semiconductor integrated circuit device having a trench buried type separation structure, a residual stress around a separation groove is reduced. SOLUTION: In a heat treatment after embedding an insulating film 5c in an isolation groove 5a, a processing temperature at which an intrinsic stress remaining in the insulating film 5c after the embedding process and a thermal stress generated by the heat treatment cancel each other. Heat treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit technology, and more particularly, to a method of manufacturing a semiconductor integrated circuit device having a trench-buried type element isolation portion and a semiconductor integrated circuit. The present invention relates to technology that is effective when applied to an apparatus.

[0002]

2. Description of the Related Art An element isolation technique in a semiconductor integrated circuit device is an important technology for securing the electrical characteristics of the device while improving the degree of element integration and improving the performance of the entire semiconductor integrated circuit device. .

In particular, in a large-capacity semiconductor memory, how to reduce the distance between adjacent elements is a factor that determines the size of the memory cell region, and therefore, element isolation technology is important in increasing the memory capacity. .

Further, from the viewpoint of the electrical characteristics of the device, for example, a MOS-FET (Metal Oxide Semiconductor)
r Field Effect Transistor), which affects the junction leak, as well as the narrow channel effect, electric field concentration at the edge, and sub-threshold characteristics.

[0005] As this element isolation technique, a local oxidation method (Local Oxidization of Silicon; hereafter referred to as LOC) is generally used.
OS) is used, but development of a new element isolation technique that replaces element isolation by LOCOS is being promoted in accordance with a demand for improvement in element integration.

As such a new device isolation technology, there is a trench isolation type device isolation technology. This technology is a technology for performing element isolation by embedding a predetermined material in a groove formed in a semiconductor substrate, and has the following excellent features.

That is, the device isolation interval can be reduced, the device isolation film thickness can be easily set and controlled, the field inversion voltage can be easily set, and impurities can be separated between the side walls and the bottom in the trench to prevent inversion. Since the layer can be separated from the element diffusion layer and the channel region, it is advantageous in ensuring sub-threshold characteristics, reducing junction leakage, and reducing the back gate effect.

By the way, the present inventor studied a manufacturing process of a semiconductor integrated circuit device having a step of forming an element isolation portion. The following is a technology studied by the present inventor and not a known technology, but the outline is as follows.

First, after a separation groove extending in the width direction is formed in a semiconductor substrate by an etching method or the like, a separation film made of an insulating material or the like is formed on the semiconductor substrate by CVD (Chemical Vap).
or Deposition) method.

Subsequently, a heat treatment is performed on the semiconductor substrate in a predetermined gas atmosphere. Then, after the separation film on the semiconductor substrate is removed and planarized so that the separation film remains only in the separation groove, an impurity for forming a well or the like is ion-implanted into the semiconductor substrate with high energy.

The trench isolation type element isolation technology is disclosed in, for example, Press Journal Inc., published on Feb. 20, 1991, entitled "Monthly Semiconductor World".
conductor World) March 1991 "P112-P11
7 describes a trench-buried type element isolation structure and its features and problems.

[0012]

By the way, the present inventor has found the following problems in the manufacturing technology of the semiconductor integrated circuit device having the above-mentioned element isolation portion forming process studied by the inventor.

That is, due to the difference between the intrinsic stress generated in the separation film when the separation film is embedded in the separation groove and the thermal stress generated in the separation film during heat treatment after the formation of the separation film, the vicinity of the separation groove is reduced. As a result, a high-energy ion implantation after the heat treatment causes crystal defects to be generated in the residual stress generation region. Therefore, there arises a problem that the reliability and the yield of the semiconductor integrated circuit device are reduced, for example, a leak current flows between adjacent elements.

An object of the present invention is to provide a technique capable of relaxing residual stress around an isolation groove in a semiconductor integrated circuit device having a trench buried type isolation structure.

Another object of the present invention is to provide a semiconductor integrated circuit device having a trench buried type isolation structure, in which a crystal defect generated in a residual stress generating region around the isolation trench due to ion implantation after the formation of the isolation trench. It is an object of the present invention to provide a technology capable of reducing the noise.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, in the heat treatment after the step of embedding the isolation film in the isolation groove formed in the semiconductor substrate, the intrinsic stress remaining in the isolation film after the step of embedding the isolation film, The method further includes a step of performing a heat treatment at a temperature at which the thermal stress generated in the separation membrane by the heat treatment cancels each other.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. (Note that components having the same functions in all drawings for describing the embodiments are denoted by the same reference numerals.) , And the repeated explanation is omitted).

FIGS. 1 to 6 are cross-sectional views of a main part during a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 7 is a graph showing the relationship between the processing temperature and the stress during the heat treatment step, and FIGS. 8 and 9 show the essential parts of the semiconductor integrated circuit device manufactured by using the method for manufacturing the semiconductor integrated circuit device shown in FIGS. 10 and 11 are sectional views of FIGS.
FIG. 9 is a plan view of the semiconductor integrated circuit device manufactured by using the method for manufacturing a semiconductor integrated circuit device of FIG. 8.

A method of manufacturing a semiconductor integrated circuit device according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 1, an insulating film 2 made of, for example, silicon dioxide (SiO ₂ ) is formed on a semiconductor substrate 1s made of, for example, silicon (Si) single crystal of a predetermined conductivity type.
Is formed by a thermal oxidation method or the like.

Subsequently, an insulating film 3 made of, for example, silicon nitride is formed on the insulating film 2 by a CVD method or the like, and a photoresist pattern such that an isolation formation region of a trench buried structure is exposed thereon. 4 is formed by a photolithography technique.

Thereafter, using the photoresist pattern 4 as an etching mask, the insulating film 3 exposed from the photoresist pattern 4 is removed by dry etching or the like, and then the photoresist pattern 4 is removed. Thus, an opening 3a is formed in the insulating film 3 as shown in FIG.

Next, by using the insulating film 3 remaining on the semiconductor substrate 1s as an etching mask, the insulating film 2 and the semiconductor substrate 1s exposed from the opening 3a of the insulating film 3 are removed by dry etching or the like. As shown in FIG. 3, an isolation groove 5a is formed in the semiconductor substrate 1s.

[0026] Subsequently, by carrying out a thermal oxidation process to the semiconductor substrate 1s, as shown in FIG. 4, consists of the upper surface of the insulating film 3 (including the inside of the isolation trench 5a), for _example, SiO ₂ insulating A membrane (separation membrane) 5b is formed.

Thereafter, as shown in FIG.
An insulating film (isolation) 5c made of, for example, SiO ₂ is deposited on the s by CVD or the like to fill the isolation trench 5a. In this case, the CVD method uses, for example, TEOS (Tetraethoxysilane) gas (about 32.5 MGM) and ozone gas (5.0 SLM (O ₂ ) +13.0 wt.
% O ₃ ) and a thermal CVD method using, for example, nitrogen gas as a carrier gas. The processing temperature is, for example, 440 ° C., and the pressure in the processing chamber is, for example, 450 Torr.

Next, after subjecting the semiconductor substrate 1s to a heat treatment, for example, in a nitrogen gas atmosphere, the insulating film 5
c is etched back method or CMP (Chemical Mechanica)
l Polishing) method, etc.
As shown in (1), an insulating film 5c is buried only in the separation groove 5a to form a separation portion (hereinafter simply referred to as a separation portion) 5 having a trench buried structure.

Thereafter, when the semiconductor substrate 1s is doped with an impurity of a predetermined conductivity type for forming a well, for example, phosphorus as an n-type impurity,
For example, ion implantation is performed at about 1 × 10 ¹³ / cm ² . The ion implantation energy at this time is, for example, 500 KeV.
For example, in the case of boron as a p-type impurity, it is, for example, about 200 KeV.

In the present embodiment, the temperature of the heat treatment after the step of depositing the insulating film 5c is, for example, about 750 ° C. to 850 ° C., preferably 8 ° C.
It should be about 00 ° C.

FIG. 7 shows the relationship between the temperature and the stress during this heat treatment.
Shown in FIG. 7 is a diagram showing a relationship between a processing temperature and a stress applied to the semiconductor substrate 1s when a heat treatment is performed on the semiconductor substrate 1s in which the insulating film 5c is formed by the above-described forming method and conditions.

The horizontal axis indicates the processing temperature, and the vertical axis indicates the stress. In regions where the processing temperature is low, tensile stress is high, and in regions where the processing temperature is high, shrinkage stress is high. It can be seen that both stresses are zero (0) near the processing temperature of about 800 ° C.

That is, by setting the processing temperature during the heat treatment as described above, the insulating film 5c can be formed immediately after the deposition.
In this case, the intrinsic stress remaining in the groove and the thermal stress generated by the heat treatment can be offset each other, so that the residual stress remaining around the separation groove 5a can be reduced.

For this reason, it is possible to reduce crystal defects generated near the isolation trench 5a due to the ion implantation step after the heat treatment step. Therefore, the leak current flowing between the elements can be reduced, and the separation capability of the separation unit 5 can be improved, so that the yield and reliability of the semiconductor integrated circuit device can be improved.

Next, an application example of a semiconductor integrated circuit device manufactured by using the method of manufacturing a semiconductor integrated circuit device according to the present embodiment will be described with reference to FIGS. FIG. 8 is a sectional view taken along line VIII-VIII in FIG.

The semiconductor integrated circuit device according to the present embodiment is, for example, a 64-Mbit DRAM. However, the present invention
The present invention is not limited to application to a 64 Mbit DRAM, and various applications are possible.

The semiconductor substrate 1s which constitutes the DRAM, for example p ^- made form of silicon (Si) single crystal, in its upper portion, the separation portion 5 of the grooving buried structure for element isolation is formed.

The separation portion 5 is formed by the above-described method, and is formed by embedding insulating films 5b and 5c in a separation groove 5a dug in the semiconductor substrate 1s. The depth of the separation groove 5a is, for example, about 0.3 μm.

The insulating film 5b is formed mainly for the purpose of stress relaxation. The insulating film 5c is a film for exclusively filling the isolation groove 5a. This insulating film 5
The upper surfaces of b and 5c are formed flat so as to have the same height as the main surface of the semiconductor substrate 1s.

Semiconductor substrate 1s in memory cell region M
A p-well 6p is formed on the upper portion of the substrate by ion implantation for forming the well. This p-well 6p
Is doped with, for example, boron as a p-type impurity.

The memory cell MC is formed on the p well 6p. This memory cell MC has 1
Memory cell selection MOS-FET (hereinafter referred to as selection MOS
7) and one capacitor 8. The size of this one memory cell MC is, for example, 1.1.
It is about 5 μm ² .

The selection MOS 7 has a pair of semiconductor regions 7a and 7b formed apart from each other on the upper portion of the semiconductor substrate 1s.
And a gate insulating film 7c formed on the semiconductor substrate 1s
And a gate electrode 7d formed on the gate insulating film 7c.

The semiconductor regions 7a and 7b are regions for forming a source region and a drain region of the selection MOS 7, and for example, an n-type impurity such as phosphorus or arsenic (As) is introduced into the semiconductor regions 7a and 7b. ing. In addition,
A channel region of the selection MOS 7 is formed between the semiconductor regions 7a and 7b.

One active region composed of the semiconductor regions 7a and 7b and two channel regions is defined so that its planar shape is surrounded by the separating portion 5, and is symmetrical about the semiconductor region 7a. It is formed in a shape (see FIG. 10).

The gate insulating film 7c is made of, for example, SiO ₂ . The gate electrode 7d is formed by depositing a conductor film 7d2 made of, for example, tungsten on a conductor film 7d1 made of, for example, a low-resistance polysilicon film. The resistance of the gate electrode 7d is reduced by the conductive film 7d2.

However, the gate electrode 7d may be formed of a single film of low-resistance polysilicon, or may be formed of a single film of a metal film such as tungsten. The conductive film 7
d2 is, for example, tungsten silicide (WSi ₂₎ silicide film may be used, such as.

The gate electrode 7d is also a part of the word line WL. The word line WL extends in a direction orthogonal to the direction in which the active region extends, and the selection M
A certain width (L) required to obtain the threshold voltage of OS7
g) (see FIG. 10). The interval between the adjacent word lines WL is, for example, about 0.67 μm.

The region of the word line WL having the dimension of Lg is provided wider than the width of the active region by at least an amount corresponding to the mask alignment margin in the manufacturing process.

When the element isolation region is formed of a field insulating film by the LOCOS method, the upper portion of the field insulating film protrudes from the main surface of the semiconductor substrate 1s, and a step formed by the field insulating film on the main surface of the semiconductor substrate 1s. Is formed, the word line WL is formed on the main surface, the thickness of the metal film constituting the word line WL is reduced due to the low step coverage, and the resistance of the word line WL increases. There is.

However, in the present embodiment, since the upper surface of isolation portion 5 is formed flat, word lines WL are formed with substantially the same thickness in the extending direction. For this reason, the resistance of the word line WL can be reduced as compared with the case where the field insulating film is used as the separation portion.

The upper surface and the side surfaces of the gate electrode 7d (word line WL) are formed with the cap insulating film 10a and the sidewall (sidewall insulating film) 10b via the insulating films 9a and 9b.
Covered by These cap insulating films 10
a and the side wall 10b are made of the interlayer insulating films 11a to 11a.
11c.

The interlayer insulating films 11a to 11c have
A connection hole 12a1 is formed to expose the semiconductor region 7a in the upper layer of the semiconductor substrate 1s, and the interlayer insulating films 11a, 1 are formed.
A connection hole 12b1 is formed in 1b so that the semiconductor region 7b in the upper layer of the semiconductor substrate 1s is exposed. The diameter of these connection holes 12a1 and 12b1 is, for example, 0.36 μm.
It is about.

The insulating films 9a and 9b are made of, for example, SiO ₂ and have, for example, the following two functions. That is,
First, the cap insulating film 10a and the side wall 1
0b is formed, the inside of the film forming processing apparatus becomes conductive film 7d2.
This function prevents contamination with the constituent metal elements.
The second function is to reduce stress applied to the cap insulating film 10a and the sidewalls 10b due to a difference in thermal expansion during a heat treatment or the like in a manufacturing process of a semiconductor integrated circuit device.

In this embodiment, the cap insulating film 10a and the side wall 10b are formed of, for example, silicon nitride having a thickness of about 1000 to 3000 °.

As a result, the cap insulating film 10a and the side wall 10b serve as an etching stopper when the connection holes 12a1 and 12b1 are formed in the interlayer insulating films 11a and 11b, and the connection holes 1a between the adjacent word lines WL.
2a1 and 12b1 are formed in a self-aligning manner. That is, the cap insulating film 10a and the side wall 10b are connected to the connection hole 1 in the width direction of the word line WL.
The dimensions 2a1 and 12b1 are specified.

For this reason, for example, the connection holes 12a1, 12b1
Is slightly shifted in the width direction of the word line WL (the horizontal direction in FIG. 10), since the cap insulating film 10a and the side wall 10b function as an etching stopper,
Part of the word line WL is not exposed from the connection holes 12a1 and 12b1. Therefore, the connection hole 12a
1,12b1 can be reduced in alignment margin. That is, miniaturization of the memory cell MC can be promoted.

The interlayer insulating film 11a is made of, for example, SiO ₂ , and the interlayer insulating film 11b is made of, for example, BPSG (Boro Pho
(spho Silicate Glass). This interlayer insulating film 11a
Has a function of preventing boron or phosphorus in the upper interlayer insulating film 11b from diffusing into the lower semiconductor substrate 1s.

The interlayer insulating film 11b has a function of flattening the base of the wiring layer. As a result, a margin for photolithography can be secured, and the connection hole 1
The pattern transfer accuracy of 2a1, 12b1 and wiring can be improved.

On the interlayer insulating film 11b, for example, SiO ₂
An interlayer insulating film 11c is formed. If a part of the cap insulating film 10a is exposed from the interlayer insulating film 11b at the time of a bit line forming step to be described later or the like, the exposed portion is etched to expose the word line WL. This is a film for preventing such a case. Therefore, when such a problem does not occur, it may not be provided.

The bit line BL is formed on the interlayer insulating film 11c. The bit line BL is formed, for example, in a layer above the conductor film BL1 made of low-resistance polysilicon, for example, by WS
conductor films BL2 is being deposited consisting of i _2, the connection hole 1
It is electrically connected to the semiconductor region 7a via 2a1. The interval between the adjacent bit lines BL is, for example,
It is about 0.86 μm.

A mask film 13b serving as an etching mask when forming the connection hole 12a1 is left between the conductor film BL1 and the interlayer insulating film 11c. This mask film 1
Reference numeral 3b denotes a film for increasing the etching selectivity at the time of forming the connection hole 12a1, which is made of, for example, low-resistance polysilicon and is also a part of the bit line BL.

The bit line BL is connected to the word line W
They are arranged so as to be orthogonal to L (see FIG. 11). The center line of the bit line BL does not necessarily have to coincide with the center of the connection hole 12a1 for the bit line. In this case, however, the bit line BL has a protrusion for completely surrounding the connection holes 12b1 and 12b2 for the capacitor. I need.

If the above-mentioned protruding portion is formed on the bit line BL, a short circuit between the adjacent bit line BL and the protruding portion may occur. Therefore, the portion of the bit line BL adjacent to the protruding portion is removed from the protruding portion. It is slightly bent away.

The upper and side surfaces of the bit line BL are covered with a cap insulating film 14a and a side wall 14b via insulating films 9c and 9d. The cap insulating film 14a and the side wall 14b are formed of the same material as the constituent material of the cap insulating film 10a and the side wall 10b covering the word line WL.

The thickness of the cap insulating film 14a and the side wall 14b is, for example, about 1000 °.
The cap insulating film 14a and the side wall 14b
Is covered with an insulating film 11d. The insulating film 11d is a film that functions as an etching stopper when removing the underlying insulating film after the formation of the capacitor 8, and is made of, for example, silicon nitride.

The thickness of the insulating film 11d is, for example, 100
It is set at about 500 °, preferably about 250 °. If the thickness is larger than this, hydrogen is trapped by the silicon nitride film during the final hydrogen annealing treatment for terminating dangling bonds, and a sufficient termination effect cannot be obtained.

In the upper layer of the bit line BL, for example, a cylindrical capacitor 8 is formed. That is, the DRAM of the present embodiment has a so-called COB (Capacitor Over Bitlin) in which the capacitor 8 is arranged on the bit line BL.
e) It has a structure.

The capacitor 8 is configured such that the surface of the first electrode 8a is covered with the second electrode 8c via the capacitor insulating film 8b. That is, in the present embodiment, the first electrode 8
Capacitance portions are also formed on the lower surface side of a and on the side surface of the shaft portion of the capacitor 8, so that a large capacitance can be secured.

The first electrode 8a is made of, for example, low-resistance polysilicon, and has the conductor film 1 embedded in the connection hole 12b1.
5, is electrically connected to one semiconductor region 7b of the selection MOS 7. The conductor film 15 is made of, for example, low-resistance polysilicon.

The capacitor insulating film 8b is formed, for example, by depositing a SiO ₂ film on a silicon nitride film. The second electrode 8c is made of, for example, low-resistance polysilicon, and is electrically connected to a predetermined wiring.

The mask film 13c below the first electrode 8a of the capacitor 8 is a film used as a mask when forming the connection hole 12b2. This mask film 13c is made of, for example, low-resistance polysilicon,
It is a part of the electrode 8a.

On the other hand, a p-well 6p and an n-well 6n are formed above the semiconductor substrate 1s in the peripheral circuit region P. For example, boron of a p-type impurity is introduced into the p well 6p. Further, for example, phosphorus or As, which is an n-type impurity, is introduced into the n-well 6n. On the p well 6p and the n well 6n, for example, an nMOS 16 and a pMOS 17 are formed.

These nMOS 16 and pMOS 17
Thereby, peripheral circuits such as a DRAM sense amplifier circuit, a column decoder circuit, a column driver circuit, a row decoder circuit, a row driver circuit, an I / O selector circuit, a data input buffer circuit, a data output buffer circuit, and a power supply circuit are formed. Have been.

The nMOS 16 has a pair of semiconductor regions 16a and 16 formed apart from each other above the p well 6p.
b and the gate insulating film 16 formed on the semiconductor substrate 1s
c and the gate electrode 1 formed on the gate insulating film 16c.
6d.

The semiconductor regions 16a and 16b have the nMOS1
6 for forming a source region and a drain region. In the semiconductor regions 16a and 16b, for example, phosphorus or As of an n-type impurity is introduced. In addition,
A channel region of the nMOS 16 is formed between the semiconductor regions 16a and 16b.

The gate insulating film 16c is made of, for example, SiO ₂ . The gate electrode 16d is formed by depositing a conductor film 16d2 made of tungsten on a conductor film 16d1 made of, for example, low-resistance polysilicon. However, the gate electrode 16d may be formed of a single film of, for example, low-resistance polysilicon, or may be formed of a single film of a metal film such as tungsten. The conductor film 16d2 may use a silicide film such as WSi _2, and the like.

On the upper surface and side surfaces of the gate electrode 16d,
A cap insulating film 10a and a side wall 10b are formed via the insulating films 9a and 9b. Insulating film 9a,
9b is an insulating film 9a, 9b in the memory cell region M described above.
And has the same function as, for example, SiO ₂ .

The cap insulating film 10a and the side walls 10b are made of, for example, silicon nitride. However, in this case, the side wall 10b is
This is a film for forming a shallow semiconductor region on the channel side of 6a and 16b.

The pMOS 17 has a pair of semiconductor regions 17a and 17 formed apart from each other on the n-well 6n.
b and the gate insulating film 17 formed on the semiconductor substrate 1s
c and the gate electrode 1 formed on the gate insulating film 17c.
7d.

The semiconductor regions 17a and 17b are formed by pMOS1
5 is a region for forming a source region and a drain region, and for example, boron as a p-type impurity is introduced into the semiconductor regions 17a and 17b. Note that a channel region of the pMOS 17 is formed between the semiconductor regions 17a and 17b.

The gate insulating film 17c is made of, for example, SiO ₂ . The gate electrode 17d is formed by depositing a conductor film 17d2 made of WSi ₂ on a conductor film 17d1 made of, for example, low-resistance polysilicon. However, the gate electrode 17d may be formed of, for example, a single film of low-resistance polysilicon or a single film of a metal such as tungsten. The conductor film 17d2 is made of, for example, WSi.
A silicide film such as ₂ may be used.

On the upper surface and side surface of the gate electrode 17d,
A cap insulating film 10a and a side wall 10b are formed via the insulating films 9a and 9b. Insulating film 9a,
9b is an insulating film 9a, 9b in the memory cell region M described above.
And has the same function as, for example, SiO ₂ .

The cap insulating film 10a and the side walls 10b are made of, for example, silicon nitride. However, in this case, the side wall 10b is
This is a film for forming a shallow semiconductor region on the channel side of 6a and 16b.

The nMOS 16 and pMOS 17 are
The insulating film 1 is covered with the above-mentioned interlayer insulating films 11a to 11c.
1d is deposited. Further, in such a memory cell region M and a peripheral circuit region P, an interlayer insulating film 11e is formed on the insulating film 11d, thereby covering the second electrode 8c of the capacitor 8.

The interlayer insulating film 11e is formed by depositing an insulating film 11e2 made of, for example, BPSG on an insulating film 11e1 made of, for example, SiO ₂ . Insulating film 11e
Reference numeral 1 has a function of preventing boron or phosphorus in the upper insulating film 11e2 from diffusing to the second electrode 8c side of the capacitor 8.

As described above, according to the present embodiment, the following effects can be obtained.

(1) In the heat treatment after the insulating film 5c for forming the isolation portion 5 is deposited, the heat treatment temperature is set such that the intrinsic stress and the thermal stress cancel each other, so that the insulating film 5c is formed immediately after the deposition. In this case, the intrinsic stress remaining in the groove and the thermal stress generated by the heat treatment can be offset each other, so that the residual stress remaining around the separation groove 5a can be reduced.

(2) According to the above (1), it is possible to reduce crystal defects occurring near the separation groove 5a due to the ion implantation step after the heat treatment step.

(3) According to the above (1) and (2), the separation capability of the separation unit 5 can be improved, so that the yield and reliability of the semiconductor integrated circuit device can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof. Needless to say,

For example, in the above-described embodiment, the case where the heat treatment is performed in a nitrogen gas atmosphere after the step of depositing the insulating film for forming the isolation portion has been described. However, the present invention is not limited to this, and various changes can be made. Yes, for example, the heat treatment may be performed in an atmosphere of argon gas, hydrogen gas or oxygen gas.

Further, in the above embodiment, the case where the capacitor of the memory cell is cylindrical has been described. However, the present invention is not limited to this, and various modifications can be made. For example, a fin may be used.

Further, in the above-described embodiment, the case where the bit line is constituted by providing a silicide layer on low-resistance polysilicon has been described. However, the present invention is not limited to this. For example, the bit line is formed only by the silicide layer. May be. In this case, the bit line can be made thin.

In the above embodiment, the MOS
The case where the cap insulating film and the sidewall made of silicon nitride or the like are provided around the gate electrode of the FET has been described, but the present invention is not limited to this. For example, the cap insulating film and the sidewall are made of SiO ₂ And may be applied to the case where the cap insulating film and the side wall are not provided.

In the above embodiment, the present invention is applied to a DR having a structure in which a capacitor is arranged above a bit line.
Although the case where the present invention is applied to AM has been described, the present invention is not limited to this, and the present invention can also be applied to a DRAM having a structure in which a capacitor is arranged below a bit line.

In the above description, the invention made mainly by the present inventor is referred to as DRA, which is a field of application in which the background was used.
M has been described, but the present invention is not limited to this. For example, SRAM (Static Random Acce
ss Memory) and EEPROM (Electrically Erasable Pr
The present invention can be applied to other semiconductor memories such as grammable ROMs, and also to a semiconductor integrated circuit device having a logic circuit such as a microprocessor. INDUSTRIAL APPLICABILITY The present invention can be applied to an apparatus having at least a trench-buried type separation part.

[0097]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, in the heat treatment after the separation film deposition step, the heat treatment temperature is set so that the intrinsic stress and the thermal stress cancel each other. Since the residual stress around the separation groove can be reduced, it is possible to reduce the occurrence of crystal defects in the residual stress generation region due to the ion implantation step after the heat treatment. Therefore, it is possible to suppress the occurrence of a problem such as a leak current flowing between the elements,
Since the element isolation capability can be improved, it is possible to improve the yield and reliability of the semiconductor integrated circuit device having the trench buried type isolation portion.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention during a manufacturing step thereof;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5;

FIG. 7 is a graph showing a relationship between a processing temperature and a stress in a heat treatment step.

FIG. 8 is a cross-sectional view of a main part of a semiconductor integrated circuit device manufactured by using the method of manufacturing the semiconductor integrated circuit device of FIGS. 1 to 6;

FIG. 9 is a cross-sectional view of a main part of the semiconductor integrated circuit device manufactured by using the method of manufacturing the semiconductor integrated circuit device of FIGS. 1 to 6;

10 is a plan view in FIG. 8 of the semiconductor integrated circuit device manufactured by using the method of manufacturing the semiconductor integrated circuit device in FIGS. 1 to 6;

11 is a plan view of the semiconductor integrated circuit device manufactured by using the method of manufacturing the semiconductor integrated circuit device of FIGS. 1 to 6 in FIG. 8;

[Explanation of symbols]

 1s Semiconductor substrate 2 Insulating film 3 Insulating film 3a Opening 4 Photoresist pattern 5 Separating part 5a Separating groove 5b Insulating film (separating film) 5c Insulating film (separating film) 6p p-well 6n n-well 7 Memory cell selection MOS / FET 7a , 7b semiconductor region 7c gate insulating film 7d gate electrode 7d1, 7d2 conductive film 8 capacitor 8a first electrode 8b capacitor insulating film 8c second electrode 9a, 9b insulating film 10a cap insulating film 10b sidewall 11a-11c interlayer insulating film 11d insulating Film 12a1 Connection hole 12b1, 12b2 Connection hole 13b, 13c Mask film 14a Cap insulating film 14b Sidewall 15 Conductive film 16 N-channel type MOS / FET 16a, 16b Semiconductor region 16c Gate insulating film 16d Gate electrode 16d1, 16d2 Conductive film 17 p channel The MOS · FET 17a, 17b semiconductor region 17c gate insulating film 17d gate electrode 17d1,17d2 conductor film

Claims (6)

[Claims] In a heat treatment after a step of embedding a separation film in a separation groove formed in a semiconductor substrate, intrinsic stress remaining in the separation film after a step of embedding the separation film and thermal stress generated in the separation film by the heat treatment are reduced. A method for manufacturing a semiconductor integrated circuit device, comprising a step of performing heat treatment at a temperature that offsets each other. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the step of ion-implanting impurities of a predetermined conductivity type into said semiconductor substrate. . 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said separation film is formed by a chemical vapor deposition method using a mixed gas of a tetraethoxysilane gas and an ozone gas. Of manufacturing a semiconductor integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the temperature during the heat treatment step is 800 ° C. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a gas atmosphere in said heat treatment step is a nitrogen gas, an argon gas, a hydrogen gas, or an oxygen gas atmosphere. A method for manufacturing a semiconductor integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the step of implanting impurities of a predetermined conductivity type is a step for forming a well in a semiconductor substrate. A method for manufacturing an integrated circuit device.