JPH1079438A - Semiconductor protection device and method of manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: To reduce the amount of heat generated at the time of junction breakdown of a protection element and prevent junction breakdown and wiring breakdown. SOLUTION: P-type impurity regions (220b, 220c) having a higher impurity concentration on the surface of a semiconductor substrate (200)
Is formed in the same step as the impurity ion implantation step for adjusting the threshold voltage of the memory cell transistor. Next, a low-concentration N-type impurity region (220b) and a high-concentration impurity region (224b) are formed in the same step as the memory cell transistor formation region. By forming the impurity region (220b) having a higher concentration than the substrate region, a high-concentration PN junction is formed, the junction breakdown voltage is reduced, and the amount of heat generated during the junction breakdown can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor protection device for protecting an internal circuit from external abnormal voltage, particularly static electricity, and a method of manufacturing the same, and more particularly, to a semiconductor device including a memory cell having an insulated gate field effect transistor. The present invention relates to an internal circuit protection device for a storage device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In semiconductor devices, both manufacturers and users are liable to cause destruction of internal circuit elements due to the application of static electricity generated during an assembly and test process to external terminals. Sources of such static electricity include:
"Human body", "Package insertion device", "Test device",
"Thunder" and others. In a MOS LSI (Large Scale Integrated Circuit) having an insulated gate field effect transistor (MOSFET) as a component, when these static electricity is applied, a large electric field is applied to the gate insulating film of the MOSFET connected to the external terminal. Is applied, and the gate insulating film is destroyed. In order to prevent such destruction due to static electricity, M
In an OS-type LSI, a protection circuit is provided for an input circuit, an output circuit, and a power supply line (including both lines for transmitting an operation power supply voltage and a ground voltage) connected to external terminals.

FIG. 33A shows an example of the configuration of a conventional input protection circuit. In FIG. 33A, an input protection circuit 3 is provided between an external terminal 1 for receiving an external signal and an internal circuit 2 for generating an internal signal according to a signal given to the external terminal 1. In internal circuit 2, internal node 9 is connected from external terminal 1 through input protection circuit 3.
Representatively shows an n-channel MOS transistor 4 receiving a signal applied to its gate.

The input protection circuit 3 is connected between the signal line 11 and the internal node 9 and an NPN lateral transistor 5 for discharging an abnormally high voltage (static electricity) applied from the external terminal 1 to the signal line 11. A resistance element 6 for delaying transmission of static electricity to internal circuit 2 by its current limiting function is included. NPN lateral transistor 5 includes a collector node 5a connected to signal line 11, an emitter node 5b connected to a ground node receiving the ground potential,
It has a base connected to substrate region 14 via parasitic resistance 5c. The resistance element 6 is formed of a thin film resistor such as polysilicon formed on a field insulating film or an impurity diffusion layer formed on the surface of a semiconductor substrate.

FIG. 33B shows the NP shown in FIG.
FIG. 3 is a diagram illustrating a planar layout of an N lateral transistor. In FIG. 33B, a field insulating film 16 is formed on the surface of the semiconductor substrate region so as to surround high-concentration N-type impurity region 7 functioning as a collector region. High-concentration N-type impurity region 8 functioning as an emitter region is formed to surround field insulating film 16. The base is provided by the P-type substrate region where this NPN lateral transistor is formed. The N-type impurity region 7
Collector node (signal wiring) via contact hole 12
Are electrically connected to the low-resistance aluminum wiring 5a (11).

In the impurity region 8, low resistance aluminum interconnections 5b (emitter nodes) are provided symmetrically on both sides of the aluminum interconnections 5a (11). Aluminum wiring 5b constituting the emitter electrode node is electrically connected to impurity region 8 via contact hole 13. This aluminum interconnection 5b is connected to receive a ground voltage at a portion not shown. By forming impurity region 8 constituting the emitter region so as to surround impurity region 7 forming the collector region, the width of the path through which the collector current flows is increased, and a large current is discharged at a high speed.

FIG. 33 (C) is a diagram showing a cross-sectional structure along the line AA shown in FIG. 33 (B). FIG.
In (C), NPN lateral transistor is lightly doped P-type (P ^-) is formed on the semiconductor substrate 14 surface and high P-type impurity concentration than the substrate 14 (P ^-)
It is formed on the surface of the well 15. The P well 15 as this semiconductor substrate region is provided to reduce a leak current due to a parasitic MOS transistor.

The NPN lateral transistor includes high-concentration N-type impurity regions 7 and 8 formed on the surface of P well 15 with a space therebetween. Between the impurity region 7 serving as a collector region and the impurity region 8 serving as an emitter region of the NPN lateral transistor, a thick element isolation insulating film 16 formed by LOCOS (local silicon thermal oxidation method).
Is formed. P forming this lateral transistor
An element isolation insulating film 17 formed by the LOCOS method is formed around the well 15.

Impurity regions 7 and 8 are electrically connected to aluminum electrode wires 5a and 5b, respectively, through contact holes 12 and 13 formed in interlayer insulating film 18 formed thereon. Aluminum electrode wiring 5a serving as a collector node is connected to external terminal 1 via signal line 11. Aluminum electrode wiring 5b serving as an emitter node is connected to receive a ground voltage. Next, the operation of the input protection circuit shown in FIGS.

When a voltage during normal operation is applied to external terminal 1, N ⁺ impurity region 7 and P well 15 are in a reverse bias state (P type semiconductor substrate 14 is biased to the ground voltage level. ), The NPN lateral transistor 5 is off. Therefore, the signal applied to external terminal 1 is transmitted to internal node 9 via resistance element 6, and MOS transistor 4 included in internal circuit 2 is turned on or off.

A large voltage level of static electricity is applied to the external terminal 1.
When applied, this static electricity is transferred to the N
Transfer to collector node 5a of PN lateral transistor
Is done. This large positive voltage static electricity is transferred to the impurity region 7.
Through aluminum electrode wiring 5a serving as a collector node
And the impurity region 7 and the P well 15 are deeply inverted.
It is in the ias state. This N⁺Impurity region 7 and P well
Large reverse bias voltage at the junction between
The depletion layer spreads more, and a high electric field is applied in this depletion layer.
Avalanche breakdown (junction breaker
)) And N ⁺From the impurity region 7 to the P well 15
Current flows to the ground line via the P-type semiconductor substrate 14 and
You. The P well 15 and the P-type semiconductor substrate 14 are shown in FIG.
As shown in (A), a resistance component 5c is provided.
The input current causes a voltage drop due to the resistance component 5c,
The potentials of P well 15 and P type semiconductor substrate 14 are raised.
Let

Due to the rise in the potential of P well 15, NP
The base potential of the N lateral transistor rises and NP
The N lateral transistor 5 conducts, and a large amplifying action of the NPN lateral transistor (the length of the base / emitter facing region is large) causes a large current to flow through the impurity region 8 and further through the emitter electrode node (aluminum electrode wiring) 5b. Flows to the ground line. Thereby, static electricity is discharged and a large voltage is prevented from being transmitted to internal node 9. Resistive element 6 delays transmission of this static electricity to internal node 9 and ensures that this N
Prevents static electricity before being absorbed by the PN lateral transistor 5 from being transmitted to the internal node 9. This prevents the gate insulating film of the MOS transistor 4 included in the internal circuit 2 from being broken.

When a large negative static electricity (surge voltage) is applied to the external terminal 1, the P well 15 and the N ⁺ -type impurity region 7 are biased in the forward direction, and the P-type semiconductor substrate 14 and the P-well 15 Thus, a current flows to N ⁺ impurity region 7. In this case, impurity region 7 acts equivalently as an emitter region, and the base / emitter is forward-biased to turn on the lateral NPN bipolar transistor. By action, it supplies current and absorbs negative static electricity (surge voltage).

[0014]

When discharging static electricity,
Amperage current may flow. In order to prevent the wiring and the PN junction from being destroyed by the large discharge current, the following configuration is adopted in the NPN lateral transistor to prevent concentration of power consumption and suppress generation of Joule heat.

In N ⁺ impurity regions 7 and 8, a large number of contact holes are provided, and the total area is made as large as possible. Thus, concentration of current in N ⁺ impurity regions 7 and 8 is prevented. Further, the area of N ⁺ impurity regions 7 and 8 is made as large as possible, and the current in impurity regions 7 and 8 is dispersed.

As the density and integration of semiconductor devices increase,
The area occupied by the input protection circuit decreases accordingly, and the area occupied by the NPN lateral transistor also decreases. When junction breakdown occurs in the NPN lateral transistor due to surge voltage (abnormal voltage) such as static electricity, a large current flows due to the junction breakdown voltage, and Joule heat is generated. Most of the breakdown voltage is applied between the depletion layers of the PN junction having a large resistance value. Further, a large current at the time of breakdown is generated by the avalanche breakdown phenomenon in the depletion layer. Therefore, a large current and voltage are applied at the PN junction, and large Joule heat is generated at this portion. When this Joule heat is equal to or higher than the eutectic temperature (577 ° C.) of aluminum as the electrode wiring and silicon as the substrate material, this heat is transmitted to the contact region provided in the vicinity, so that the collector electrode wiring Eutectic occurs between the aluminum and the silicon of the N ⁺ impurity region 7 connected thereto, that is, aluminum diffuses into the impurity region to form an alloy with silicon Si, and the alloy of aluminum and silicon and the Al alloy are spiked. Grow in shape. The Al alloy spike grows toward the PN junction, and when the Al alloy spike penetrates through the PN junction, the aluminum electrode wiring and the P well 15 and the P type semiconductor substrate 14 are electrically short-circuited, and the input protection circuit is formed. (The external terminal 1 is directly electrically connected to the substrate regions 15 and 14 and a current always flows).

The Joule heat due to such a breakdown voltage causes the eutectic temperature of aluminum and silicon (57 ° C.).
In the past, this breakdown voltage was suppressed to, for example, about 16 V so as not to exceed 7 ° C.). This junction breakdown voltage is expressed by the low impurity concentration of the PN junction and the inverse function of the impurity concentration Na of the P well 15 (Na ^−3/4 to ^−2/5 ). If the impurity concentration in the portion varies, the junction breakdown voltage also varies. If the junction breakdown voltage shifts to a higher value, the amount of heat generated by Joule heat also increases, the temperature near the junction rises above the eutectic temperature of aluminum and silicon, and the NPN lateral transistor as an input protection element is destroyed. ,
A problem arises in that protection against input surge voltage (abnormal voltage; static electricity) cannot be performed.

Further, even when the junction breakdown voltage does not generate heat equal to or higher than the eutectic temperature, for example, 45
If the temperature is 0 ° C. or more, aluminum Al diffuses into the silicon substrate region, and silicon Si diffuses toward the aluminum electrode wiring side, and silicon nodules may be generated in the contact portion. In this case, the silicon nodule has a high resistance, the resistance of the contact portion increases, and the amount of heat generated by Joule heat increases, and this aluminum electrode wiring layer is melted and broken, and does not function as an input protection element. Problems arise.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input protection device which operates stably with an excellent withstand voltage against an abnormal voltage such as static electricity and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor device having a highly reliable input protection circuit which operates easily and stably without increasing the number of manufacturing steps, and a method of manufacturing the same.

[0021]

According to a first aspect of the present invention, there is provided a semiconductor protection device, comprising: a first conductivity type semiconductor substrate region; and a second conductivity type first impurity electrically connected to a first external terminal. A second region of a first conductivity type having a higher impurity concentration than the semiconductor substrate region and formed between the first impurity region and the semiconductor substrate region so as to surround the first impurity region;
First and second impurity regions on the surface of the semiconductor substrate region.
And a third impurity region which is formed apart from the impurity region and is electrically connected to the second external terminal.

A semiconductor protection device according to a second aspect is formed so as to surround the first impurity region between the first and second impurity regions and to be surrounded by the second impurity region.
The semiconductor device further includes a fourth impurity region having an impurity concentration lower than the impurity concentration of the first impurity region.

According to a third aspect of the present invention, in the semiconductor protection device according to the first or second aspect, the third impurity region is a second conductivity type impurity region, and the third impurity region is formed on the surface of the semiconductor substrate region. There is further provided a fourth impurity region of the first conductivity type formed so as to surround it.

According to a fourth aspect of the present invention, there is provided the semiconductor protection device according to the third aspect, wherein the second conductive layer is formed between the third and fourth impurity regions and has a lower impurity concentration than the third impurity region. A fifth impurity region of the mold.

According to a fifth aspect of the present invention, in the semiconductor protection device according to the first or second aspect, the third impurity region is a first conductivity type impurity region having an impurity concentration higher than that of the semiconductor substrate region. .

The semiconductor protection device according to claim 6 is the device according to any one of claims 1 to 5, wherein
A thick insulating film formed on the surface of the semiconductor substrate region between the impurity regions.

According to a seventh aspect of the present invention, there is provided the semiconductor protection device according to any one of the first to fourth aspects, wherein
And a gate electrode layer formed on the surface of the semiconductor substrate region between the impurity regions through an insulating film.

The semiconductor protection device according to claim 8 is the device according to any one of claims 1 to 7, wherein
One of the external terminals receives one of a power supply voltage and a ground voltage, and the other receives one of an input signal and an output signal.

According to a ninth aspect of the present invention, in the semiconductor protection device according to any one of the first to seventh aspects, one and the other of the first and second external terminals receive a power supply voltage and a ground voltage, respectively.

According to a tenth aspect of the present invention, in the device of the third aspect, the gate electrode layer receives a signal from an internal circuit, and one of the first and second external terminals receives one of a power supply voltage and a ground voltage. And the other acts as a signal output terminal.

According to an eleventh aspect of the present invention, in the semiconductor protection device according to any one of the first to tenth aspects, the protection device is used for a semiconductor memory device. A semiconductor memory device includes a plurality of memory cells having at least one insulated gate field effect transistor for storing information. The surface impurity concentration of the channel region of the insulated gate field effect transistor is substantially the same as the impurity concentration of the second impurity region.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a plurality of memory cells arranged in a matrix, each having at least one insulated gate field effect transistor, and accessing the plurality of memory cells. Device for manufacturing a semiconductor device, comprising: an internal circuit for protecting the internal circuit; and a protection element having a junction formed between at least one impurity region of the opposite conductivity type to protect the internal circuit from an abnormal external voltage. In the same step as the implantation of impurity ions into the channel region for adjusting the threshold voltage of the insulated gate field effect transistor of the memory cell, the impurity ions are also introduced into at least one junction forming region of the protection element. It is characterized by being injected.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device, the insulated gate field effect transistor of the memory cell is formed on the surface of the semiconductor substrate region of the first conductivity type, and impurity ions for adjusting the threshold voltage are formed. , A first conductivity type impurity ion. The protection element includes a second conductive type second semiconductor substrate region provided separately from the memory cell formation region, and a second conductive type second semiconductor type region formed on the surface of the second semiconductor substrate region with a gap therebetween. The semiconductor device includes first and second impurity regions. The impurity ion implantation is performed on the first and second impurity region forming regions.

According to a fourteenth aspect of the present invention, in the method of the thirteenth aspect, the impurity ion implantation is performed on a surface of the second semiconductor substrate region between the first and second impurity regions. Is also performed.

According to a fifteenth aspect of the present invention, in the method of the twelfth aspect, the insulated gate field effect transistor of the memory cell is formed in the semiconductor substrate region of the first conductivity type. The protection element includes a first impurity region of the second conductivity type formed on the surface of the second semiconductor substrate region of the first conductivity type provided in a region different from the memory cell formation region and a first impurity region of the second conductivity type. A second impurity region of a conductivity type is included.
The impurity ion implantation is performed by implanting impurity ions of the first conductivity type into the channel forming region and the first impurity region forming region of the insulated gate field effect transistor.

By forming the second impurity region having a higher concentration than the substrate region between the first impurity region and the semiconductor substrate region, it is possible to suppress the expansion of the depletion layer width when a reverse bias voltage is applied. As a result, the electric field applied to the depletion layer can be increased, and junction breakdown can be caused with a low reverse bias voltage. As a result, the junction breakdown voltage is reduced, the amount of heat generated by Joule heat can be suppressed, and the generation of Al alloy spikes can be suppressed.

Further, by forming the second impurity region simultaneously with the ion implantation for adjusting the threshold voltage of the memory cell transistor, the junction breakdown voltage can be reduced without increasing the number of manufacturing steps.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 schematically shows an entire configuration of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, the semiconductor device includes a DRAM (Dynamic Random Access Memory).

In FIG. 1, a semiconductor device includes a memory cell array MA having a plurality of memory cells arranged in a matrix of rows and columns, an external address signal supplied from the outside via an address protection circuit APC, and a buffer. An address buffer AB for processing to generate an internal address signal, an X decoder ADX for decoding an internal address signal from the address buffer AB and selecting a corresponding row in the memory cell array MA, and an internal address signal from the address buffer AB. Includes Y decoder ADY for decoding and generating a column selection signal for selecting a corresponding column in memory cell array MA.

The semiconductor device further includes a sense amplifier for detecting and amplifying data of a memory cell connected to a selected row (word line) in the memory cell array MA;
It includes an I / O gate for connecting a corresponding column in memory cell array MA to output buffer OB according to a column selection signal from Y decoder ADY. In FIG. 1, the sense amplifier and the I / O gate are indicated by one block SI. The output buffer OB controls the block SI
, And external read data Dout transmitted to data output terminal Q via output protection circuit OPC is generated.

The semiconductor device further includes, as a peripheral circuit, a control signal generation system CG for generating a control signal for controlling various internal operation timings of the device. Control signal generating system CG receives externally applied control signals, that is, row address strobe signal / RAS, column address strobe signal / CAS, and write enable signal / WE via input protection circuit IPC. Peripheral circuits include an address buffer AB, X decoders ADX, Y
It may include a decoder ADY and a block SI.

The internal circuit to be protected by the protection circuit includes an address buffer AB and a control signal generation system CG for receiving and buffering an external signal from an external terminal, and an output for generating internal read data and outputting it to the external terminal. Includes buffer OB. Although not shown in FIG. 1, an input buffer is further provided for writing data, and this input buffer is connected to external terminal Q by output protection circuit OPC.
(The data input and output are performed through the same terminal), thereby protecting from an externally applied surge voltage (static electricity).

Control signal generating system CG includes a word line drive signal Rn transmitted on a selected row (word line) in memory cell array MA and a signal for precharging each internal node to a prescribed potential VB during a standby cycle. Is generated. This control signal generating system CG is shown to also generate a precharge potential VB for precharging internal nodes during a precharge cycle (standby cycle).

FIG. 2 shows the memory cell array M shown in FIG.
FIG. 2 is a diagram schematically showing a configuration of A. In FIG. 2, a memory cell array MA is arranged corresponding to a plurality of memory cells MC arranged in a matrix of rows and columns, and each row of the memory cells MC. Word lines (WL0-WLn)
And a plurality of bit line pairs BL,
ZBL (BL0, ZBL0 to BLm, ZBLm). Bit lines BL and ZBL are arranged in pairs,
Complementary data signals are transmitted to each other. The memory cell MC includes one word line WL and a pair of bit lines B
It is arranged corresponding to the intersection of L and ZBL. For example, memory cell MC is arranged corresponding to the intersection of word line WL0 and bit line BL0, and another memory cell M corresponding to the intersection of word line WL1 and bit line ZBL0.
C is arranged.

Bit line pair BL0, ZBL0-BLm, Z
Precharge / equalize circuits (P / E) PE0 to PEm for precharging and equalizing a corresponding bit line pair BL, ZBL to a predetermined potential VB in a standby cycle (precharge) corresponding to each of BLm.
Is arranged.

The block SI includes a bit line pair BL0, ZB
L0 to BLm, ZBLm are arranged corresponding to each,
Sense amplifiers SA0-SA for differentially amplifying and latching the signal potentials of bit line pair BL, ZBL corresponding to the activation
m and bit line pairs BL0, ZBL0 to BLm, ZBLm
The corresponding bit lines BL, BL are provided corresponding to the respective bit lines, and become conductive in response to a column selection signal from the Y decoder ADY.
An IO gate connecting ZBL to internal data transmission lines I / O and ZI / O is included. The IO gate is connected to the bit line pair BL.
i, ZBLi (i = 0 to m), and includes transfer gates Tia and Tib arranged correspondingly. A pair of transfer gates are simultaneously turned on in accordance with a column selection signal from Y decoder ADY. Thereby, a pair of bit lines are connected to internal data lines I / O and ZI / O.

Sense amplifiers SA0 to SAm receive sense amplifier activation control signals φA and φA transmitted through sense amplifier activation signal lines SADA and SADB, respectively.
Activated in response to B. Sense amplifiers SA0 to SA
The two sense amplifier activation control signals .phi.A and .phi.B are used for activating each of the sense amplifiers SA0 to SAm.
This is because it includes a P-sense amplifier composed of an OS transistor and an N-sense amplifier composed of a cross-coupled n-channel MOS transistor. The P sense amplifier raises the high potential bit line of the corresponding bit line pair BL, ZBL to the operating power supply voltage level, while the N sense amplifier lowers the corresponding low potential bit line of the corresponding bit line pair BL, ZBL. Discharge potential to ground potential level.

FIG. 3 is a diagram more specifically showing the structure of the memory cell and precharge / equalize circuit shown in FIG. In FIG. 3, typically, one word line WL
And a pair of bit lines BL and ZBL.

Precharge / equalize circuit PE is rendered conductive in response to precharge instructing signal φP, and precharge voltage V transmitted on precharge voltage transmission line SPE.
Transfer gates PEa and PEb transmitting B to bit lines BL and ZBL are included. Precharge / equalize circuit PE may further include a transistor that conducts in response to precharge instruction signal φP to electrically short bit lines BL and ZBL.

The memory cell MC conducts in response to the potential (word line drive signal Rn) on the word line WL and the memory cell capacitor MCA for storing information in the form of electric charge, and connects the memory cell capacitor MCA to the bit line BL. Or ZBL
Is connected to the access transistor MT. In FIG. 3, access transistor MT is shown connecting memory cell capacitor MCA to bit line BL. This access transistor MT has an n-channel MO
It is composed of S transistors. Bit lines BL and ZB
L has parasitic capacitances BPCa and BPCb, respectively. Memory cell capacitor MCA has one electrode connected to one conduction terminal of access transistor MT and the other electrode connected to receive a fixed reference potential Vcp. One electrode of memory cell capacitor MCA functions as a storage node for storing information. Reference voltage (cell plate voltage) V applied to the other electrode (cell plate) of memory cell capacitor MCA
cp is generated, for example, by dividing the operating power supply voltage VCI by resistance in a voltage generation circuit formed of a series body of resistors Ra and Rb. This operation power supply voltage VCI
May be a voltage generated by internally stepping down an external power supply voltage, or may be a power supply voltage provided externally without such an internal voltage down converter.

Normally, precharge voltage VB and cell plate voltage Vcp are each そ れ ぞ れ of power supply voltage VCI.
The voltage level is set to Next, the operation will be briefly described.

At the time of precharge (at the time of a standby cycle)
, The precharge signal φP is at the high level, the transfer gates PEa and PEb in the precharge / equalize circuit are both conductive, and the bit lines BL and ZBL are charged to the precharge voltage VB at the intermediate potential level. When an active cycle starts, precharge signal φP attains a low level, and transfer gates PEa and PEb both enter a non-conductive state. When a word line WL is designated by an address signal, a word line drive signal Rn is transmitted on the word line WL, the potential thereof rises, and the access transistor MT included in the memory cell MC is turned on. As a result, the memory cell capacitor MCA is connected to the bit line BL, and the potential of the bit line BL changes from the precharge voltage VB according to the data stored in the memory cell capacitor MCA. The amount of change in potential of bit line BL is determined by the ratio of the capacitance of memory cell capacitor MCA to the capacitance of parasitic capacitance VBCa connected to bit line BL. Since no memory cell is connected to bit line ZBL, precharge voltage VB is maintained (charged to parasitic capacitance BPCb).

Sense amplifier SA is then activated to detect, amplify and latch the potential difference appearing on bit lines BL and ZBL. Thereafter, a memory cell column addressed by a column address signal is selected according to a column selection signal from a Y decoder (see FIG. 1 or 2), and a memory cell arranged corresponding to the selected row and column is selected. Data writing or reading (access operation) is performed on the selected memory cell.

In the structure described above, the internal signals shown in FIG. 3 are all supplied with power supply voltage VCI and ground voltage Vss.
(GND) level. When the memory cycle (active cycle) is completed, word line drive signal Rn on word line WL drops to the level of ground potential GND. As a result, the memory access transistor MT is turned off. In addition, precharge instruction signal φP
Goes high, transfer gates PEa and PEb of the precharge / equalize circuit are rendered conductive, and bit lines BL and ZBL are precharged to the precharge voltage VB level of the intermediate potential level.

As the power supply voltage VCI is lowered, the MOS transistor as a component is scaled down to guarantee its operation characteristics. In this scale down, the threshold voltage Vth of the access transistor is not scaled down in accordance with the scaling rule for the following reason.

Generally, a MOS transistor is turned off when the potentials of its gate and source are equal.
However, in this state, current does not flow at all through the MOS transistor, but a current called "tail current (subthreshold current)" flows. Generally, the threshold voltage Vth is defined as a gate-source voltage when a MOS transistor having a predetermined gate width flows a drain current having a constant current value.

FIG. 4 is a graph showing the tail current characteristics of the n-channel MOS transistor. The vertical axis shows the drain current IDS flowing through the MOS transistor, and the horizontal axis shows the gate-source voltage VGS. As shown by the curve I1, in the case of the threshold voltage VTHL, the drain current IDS0 having a significant value flows even when the gate-source voltage VGS becomes 0V. This current I
In order to reduce DS0 to an almost negligible level, it is necessary to increase the threshold voltage to the value of VTHH. When the gate-source voltage VGS becomes higher than the threshold voltages VTHL and VTHH,
A large drain current IDS flows rapidly. Therefore, in order to make the MOS transistor conductive at high speed, it is preferable to use a MOS transistor having a threshold voltage as low as possible. The tail current characteristic of the p-channel MOS transistor is represented by a curve symmetrical to curves I1 and I2 with respect to the vertical axis shown in FIG. For high-speed operation, it is preferable to use a MOS transistor having a threshold voltage as low as possible (threshold voltage with a small absolute value). However, in the case of a semiconductor memory device, the following problem occurs when such a low threshold voltage MOS transistor is used as an access transistor of a memory cell.

Now, consider two memory cells MCa and MCb in the same column as shown in FIG. Memory cell MC
a is the memory cell capacitor MCAa and the word line WL
a in response to the potential on the memory cell capacitor M
Access transistor MTa connecting CAa to bit line BL is included. Memory cell MCb includes a memory cell capacitor MCAb and an access transistor MTb connecting memory cell capacitor MCAb to bit line BL in response to a signal potential on word line WLb.

Now, consider the operation of writing "0" (low level) data to memory cell MCb in a state where "1" (high level) data is stored in memory cell MCa. In this case, the potential on word line WLa is at the low level of ground voltage GND level, and the potential on word line WLb is at the high level (usually a voltage level higher than power supply voltage VCI (; threshold of access transistor MT). Value to prevent voltage loss)).

When writing data "0", bit line BL
Is set to the ground potential GND level. In this state, access transistor M of memory cell MCa
Ta has the same potential as the gate (word line WLa) and the potential at the source (bit line BL). Therefore, when a MOS transistor having a tail current characteristic as shown by curve I1 in FIG. 4 is used as access transistor MTa, a tail current flows from memory cell capacitor MCAa to bit line BL, and memory cell capacitor MCAa
, The amount of accumulated charge of the semiconductor device decreases. Therefore, the charge retention characteristics of the memory cell are degraded, and the reliability of the semiconductor memory device is impaired. The “1” stored in the memory cell MCa
Is changed to "0" data due to the charge loss due to the tail current, so that a semiconductor memory device that stores data accurately cannot be realized, and the reliability of the memory device is also impaired. It is.

Therefore, in this semiconductor memory device, as access transistor MT of the memory cell,
A MOS transistor whose threshold voltage is as high as possible and whose tail current is as small as possible is used. On the other hand, the address buffer AB shown in FIGS.
Peripheral circuits such as the X decoder ADX, the Y decoder ADY, and the control signal generation system CG are required to operate as fast as possible. Therefore, low threshold voltage MOS transistors having tail current characteristics as shown by a curve I1 in FIG. 4 are used as components of these peripheral circuits. Here, "low threshold voltage" indicates "threshold voltage having a small absolute value", and the absolute value of the threshold voltage of a p-channel MOS transistor is similarly reduced. The threshold voltage of the MOS transistor used in the peripheral circuit is actually set to an appropriate value in consideration of current consumption (current consumption in a standby cycle).
Therefore, in a semiconductor memory device, a MOS transistor having a low threshold voltage and a MOS transistor having a high threshold voltage (a threshold voltage having a large absolute value) are used. In the method of manufacturing MOS transistors having different threshold voltages, first, a MOS transistor having the same threshold voltage, that is, a low threshold voltage is formed in both the peripheral circuit and the memory cell array. Then, a P-type impurity such as boron is ion-implanted into the surface of the channel region of the gate electrode only for the access transistor of the memory cell to increase the P-type impurity concentration on the surface of the channel region of the access transistor. Threshold voltage is increased.

Therefore, a normal semiconductor memory device manufacturing process includes a manufacturing process for making the threshold voltage of an access transistor in a memory cell array portion different from that of a MOS transistor included in a peripheral circuit. Have been. In the present invention, utilizing this step, the junction breakdown voltage of the protection element included in the protection circuit is reduced, and the amount of heat generated by Joule heat is reduced. Hereinafter, a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings.

First, as shown in FIG. 6, a thin thermal oxide film (pad oxide film) 202 is grown on the surface of a low impurity concentration P-type semiconductor substrate 200 according to a thermal oxidation method. Next, a silicon nitride film 204 is deposited on this thermal oxide film 202 according to, for example, a CVD method (chemical vapor deposition method).
A layer insulating film is formed.

Next, as shown in FIG. 7, after forming a resist film on the silicon nitride film 204, the resist film is patterned according to a photolithography method to form a resist pattern 206. Using the resist pattern 206 as a mask, the silicon nitride film 204 is selectively etched away to expose a portion of the pad oxide film 204 which will be an element isolation region.

Next, as shown in FIG. 8, after removing the resist pattern 206, thermal oxidation is performed using the silicon nitride film 204 as a mask, and a thick silicon dioxide film (field oxide film: LOCOS) is selectively formed in the element isolation region. An oxide film 210 is grown. The method for forming an oxide film by this selective thermal oxidation is a local silicon oxidation method (LOCOS method).
Called. The field oxide film 210 also grows under the nitride film 204 during the thermal growth. Therefore, as shown in FIG. 8, the silicon nitride film 204 is partially lifted. The field oxide film 210 defines a MOS transistor formation region.

Under the thermal oxide film 210, a P-type impurity such as boron is ion-implanted before the LOCOS method in order to prevent the formation of a parasitic MOS transistor. A channel stopper region is formed below.

Next, as shown in FIG. 9, the unnecessary portions of the silicon nitride film 204 and the pad oxide film 202 are removed by etching to expose the surface of the semiconductor substrate 200.

Next, a process for actually manufacturing MOS transistors which are components of the memory cell array, the peripheral circuit and the protection circuit is started. In the following description of the manufacturing process, the following regions are assumed. In FIG. 10, a region 300 between field oxide films 210a and 210b is
It is used as an array area for forming a memory cell. In this region 300, an access transistor (n-channel MOS transistor) is formed. In a region 302 between field oxide films 210b and 210c, an n-channel MOS transistor forming a peripheral circuit is formed. As described above, the peripheral circuit is an internal circuit for controlling each access of the semiconductor memory device, and at a logic gate level, an inverter, a NAND gate,
And a NOR gate. This peripheral circuit includes an n-channel MOS transistor and a p-channel M transistor.
It includes both OS transistors. Field oxide film 210
Region 304 between c and 210d is used as a region for forming a p-channel MOS transistor included in this peripheral region.

A region 3 for forming a protection circuit is relatively close to the pad region outside the peripheral circuit region.
06 is provided. This region 306 is defined by field oxide films 210e and 210h. NP to form an NPN lateral transistor
To define the emitter region and the collector region of the N lateral transistor, a field oxide film 21 is formed.
0f and 210g are formed. The region between field oxide films 210f and 210g is used as a collector formation region of an NPN lateral transistor. The region between field insulating films 210e and 210f and the region between field oxide films 210g and 210h are used as emitter forming regions of the NPN lateral transistor.

First, as shown in FIG. 10, a resist film 212 is formed over the entire surface of the semiconductor substrate 200 by, for example, a spin coating method, and then a resist pattern is formed by a photolithography method. Thereby, the surface of the peripheral circuit formation region 304 is exposed. In this state, N-type impurities such as phosphorus having a concentration of about 1 × 10 ¹³ cm ⁻³ are ion-implanted at an energy of about 1000 KeV, and relatively low impurities are implanted into the surface of the peripheral circuit formation region 304 of the P-type semiconductor substrate 200. N well 2 of concentration
15a are formed. N well 215a functions as a substrate region for a p-channel MOS transistor included in peripheral circuit formation region 304. Another N-well separates the protection circuit from other internal circuits, prevents diffusion of minority carriers to peripheral circuits when a surge voltage (high voltage such as static electricity) is applied, and protects to prevent latch-up phenomenon It may be formed so as to cover the circuit formation region 306.

Next, as shown in FIG. 11, after removing the resist pattern 212, a resist film is formed again.
Resist pattern 21 according to photolithography
4 is formed. The resist pattern 214 covers the peripheral circuit formation regions 302 and 304 and exposes the surfaces of the access transistor formation region 300 and the protection circuit formation region 306 of the memory array. In this state,
Under an acceleration condition of 700 KeV, an impurity concentration of 1 × 10 ¹³ cm
A P-type impurity such as boron having a concentration of about ^-3 is ion-implanted to form a P-well. Memory cell array formation area 3
00, a P well 220a is formed, and in the protection circuit formation region 306, P wells 220b, 220
c and 220d are formed. Next, in order to increase the threshold voltage of the access transistor of this memory array, a P-type impurity such as boron is ion-implanted at an energy of about 50 KeV and a concentration of about 1 × 10 ¹² cm ⁻³ .
The ion implantation of the P-type impurity of, for example, boron is performed in memory cell array formation region 300 and protection circuit formation region 3.
06. Thereby, the P-type impurity concentration on the surfaces of P wells 220a to 220d in memory array formation region 300 and protection circuit formation region 306 is increased. By this two-stage ion implantation, the threshold voltage of the access transistor formed in memory cell array formation region 300 is about 0 lower than the threshold voltage of the n-channel MOS transistor of the peripheral circuit formed in peripheral circuit formation region 302. .3V higher.

FIG. 12 is a graph showing the results of a simulation of the distribution of impurity ions (activating ions) from the substrate surface of the P well during the implantation of impurity ions under the above conditions. In FIG. 12, the horizontal axis indicates the distance from the substrate surface (unit: μm), and the vertical axis indicates the impurity ion concentration (activation ion concentration) (unit: cm ⁻³ ). In FIG. 12, the impurity ion concentration distribution of the N-type impurity region at the time of forming the LDD structure, which will be described later, is also represented by curve S
3 and S4 (phosphorus and arsenic). In FIG. 12, curve S1 shows the impurity ion concentration when P-type boron ion implantation (channel doping) for increasing the threshold voltage of the access transistor in the memory cell array is not performed, and curve S2 shows this impurity ion concentration. 4 shows an impurity ion (boron ion) distribution when boron for increasing a threshold voltage is doped into a channel region.

As shown in FIG. 12, when boron ion implantation (channel doping) for increasing the threshold voltage is performed, the impurity ion concentration on the substrate surface is high. In addition, the implanted boron is N
It is implanted deeper than the ⁺ type impurity ions (As, P), and a high concentration P / N junction is reliably formed. As described above, the junction breakdown voltage of the PN junction decreases as the P-type impurity ion concentration increases (NA ^{−3/4 to} NA ⁾ .
^-2/5 ). Here, NA indicates the acceptor concentration.
Therefore, by further implanting boron, which is the P-type impurity ion, into the surface of the P-well, the concentration of the P-type impurity ion in the junction region of the P-well increases,
Junction breakdown voltage is lower. This is because when the P-type impurity ion concentration increases, the spread of the depletion layer decreases, and a large electric field is applied to the depletion layer with a small voltage, so that avalanche breakdown easily occurs in the depletion layer (depletion). The width D of the layer is proportional to the reverse bias voltage Vr, and is proportional to NA ^-1/2 to NA ^-1/3 with respect to the P-type impurity ion concentration NA).

Therefore, by increasing the impurity ion concentration on the surfaces of P wells 220b-220d in protection circuit formation region 306 in the same manufacturing process as channel doping for increasing the threshold voltage in this memory cell array, The junction breakdown voltage of an NPN lateral transistor to be formed later is reduced, the avalanche current is also relatively small, the amount of heat generated by Joule heat can be reduced, and the Al alloy spike caused by eutectic aluminum and silicon is reduced. Growth can be suppressed, and junction breakdown can be suppressed.

Further, by suppressing this heat generation, A
(1) The diffusion of silicon Si into aluminum wiring during the growth of alloy spikes can be suppressed, the generation of silicon nodules can be suppressed, the wiring resistance can be suppressed accordingly, and surges, which are abnormal voltages such as static electricity, can be suppressed. Disconnection due to heat generation of the aluminum wiring when voltage is applied can be prevented, and a highly reliable protection circuit can be realized.

In the simulation results shown in FIG. 12, the junction breakdown voltage is reduced from 15.9 V to 14.1 V when channel doping is performed, the power consumption at the time of junction breakdown is reduced, and the amount of heat generated is reduced. It was seen to decrease.

Next, as shown in FIG. 13, after removing the resist pattern 214 formed on the peripheral circuit formation regions 302 and 304, a film thickness of 1
An oxide film 216 of about 50 ° is formed.
Low-resistance polysilicon doped with impurities
It is deposited according to the D method or the like. Thereafter, a resist pattern is formed on the polysilicon film according to a photolithography method, and the polysilicon and the oxide film are selectively removed by etching using the resist pattern as a mask. Thus, a gate electrode structure of a MOS transistor having gate oxide film 216 and gate electrode 218 is formed in each of regions 302, 303, and 304.

Here, oxide film 216 may be another insulating film (for example, a silicon nitride oxide film). Further, the gate polysilicon film 218 may be replaced with a high melting point silicide metal layer such as molybdenum silicide.

Then, as shown in FIG. 14, first, a peripheral circuit region 30 in which a p-channel MOS transistor is formed
4 is covered with a resist pattern 209, and an N-type impurity such as phosphorus is
Ion implantation is performed at a concentration of 2 × 10 ¹³ cm ^-3 under KeV acceleration conditions. Thus, in regions 300 and 302, relatively high-concentration relatively high-concentration N-type (N ⁻ -type) impurity regions 222 are formed in a self-aligned manner using the gate electrode structure formed of oxide film 216 and polysilicon film 218 as a mask. Is done. Boron ions implanted during channel doping are implanted deeper than the implanted phosphorus. This allows
As shown in FIG. 15A, in the region 300, P ⁻
A higher concentration P well 221 is formed on the well 220a.
a is formed.

Similarly, in protection circuit formation region 306, phosphorus ions are implanted, and P well 220 whose impurity concentration is relatively increased by a channel doping step is formed.
N ⁻ -type impurity regions 222b are formed on the surfaces of b, 220c and 220d. The N ⁻ -type impurity region 222 b formed by the phosphorus ion implantation is
b, 220c and 220d (FIG. 12)
The boron ion implantation depth is deeper than the phosphorus implantation depth as shown in FIG. Therefore, this protection circuit formation region 30
Also in the case of No. 6, a PN junction having a higher concentration is formed as compared with the related art, and a reduction in breakdown voltage at the time of junction breakdown is guaranteed, and heat generation at the time of junction breakdown is reduced.

Next, as shown in FIGS. 15A and 15B, arsenic As was accelerated to 4 × 10 4 under the acceleration condition of 50 KeV.
Ion implantation is performed at a concentration of ¹⁵ cm ^-3 . As shown in FIG. 15A, in the memory cell formation region 300 and the peripheral circuit formation region 302, the high-concentration N is formed in a self-aligned manner using the gate electrode structure (using the sidewall insulating film) as a mask.
⁺ Type impurity region 224a is formed on the surface of N ⁻ type impurity region 222b. This is because, as shown in FIG. 12, the ion implantation depth of arsenic As is shallower than that of phosphorus. As a result, in the access transistor of the memory cell, an LDD (Lightly Doped Drai
n) The structure is realized, and even when the access transistor is miniaturized, the high electric field of the drain is alleviated, and the generation of hot electrons and the destruction of the drain junction are prevented.

At this time, as shown in FIG. 15B, in the protection circuit forming region 306, the arsenic ions are implanted under the same conditions using field oxide films 210e, 210f, 210g and 210h as masks. As a result, a high concentration N ⁺ -type impurity region 224b containing arsenic is formed on the surface of the N ⁻ -type impurity region 222b. In the protection circuit forming region ^{306, N + / N - / P} / P
^-A mold joining structure is formed. Since the N-type impurity region has a double diffusion structure, the depletion layer can be formed in the N-type impurity region 22.
2b and 224b, P well 2
A large electric field is prevented from being applied between the depletion layers in 20b and 220c, and a depletion layer is spread between the N ⁺ impurity region 224b and the P ^- wells 220b and 220c, and a high electric field is applied between them. This alleviates the peak electric field applied to the depletion layer, reduces the junction breakdown voltage, and reduces the peak electric field.
Prevent joint breakage.

Next, as shown in FIG. 16, after removing the resist pattern 220, a resist film is formed again, and then the n-channel MOS is formed according to the photolithography method.
The resist pattern 2 covers the regions 300 and 304 where the transistors are formed and the protection circuit formation region 306.
25 are formed. In this state, p-channel MOS transistor formation region 304 of the peripheral circuit, ie, N
The well 215a is exposed. In this state, a P-type impurity such as boron is ion-implanted, and a low-resistance high-concentration P-type impurity region 226 is formed in the N well 215a in a self-aligned manner. Thus, source / drain regions of the p-channel MOS transistor are formed in region 304.

Thereafter, after removing the resist pattern 225, necessary electrode wirings are formed by patterning, whereby a required semiconductor memory device is formed.

In the first embodiment, region 30 for forming an n-channel MOS transistor of the peripheral circuit is formed.
2, an n-channel MOS transistor is formed on the surface of a P-type semiconductor substrate 200. In this peripheral circuit formation region 302, P
A well may be formed.

In the protection circuit formation region 306, a protection element is formed on the surface of the P-type semiconductor substrate 200. However, this protection circuit formation region 306
In P, surrounding these protection element formation regions, P
A well may be formed. Further, an N-well is formed so as to surround the entire protection circuit formation region 306, thereby preventing minority carriers from flowing to peripheral circuits during operation of the protection circuit, thereby preventing a latch-up phenomenon in the peripheral circuits. It may be configured as follows.

Further, a triple well structure in which a well region of the second conductivity type is further formed in the well region of the first conductivity type and a MOS transistor is formed in the well region of the second conductivity type may be used. Good.

As described above, according to the first embodiment of the present invention, in order to protect the internal circuit from a surge voltage (abnormal voltage) such as static electricity from the outside, this protection element includes:
Since a PN junction having a relatively high concentration is formed, the junction breakdown voltage can be reduced.
Accordingly, the amount of heat generated by the junction breakdown voltage at this junction can be reduced.

In order to form this high-concentration PN junction, a high-concentration P-type region (P-type) region is formed by using the same step as the ion implantation step for increasing the threshold voltage of the memory cell transistor. Therefore, it is possible to realize a protection element with reduced junction breakdown voltage without increasing the number of manufacturing steps.

[0090] Further, this protection device similar to the LDD structure N ^{+ /} N ^- / P - because of the structure, it is possible to relax the peak electric field applied to the depletion layer at the time of junction breakdown, the PN junction Destruction can be prevented.

[Second Embodiment] FIG. 17A shows a structure of a main portion of a semiconductor device according to a second embodiment of the present invention. In FIG. 17A, a static random access memory (SR
AM) shows a configuration of a memory cell included in the memory cell. FIG.
In (A), the SRAM cell includes an n-channel MOS transistor Q1 connected between a storage node SN1 for storing information and a ground node Vss and a gate connected to the storage node SN2, a storage node SN2 and a ground node Vss. And a high resistance element R1 connected between a power supply node supplying power supply voltage Vcc and storage nodes SN1 and SN2, respectively, and an n-channel MOS transistor Q2 having a gate connected to storage node SN1. And R2
In response to a signal potential on word line WL, and connects storage nodes SN1 and SN2 to bit line B, respectively.
Includes n-channel MOS transistors Q3 and Q4 connected to L and ZBL.

In the SRAM cell, data is stored in storage nodes SN1 and SN2 by a flip-flop including MOS transistors Q1 and Q2. When H-level data is stored in storage node SN1, MOS transistor Q2 is turned on, storage node SN2 is pulled down to the ground potential level, and MOS transistor Q1 is turned off. Storage node SN1 is pulled up to power supply voltage Vcc level via resistance element R1. On the other hand, storage node SN2 is connected to MOS transistor Q
2 is pulled down to the ground voltage level. In this state, in order to prevent a large current from flowing from the power supply node to the ground node via resistance element R2 and MOS transistor Q2, resistance element R2 has a sufficiently large resistance value. On the other hand, when MOS transistor Q1 is turned off, storage node SN1 is electrically separated from the ground node. However, a tail current flows in MOS transistor Q1. When storing L-level data, the operation described above is reversed. To prevent this tail current, the threshold voltages of MOS transistors Q1 and Q2 are set to be about 0.3 V higher than the threshold voltages of MOS transistors of other peripheral circuits.

The threshold voltage of MOS transistors Q1 and Q2 is set higher than that of the MOS transistor of the peripheral circuit, as in the case of the DRAM cell.
This is performed by implanting P-type impurity ions into the channel regions of transistors Q1 and Q2. Simultaneously with the implantation of the P-type impurity ions into the channel region,
Similarly to the above, P-type ions are implanted into the emitter / collector formation region of the NPN lateral transistor of the protection element included in the protection circuit. Thereby, the first embodiment is performed.
Similarly to the above, in the SRAM cell, the junction breakdown voltage is reduced without increasing the number of manufacturing steps, and a stable protection circuit with small heat generation can be realized.

In the case of the SRAM cell of FIG. 17A, when writing / reading data, word line WL is raised to the H level of the selected state, and MOS transistors Q3 and Q4 are turned on.
Are turned on and storage nodes SN1 and SN2
Is electrically connected to bit lines BL and ZBL. At the time of data reading, a potential difference corresponding to the information of storage nodes SN1 and SN2 occurs on bit lines BL and ZBL, and the potential difference is amplified by a sense amplifier. At the time of data writing, write data is applied via bit lines BL and ZBL, and the potentials of storage nodes SN1 and SN2 are set to potential levels corresponding to the write data.

[Modification] FIG. 17B shows a structure of a modification of the SRAM cell according to the second embodiment of the present invention. In the SRAM cell shown in FIG.
As a pull-up resistance element, a thin film transistor (TF
T), p-channel MOS transistors Q5 and Q6 are provided. The other structure is the same as that of the SRAM cell shown in FIG. 17A, and corresponding portions are denoted by the same reference characters. MOS transistor Q5 is connected between the power supply node and storage node SN1, and has its gate connected to storage node SN2. MOS transistor Q6 is connected between the power supply node and storage node SN.
2 and its gate is connected to the storage node S
Connected to N1.

By using thin film transistors as MOS transistors Q5 and Q6, transistors Q5 and Q6 can be arranged above the memory cell transistors, and a load element with a small occupation area can be realized. MO
When the gates of S transistors Q5 and Q6 attain an H level, they are turned off, and provide a sufficiently high resistance value as compared with a normal resistance element. Thereby, a leak current can be suppressed. However, in MOS transistors Q1 and Q2, a current is supplied to an off-state MOS transistor via on-state MOS transistor Q5 or Q6. Therefore, also in this configuration, the threshold voltage of MOS transistor Q1 or Q2 in the off state is increased in order to reduce the tail current. In order to increase the threshold voltage, P-type impurity ions are implanted into the channel region as in the structure shown in FIG. Therefore, even in the configuration using the thin film transistor shown in FIG.
In order to raise the threshold voltage of Q2 and Q2, a P-type ion implantation step is required. In the same step as the P-type ion implantation step, P-type ion implantation is performed on the emitter / collector formation region of the NPN lateral transistor included in the protection circuit. As a result, the junction breakdown voltage of the NPN lateral transistor can be reduced without increasing the number of manufacturing steps. The manufacturing process is substantially the same as in the first embodiment.

As described above, according to the second embodiment of the present invention, the NPN of the protection circuit is formed in the same step as the P-type impurity ion implantation step for increasing the threshold voltage of the memory cell transistor of the SRAM cell. Since the P-type ion implantation is performed into the emitter / collector formation region of the lateral transistor, a transistor for protecting against static electricity (surge voltage; abnormal voltage) without increasing the number of manufacturing steps as in the first embodiment. The junction breakdown voltage can be reduced, the amount of heat generated by the junction breakdown voltage can be reduced accordingly, junction leakage current and junction destruction can be prevented, and a highly reliable protection circuit can be realized. be able to.

[Third Embodiment] FIG. 18 shows a structure of a memory cell which is a component of a semiconductor device according to a third embodiment of the present invention. In FIG. 18, the semiconductor device includes an electrically erasable and erasable memory cell (flash memory cell). In FIG. 18, the flash memory cell includes high-concentration N-type impurity regions 252a and 252a formed on the surface of P-type semiconductor substrate 250 with a space therebetween.
52b, a floating gate 254 formed on the surface of the channel region 253 between the impurity regions 252a and 252b via an insulating film, and a control gate 256 formed on the floating gate 254 via an interlayer insulating film. Including. Control gate 256
Are connected to a word line WL. Impurity region 252a
Is connected to the bit line BL, and the impurity region 252b is connected to the source line SL.

The flash memory cell stores information according to the amount of charge (electrons) stored in the floating gate 254. The operation of injecting and extracting electrons into and from the floating gate 254 is called an erase and write operation. Either a state where electrons are injected into the floating gate 254 or a state where electrons are extracted from the floating gate 254 is defined as an erased state. Which is called, and which is called a write state, is determined by specifications. There are various operation mechanisms for injecting / extracting electrons into / from the floating gate 254, and injecting / extracting electrons between the substrate 250 and the floating gate 254, and floating the source line SL via the impurity region 252b. There are extraction of electrons from the gate 254 and injection of electrons from the bit line BL to the floating gate 254 through the impurity region 252a.

Now, as shown in FIG. 19, the state where electrons are injected into floating gate 254 is made to correspond to the state where information "0" is stored. In this state, since a large number of electrons are present in the floating gate 254, the threshold voltage shifts to a higher value of Vth2. On the other hand, when the state where electrons are extracted from the floating gate 254 is associated with information “1”, in this state,
The amount of electrons existing in the floating gate 254 is small, and its threshold voltage shifts to Vth1, which is lower. Reading of information from a flash memory cell is performed by applying a read voltage between threshold voltages Vth1 and Vth2 to a corresponding word line. When the information “0” is stored, the flash memory cell is in the off state, and no current flows from the bit line BL to the source line SL via the flash memory cell. On the other hand, information "1"
When a read voltage is applied, the flash memory cell is turned on, and a current flows from bit line BL to source line SL. Information is read out by detecting the presence or absence of a current in the bit line BL.

Now, as shown in FIG. 19, word line WL1
And WL2 are connected to memory cells M1 and M2, respectively, and these memory cells M1 and M2 are connected between bit lines BL and SL. In this case, it is assumed that the memory cell M2 has a drain current characteristic as shown by a broken line in FIG. That is, consider a state where the threshold voltage is extremely low. When word line WL1 is selected, its voltage level rises to H level, while word line WL2 is in a non-selected state and its voltage level is "L". When the memory cell M1 stores information "0", the bit line BL is connected via the memory cell M1.
No current flows from the source line SL to the source line SL. On the other hand, since the threshold voltage of the memory cell M2 is sufficiently low, a leak current flows through the memory cell M2 regardless of the unselected word line WL2. Therefore, a current flows through bit line BL due to this leak current, and data "0" stored in memory cell M1 is erroneously read as "1". In order to prevent such a leak current, the threshold voltage of the flash memory cell storing the information "1" is set to a value as high as possible (to prevent so-called "over-erase"). In order to satisfy this condition, P-type impurity ions are implanted into the channel region 253 (see FIG. 18) before injecting / extracting charges (electrons) to / from the floating gate 254, and the initial threshold of the flash memory cell transistor is increased. The value voltage is set higher than the threshold voltage of the MOS transistor of the peripheral circuit. As a result, the threshold voltage of the memory cell storing the information “1” is prevented from becoming too low, and the occurrence of a so-called “over-erase” abnormality is suppressed.

Therefore, also in the flash memory, at the same time as the P-type impurity ion implantation step for making the initial threshold voltage of the flash memory cell higher than the threshold voltage of the MOS transistor of the peripheral circuit, the NPN lateral of the protection circuit is By simultaneously implanting P-type ions into the emitter / collector regions of the transistor, a reduction in the junction breakdown voltage of the NPN lateral transistor of the protection circuit can be realized without increasing the number of manufacturing steps. The manufacturing process is substantially the same as that of the first embodiment except that the flash memory cell transistor has a stacked gate structure.

In the structure of the flash memory cell, as a structure for preventing disturbance due to a high electric field at the time of writing, an SSW-DSA (Symmetrical Sidewall-Diffusion Self
There is an element structure called an alignment) structure. In this configuration, both the source region and the drain region
It has an LDD structure. Therefore, like the LDD structure of the flash memory cell, the N-type impurity region of the NPN lateral transistor can also have the LDD structure.
In this SSW-DSA structure, the drain /
In order to suppress a high electric field of the source, a P ⁺ region (P pocket) region is formed so as to cover the source and drain regions. Therefore, this P pocket region forming step
The same step as the step of forming the P well of the emitter / collector region of the NPN lateral transistor can be employed.

As described above, according to the third embodiment of the present invention, even in a semiconductor device having a flash memory cell, an impurity implantation step for adjusting a threshold voltage to a channel region of the flash memory cell transistor is performed. In the same process as that described above, ions are implanted into the junction of the NPN lateral transistor for electrostatic protection.
Junction breakdown can be reduced, the amount of heat generated at the junction of the NPN lateral transistor can be reduced accordingly, and a highly reliable protection circuit can be realized.

[Fourth Embodiment] FIG. 21A schematically shows a sectional structure of a protection element of a semiconductor device according to a fourth embodiment of the present invention. In FIG. 21A, a protection element for protecting an internal circuit against an abnormal voltage such as static electricity is formed on the surface of a low-concentration P-type (P ⁻ ) semiconductor substrate 300 and has a higher concentration than the substrate 300. P type (P
^- ) Formed on the surface of the mold well 310. This P-well 3
The area 10 is defined by the field oxide film 316. The protection element is formed on the surface of P well 310, and has a P type impurity region 320 having a higher impurity concentration than P well 310 and a low concentration N type (N type) formed to be surrounded by P type impurity region 320. ^- ) ^- Type impurity region 320 and a high-concentration N-type impurity region 324 formed on the surface of the N-type impurity region 320.

P-type impurity region 320 is formed in the same step as channel doping for adjusting the threshold voltage of the memory cell transistor, as in the first embodiment. N ⁻ -type impurity region 322 and N ⁺ -type impurity region 324 are formed in the same step as the step of introducing phosphorus and arsenic, respectively, when forming the source / drain regions of the memory cell transistor. By forming this P-type impurity region 320, as shown in FIG.
The PN junction depth becomes shallower than the configuration in which 20 is not provided (see the intersection of the curves S3 and S2 and the intersection of the curves S3 and S1 in FIG. 12). Therefore, this P
At the time of N-junction breakdown, current flows along the surface region of P well 310, and the amount of current flowing in the direction of substrate 300 can be reduced.

The protection device further includes a P well 310
It includes a high-concentration P-type impurity region 330 formed separately from the P-type impurity region 320 via a field oxide film 317. This high-concentration P-type impurity region 330 is formed in the same step as the boron ion implantation step for forming the source / drain regions of the p-channel MOS transistor of the peripheral circuit. Impurity region 324 is electrically connected to external terminal 1, and impurity region 330 is connected via wiring 319 so as to receive a ground potential.

FIG. 21B shows an electrical equivalent circuit of the protection element shown in FIG. As shown in FIG. 21B, this protection element is equivalent to a diode 335 having a cathode connected to external terminal 1 and an anode connected to receive a ground potential.

When static electricity is applied to external terminal 1, P formed between impurity region 324 and P well 310 is removed.
A high voltage is applied to the N junction, causing junction breakdown. At this time, as in the first embodiment, in the PN junction, the impurity concentration of the P-type impurity region is higher than in the conventional case, and the junction breakdown voltage is lower than in the conventional case. The current generated in the P-well 310 due to this junction breakdown is almost equal to the P-well 31 due to the shallow junction.
Through the zero surface region, it flows into the P-type impurity region 330, and is discharged to the ground potential level via the wiring 319. Thereby, static electricity is absorbed. When negative static electricity is applied, the PN junction is biased in the forward direction, and the PN diode conducts and absorbs static electricity.

As shown in FIG. 21A, the PN die
Even if an ode is used as a protection element, it is the same as in the first embodiment.
The effect of can be obtained. In particular, this PN junction is⁺
/ N ^-/ P structure enables junction breakdown
Voltage can be reduced and junction breakdown occurs
Can be reduced.

[Fifth Embodiment] FIG. 22A schematically shows a sectional structure of a protection element of a semiconductor device according to a fifth embodiment of the present invention. In FIG. 22A, a protection element is a P-type (P ⁻ ) semiconductor substrate 35 having a low impurity concentration.
The substrate 350 is formed on the surface of a P-type (P ⁻ ) well 352 having an impurity concentration higher than that of the substrate 350. The protection element is a well 3 formed on the surface of the P well 352.
A P-type impurity region 354a having an impurity concentration higher than 52;
Low-impurity-concentration N-type (N ⁻ ) impurity regions 356a and 356b formed on P-type impurity region 354a with a space therebetween, and N ⁻ -type impurity regions 356a and 356
high-concentration N-type (N ⁺ ) impurity region 358 formed on
a and 358b and impurity regions 354a and 354
and a gate electrode layer 360 formed on the surface of the channel region 359 between the gate electrodes b through a gate insulating film (not shown).

The P-type impurity region 354a is formed in the same step as the P-type impurity ion implantation for adjusting the threshold value of the memory cell transistor, as in the first to fourth embodiments. The gate electrode layer 360 is formed in the same step as the step of manufacturing the gate electrode structure of the memory cell transistor. N ^-
Type impurity regions 356a and 356b and N ⁺ type impurity regions 358a and 358b are formed in the same manufacturing process as the source / drain formation regions of the memory cell transistor and the n-channel MOS transistor of the peripheral circuit, respectively.

Impurity region 358a is electrically connected to receive ground voltage Vss, and
Are electrically connected to the external terminal 1. Gate electrode layer 3
60 is electrically connected to gate electrode node 361. Gate electrode node 361 is connected to receive a predetermined voltage (power supply voltage or ground voltage) or an internal input signal depending on the application to be used, although the connection relationship will be described later.

The protection element shown in FIG. 22A is substantially a MOS transistor. The length of the gate electrode layer 360 in the channel direction is relatively long so that punch-through does not occur (so that a depletion layer is not continuously formed between the impurity regions 354a and 354b). In the configuration of this MOS transistor, as shown by a broken circle in the figure, a parasitic region having impurity region 358a as an emitter region, impurity region 358b as a collector region, and P ⁻ well 352 (and P ⁻ substrate 350) as a base. A bipolar transistor (NPN lateral transistor) is formed.

FIG. 22B shows an electrical equivalent circuit of the protection element shown in FIG. As shown in FIG. 22B, protection element 365 has one conduction terminal connected to external terminal 1 and the other conduction terminal connected to receive ground voltage Vss. The connection destination of the gate electrode node differs depending on the application. In this case, as shown by the broken line,
A parasitic NPN bipolar transistor based on the substrate region is formed using one and the other conduction terminals of the MOS transistor as a collector and an emitter, respectively. In the fifth embodiment, the parasitic bipolar transistor is turned on when a surge voltage such as static electricity is applied, and an abnormal voltage such as static electricity is discharged. That is, when an abnormal voltage such as static electricity is generated at external terminal 1, breakdown occurs at the PN junction between N ⁺ impurity region 358b and P ^- well 352, and the avalanche current in the depletion layer is reduced to P ^- well 352. And P ^-- flow to the substrate 350. P ^- The substrate resistance in the well 352, the P ^- potential of the well 352 increases, the emitter / base is forward biased, the parasitic NPN bipolar transistor is rendered conductive, static electricity impurity regions 358 provided on the external terminal 1 To the level of the ground voltage Vss. Also in the configuration shown in FIGS. 22A and 22B, the PN junction has an N ⁺ / N ⁻ / P / P ⁻ structure, the expansion of the depletion layer width is suppressed, and the structure is relatively high. Junction breakdown occurs at a low voltage, and the amount of heat generated by the breakdown voltage can be reduced. In the case of negative static electricity, the well 352 and the impurity region 358b are biased in the forward direction, and the parasitic bipolar transistor conducts using the region 358b as an emitter.

In the case of using the MOS transistor shown in FIG. 22A as a protection element, channel region 3
There are cases where there is ion implantation for 59 and cases where it is not.

That is, as shown in FIG. 23A, in the protection element, P-type impurity ions are not implanted into the channel region below gate electrode layer 360. P-type impurity regions 354a and 354b are formed to surround N-type impurity regions 356a and 356b and 358a and 358b. In order to prevent channel doping via the gate electrode layer 360, a stopper material such as a resist film that inhibits ion implantation may be provided in the gate electrode layer 360 during P-type impurity ion implantation. In the structure of the protection element shown in FIG. 23A, no P-type impurity ions are implanted into the channel region below gate electrode layer 360. The threshold voltage is the same as the threshold voltage of the n-channel MOS transistor of the peripheral circuit, and has a low threshold voltage.

On the other hand, in the protection element shown in FIG. 23B, P-type impurity ions are implanted into gate electrode layer 360.
This is also performed for the lower channel region 359. Therefore, in the structure shown in FIG. 23B, impurity regions 354a and 354b are connected by impurity ions implanted into the surface of channel region 359. The P-type impurity ion implantation shown in FIG.
Similar to the channel doping of the memory cell transistor, it may be performed in a self-aligned manner with respect to gate electrode layer 359, and P-type impurity ions are also implanted into channel region 359 at that time. In the protection element having the structure shown in FIG. 23B, therefore, the threshold voltage Vth is increased, similarly to the memory cell transistor.

These threshold voltages correspond to the MOS of the peripheral circuit.
The same protection element as the transistor and the memory cell transistor is used in an appropriate place according to the threshold voltage. The configuration for changing the portion used according to the threshold voltage will be described later in detail.

In the structure in which the MOS transistor is used as a protection element in the fifth embodiment, the channel length is relatively long, junction breakdown occurs before punch-through occurs, and parasitic NPN lateral transistor occurs. Is turned on first, and discharges surge voltage (abnormal voltage) such as static electricity.

As described above, according to the fifth embodiment of the present invention, a MOS transistor is used, and the parasitic lateral bipolar transistor of the MOS transistor is used as a protection element. Similar effects can be obtained. Also in this case, the drain and source electric fields of the MOS transistor are relaxed by the LDD structure, and the breakdown of the gate insulating film is prevented. On the other hand, this high-concentration PN junction lowers the junction breakdown voltage, and can reduce the amount of heat generated during the junction breakdown.

[Embodiment 6] Each application of the protection element formed according to the present invention will be specifically described below.

[Application Example 1] FIG. 24 is a diagram showing a first application example of the protection element of the present invention. Referring to FIG. 24, an NPN lateral transistor QT according to the present invention is connected to a power supply node Vcc and an external terminal 1 by a wiring 1 electrically connected thereto.
1 is provided. This NPN lateral transistor QT is a transistor in which the emitter / collector region is separated by the field insulating film described in the first embodiment. Therefore, the base of NPN lateral transistor QT is connected to substrate region (P well / P type semiconductor substrate) 400. This wiring 11 is connected to the resistance element 6
Is connected to the gate of an n-channel MOS transistor 4 included in the internal circuit 2.

The internal configuration of internal circuit 2 is determined according to the function of each buffer circuit shown in FIG. Resistive element 6 delays the propagation of a surge voltage (abnormal voltage) such as static electricity applied to external terminal 1 in the same manner as the conventional input protection circuit shown in FIG. The response of the transistor 4 is delayed. As described above, before an abnormal voltage such as static electricity is transmitted to the internal circuit 2, the protection NPN lateral transistor QT discharges. In the configuration shown in FIG. 24, NPN lateral transistor QT discharges wiring 11 to a voltage level of Vcc + Vf (in the case of positive static electricity). Here, Vf is a forward drop voltage of the PN junction of the NPN lateral transistor. on the other hand,
Negative static electricity is charged to the level of -Vf.

According to the configuration shown in FIG. 24, static electricity applied to external terminal 1 can be discharged at a high speed.
At this time, since the discharge is performed at a relatively low junction breakdown voltage, it is possible to reliably prevent an abnormal voltage such as static electricity from adversely affecting the internal circuit 2.

[Application Example 2] FIG. 25 is a diagram showing a second application example of the protection element according to the present invention. In the configuration shown in FIG. 25, PN junction diodes DP1 and DP2 generated according to the fourth embodiment are used. The PN diode DP2 has a cathode connected to the power supply node Vcc and an anode connected to the signal line 11. The PN diode DP1 has its cathode connected to the wiring 11,
Its anode is connected to ground voltage node Vss.

When a positive abnormal voltage (static electricity) is applied, PN diode DP1 causes a junction breakdown and discharges a large positive voltage at external terminal 1 to the ground voltage level. In contrast, this diode DP2
Discharges the voltage reduced by the discharge of diode DP1 to power supply node Vcc. Therefore, the positive high voltage of signal wiring 11 is discharged to the level of Vcc + Vf.

When negative static electricity is applied, the negative static electricity is discharged to the power supply node due to the junction breakdown of the PN diode DP2. Next, PN diode DP1 charges the negative static electricity to the level of ground potential Vss. Therefore, the potential of signal wiring 11 is discharged by diode DP1 to the level of ground voltage Vss-Vf. Here, Vf is the PN diode DP
1 shows the forward drop voltage of the PN junction of DP2.

[Application Example 3] FIG. 26 is a diagram showing a configuration of a protection element according to a third application example of the present invention. In FIG. 26, a MOS transistor QT1 is connected between signal wiring 11 and a ground node, and an MOS transistor QT1 is connected between wiring 11 and a power supply node.
OS transistor QT2 is connected. These MOS
Transistors QT1 and QT2 have their source / drain regions and channel regions implanted with P-type impurity ions (see FIG. 23B).

The gates of MOS transistors QT1 and QT2 are connected to the ground node via resistance elements RT1 and RT2, respectively. Resistance elements RD1 and RD2
Delays the transmission of the static electricity to the gates of the MOS transistors QT1 and QT2 via the gate capacitance when the static electricity is applied to the external terminal 1. This prevents the gate insulating film from being broken when static electricity (abnormal voltage) is applied to MOS transistors QT1 and QT2.

In the arrangement shown in FIG. 26, MOS
In the transistors QT1 and QT2, the collector terminals of the parasitic bipolar transistors are connected to the signal wiring 11. When a positive abnormal voltage (static electricity) is applied to the external terminal 1, junction breakdown occurs in the MOS transistors QT1 and QT2, the abnormal voltage is discharged, and the MOS transistor QT1 finally reaches the ground potential level (Vf level). Discharge until. When negative static electricity (abnormal voltage) is applied, the substrate regions of MOS transistors QT1 and QT2 are connected to the ground voltage level, so that the PN junction conducts and current flows from substrate region to signal wiring 11. As a result, a current flows to the potential of the substrate region of MOS transistor QT2, that is, a current flows to the base of the parasitic bipolar transistor, the parasitic bipolar transistor is turned on, and a negative abnormal voltage is rapidly reduced to the ground voltage level (-Vf level). Discharge (charge).
It should be noted that P-type impurity ions are implanted into the channel regions of MOS transistors QT1 and QT2 shown in FIG. 26, the threshold voltage thereof is increased, and the leakage current during normal operation is suppressed. .

[Application Example 4] FIG. 27 shows a structure of a fourth application example of the protection element according to the present invention. This figure 2
7 is provided for an external terminal (data output terminal) 402 that receives an output signal from the output circuit 401 via an output signal wiring 404. This output circuit 40
1 includes n-channel MOS transistors OQ2 and OQ3 connected in series between a power supply node and a ground node. Signals from inside (signals corresponding to internal read data) are applied to the gates of MOS transistors OQ2 and OQ3, respectively.

The protection circuit includes an NPN lateral transistor QT provided between output signal line 404 and a power supply node.
3 and an NPN lateral transistor QT4 provided between the output signal wiring 404 and the ground node. NPN lateral transistor QT3 has an emitter region connected to the power supply node and a collector region connected to output signal line 4.
04. The base region corresponds to the substrate region 400a. On the other hand, the NPN lateral transistor QT4
Has its collector region connected to output signal wiring 404 and its emitter region connected to a ground node. The base region corresponds to the substrate region 400b.

In the structure shown in FIG. 27, during normal operation, the potential amplitude of output signal line 404 is V
cc (ground voltage Vss is 0 V). In this state, NPN lateral transistors QT3 and QT3
At T4, the off state is maintained because no junction breakdown occurs. Therefore, a signal appearing on output signal wiring 404 is transmitted to external terminal (data output terminal) 402.

When positive static electricity (abnormal voltage) is applied to external terminal 402, NPN lateral transistor QT
Junction breakdown occurs in the collector region of QT3 and QT4, and this positive abnormal voltage (static electricity) is discharged. Finally, the positive static electricity is discharged to the ground voltage Vss level (more precisely, Vss + Vf level) according to the NPN lateral transistor QT4.

On the other hand, when negative static electricity (abnormal voltage) is applied to external terminal 402, substrate regions 400a and 400n of NPN lateral transistors QT3 and QT4
From 00b, a current flows to the collector region. At this time,
The potentials of substrate regions 400a and 400b are reduced by this current, the collector acts as an emitter and is forward biased, and lateral transistors QT3 and QT4 are turned on. Therefore, in this state, the PN junction between the substrate region and the collector region is biased in the forward direction to absorb negative static electricity (abnormal voltage) and to be charged by lateral transistors QT3 and QT4.

[Application Example 5] FIG. 28 is a diagram showing a fifth application example of the protection element of the present invention. In the configuration shown in FIG. 28, PN diode DP3 according to the present invention is connected between output signal wiring 404 and the power supply node, and PN diode DP3 according to the present invention is connected between output signal wiring 404 and the ground node.
The diode DP4 is connected. PN diode DP3
Has a cathode connected to the power supply node Vcc and an anode connected to the output signal wiring 404. Diode DP4 has its cathode connected to output signal line 404 and its anode connected to the ground node. In the cathode regions of these diodes DP3 and DP4,
According to the present invention, a P-type impurity is ion-implanted in the same manufacturing process as that for adjusting the threshold of the memory cell transistor.

When a positive static electricity is applied, the diode DP3 conducts and discharges the positive static electricity to the power supply node. At the same time, the junction breakdown of the diode DP4 causes a large current to cause the positive static electricity (abnormal). Voltage)
To the ground node. Finally, the external terminal 402
The positive static electricity (abnormal voltage) given to the diode D
P3 discharges the voltage to the voltage level of Vf + Vcc (Vf is the forward voltage drop of the PN junction of the diode DP3). On the other hand, when a negative surge voltage is applied, diode DP4 conducts and supplies current to the output signal line 404 from the ground node, and the external terminal 402 is connected due to the junction breakdown between the cathode and anode of diode DP3. A current is supplied from the power supply node Vcc to the negative static electricity (abnormal voltage) generated in the above, and the negative static electricity (abnormal voltage) is absorbed. This negative static electricity (abnormal voltage)
Is discharged to the -Vf level by the diode DP4.

In normal operation, output signal wiring 40
4 is at the level of the power supply potential Vcc, and both diodes DP3 and DP4 maintain the off state (no junction breakdown of diode DP4 occurs).

[Application Example 6] FIG. 29 is a diagram showing a configuration of a protection element according to a sixth application example of the present invention. In the configuration shown in FIG. 29, as a transistor at the output stage of output circuit 401, MOS transistor OQT1 according to the present invention is provided.
And OQT2. MOS transistor OQ
T1 is connected between the power supply node and the output signal wiring 404, and the MOS transistor OQT2 is connected to the output signal wiring 40.
4 and the ground node. Signals from inside (signals corresponding to internal read data) are applied to the gates of MOS transistors OQT1 and OQT2, respectively. In these MOS transistors OQT1 and OQT2, ions are implanted only in the source and drain regions, but not in the channel region. Therefore, MOS transistors OQT1 and OQT2 have the same threshold voltage as other MOS transistors in the peripheral circuit. Therefore, these MOS transistors OQT1 and OQT1
Even when QT2 is used in the output stage of the output circuit 401, it operates at high speed because of its low threshold voltage. On the other hand, in the MOS transistors OQT1 and OQT2, P-type ions are implanted into the source / drain regions, and the junction breakdown voltage between these source / drain regions and the substrate region is relatively small. Therefore, when static electricity is applied to external terminal 402, the parasitic bipolar transistors of MOS transistors OQT1 and OQT2 conduct, and discharge this static electricity to the power supply node or the ground node. In this case, the MOS transistor OQT
1 and the substrate region of OQT2 are connected to the ground voltage level. Regardless of whether positive or negative static electricity (abnormal voltage) is applied to the external terminal 402, the MOS transistor OQ
The parasitic bipolar transistors of T1 and OQT2 conduct, and the static electricity is absorbed.

[Application Example 7] FIG. 30 shows a structure of a protection element according to a seventh application example of the present invention. In the configuration shown in FIG. 30, electric wire 41 transmitting power supply voltage Vcc is provided.
1 and the ground line 412 transmitting the ground voltage Vss.
An N lateral transistor QT5 is provided. The transistor QT5 has a collector region connected to the power supply line 411 and an emitter region connected to the ground line 412. The base region is formed by the substrate region 400. This figure 3
In the configuration shown in FIG. 0, when positive static electricity (abnormal voltage) is applied to power supply line 411, junction breakdown occurs in the collector region of NPN lateral transistor QT5, transistor QT5 conducts, and power supply line 4
11 is discharged to the ground line 412 at a high speed. Positive static electricity on the ground line 412 and the power line 411
The upper negative static electricity is absorbed by the substrate region 400.

[Application Example 8] FIG. 31 shows a structure of an eighth application example of the protection element according to the present invention. In the configuration shown in FIG. 31, a PN diode D according to the present invention is provided.
P5 is connected between power supply line 411 and ground line 412.
Diode DP5 has a cathode connected to power supply line 411 and an anode connected to ground line 412. P-type impurity ions for lowering the junction breakdown voltage are implanted into the cathode region. In the configuration shown in FIG. 31 as well, when positive static electricity (abnormal voltage) is applied to power supply line 411, breakdown occurs at the PN junction between the cathode and anode of diode DP5, and power supply line 41
1 is discharged to the ground line 412.

By providing a protective element for power supply line 411 as shown in FIG. 31, positive static electricity generated on power supply line 411 can be absorbed at high speed, and the internal circuit Can be prevented from being destroyed by static electricity (abnormal voltage) generated in the device.

Even when negative static electricity (abnormal voltage) is applied to the ground line 412, it is absorbed in the substrate region, but the reverse bias voltage between the cathode and anode of the diode DP5 reduces the junction breakdown voltage. If exceeded,
Junction breakdown occurs in the diode DP5, a current flows from the power supply line 411 to the ground line 412, and this negative static electricity (abnormal voltage) is absorbed.

[Application Example 9] FIG. 32 shows a structure of a ninth application example of the protection element according to the present invention. Referring to FIG. 32, a MOS transistor QT6 formed according to the present invention is coupled between power supply line 411 and ground line 412. MOS transistor QT6 has one conduction node connected to power supply line 411 and the other conduction node connected to ground line 412. The gate is connected to the ground line 412 via the resistance element RT. The resistance element RT delays application of a high electric field to the gate electrode layer even when a large surge voltage is applied to the power supply line 411 and the ground line 412, and prevents the gate insulating film from being broken.

In the structure shown in FIG. 32, power supply line 4
When positive static electricity is applied to the MOS transistor 11, a junction breakdown occurs at the drain (one conduction node) of the MOS transistor QT6, the parasitic NPN lateral transistor conducts, current flows from the power supply line 411 to the ground line 412, Then, the static electricity is absorbed (at this time, current also flows to the substrate region). On the other hand, the ground line 412
When negative static electricity (abnormal voltage) is applied to the MOS transistor QT6, even if the potential of the source region (one conduction node) of the MOS transistor QT6 decreases, the potential of the substrate region also decreases.
No junction breakdown occurs at this point. However, when the potential of the substrate region decreases, the power supply voltage Vc
c, a junction breakdown occurs between the other conduction node (drain electrode node) and the substrate region.
A current flows from the substrate region 11 to the substrate region, and a current flows from the substrate region to one conduction node, so that the negative static electricity of the ground line 412 is absorbed (here, the MOS transistor Q
The substrate area of T6 is connected to the ground line 412).

At this time, the resistance M
If the decrease in the gate potential of OS transistor QT6 is delayed, the gate-source of MOS transistor QT6 is biased in the forward direction, turning on MOS transistor QT6, and current is supplied from power supply line 411 to ground line 412. Thereby, negative static electricity can be absorbed at high speed.

In the above embodiment, in an NPN lateral transistor in which the emitter region and the collector region are separated by a field oxide film (field insulating film), a gate electrode layer is formed on the field insulating film. Although not provided, a similar effect can be obtained even if a gate electrode layer is provided on this field insulating film and the NPN lateral transistor is used as a so-called "field transistor".

In the above embodiment, the aluminum wiring is directly connected to the impurity region. However, in order to eliminate the problem due to aluminum alloy spikes during the manufacturing process, titanium nitride titanium nitride or titanium tungsten TiW is used. A similar effect can be obtained even in a wiring structure in which a barrier metal such as TiN / Ti and TiW / Ti is provided on the impurity region of the contact hole.

[0150]

According to the first aspect of the present invention, a protection device for protecting an internal circuit from an abnormal voltage applied to an external terminal is provided by a first conductive type semiconductor substrate region and a first external terminal. A first impurity region of the second conductivity type, which is electrically connected to the first impurity region; and a first impurity region formed between the first impurity region and the semiconductor substrate region so as to surround the first impurity region. And a second impurity region of a first conductivity type having a high impurity concentration, and formed on the surface of the semiconductor substrate region apart from the first and second impurity regions and electrically connected to a second external terminal. Since the structure includes the third impurity region, the breakdown voltage of the PN junction formed between the first impurity region and the semiconductor substrate region can be reduced, and the amount of heat generated by the junction breakdown voltage is reduced. It is possible, A highly reliable protection device that can suppress the growth of alloy spikes due to the diffusion of aluminum into the impurity region of the aluminum wiring, and can suppress junction breakdown, junction leakage, and generation of silicon nodules in the semiconductor region. Can be realized.

According to the invention of claim 2, since the fourth impurity region having an impurity concentration lower than the impurity concentration of the first impurity region is formed between the first and second impurity regions, The electric field applied to the depletion layer between the first impurity region and the second impurity region can be reduced, and the breakdown of the PN junction can be prevented while reducing the junction breakdown voltage.

According to the third aspect of the present invention, the third impurity region is constituted by an impurity region of the second conductivity type.
Since the fourth impurity region having an impurity concentration higher than that of the substrate region is further formed to surround the impurity region, the protection device has a configuration including a lateral transistor or a parasitic bipolar transistor, and these devices are turned on when an abnormal voltage is generated. With a large current amplification factor,
This abnormal voltage can be absorbed at high speed.

According to the fourth aspect of the present invention, a fifth impurity region of the second conductivity type having a lower impurity concentration than the third impurity region is provided between the third and fourth impurity regions. Therefore, also in the third impurity region, the electric field applied to the depletion layer can be reduced, and junction breakdown at the time of applying an abnormal voltage to the third impurity region can be prevented.

According to the fifth aspect of the present invention, the third impurity region is formed of the first conductivity type impurity region having an impurity concentration higher than that of the semiconductor substrate region.
A protection device including a PN junction diode can be realized, and similarly, a protection device having a low junction breakdown voltage can be realized.

According to the invention of claim 6, since a thick insulating film is formed on the surface of the semiconductor substrate region between the first and third impurity regions, each of the first and third impurity regions is formed. A lateral bipolar transistor as a collector / emitter can be formed, and an abnormal voltage can be absorbed at a high speed due to a large current amplification factor of the lateral bipolar transistor.

According to the seventh aspect of the present invention, since the gate electrode layer is formed on the surface of the semiconductor substrate region between the first and third impurity regions via the insulating film, the parasitic bipolar transistor of the MOS transistor is formed. A protection device using a transistor can be realized.

According to the invention of claim 8, one of the first and second external terminals receives one of a power supply voltage and a ground voltage, and the other receives one of an input signal and an output signal. An abnormal voltage (static electricity) externally applied to the other of the first and second external terminals can be reliably absorbed by one of the external terminals.

According to the ninth aspect of the present invention, one and the other of the first and second external terminals receive the power supply voltage and the ground voltage, and are reliably generated on the power supply voltage supply line and the ground voltage supply line. Abnormal voltage can be absorbed, and destruction of the internal circuit due to abnormal voltage on the electric wire or the ground line can be prevented.

According to the tenth aspect, the gate electrode layer of the MOS transistor receives a signal from the internal circuit, one of the first and second external terminals receives one of the power supply voltage and the ground voltage, and The other is connected to an external terminal for outputting a signal, so that the output stage of the output circuit and the protection device can be shared, and the area occupied by the device can be reduced.

According to the eleventh aspect of the present invention, the surface impurity concentration of the channel region of the MOS transistor included in the memory cell and the impurity concentration of the second impurity region are the same, and these are formed in the same manufacturing process. Therefore, a protection device having a reduced junction breakdown voltage can be easily realized without increasing the number of manufacturing steps.

According to the twelfth aspect of the present invention, the same impurity ion is implanted into at least one junction region of the protection element in the same step as the impurity ion implantation for adjusting the threshold voltage of the MOS transistor. Therefore, the breakdown voltage at the junction of the protection element can be adjusted without increasing the number of manufacturing steps. At this time, if the threshold voltage adjustment is performed to increase the threshold voltage of the MOS transistor of the memory cell, this junction region becomes a high-concentration PN junction, which may lower the junction breakdown voltage. it can.

According to the thirteenth aspect, the protection element includes the first and second impurity regions of the second conductivity type formed between the semiconductor substrate regions. Since the ion implantation is performed only on the first and second impurity regions, ions are not implanted into the channel region of the protection element. It can be the same as the MOS transistor of the peripheral circuit, and this protection element can be used also as a peripheral circuit, and the circuit occupation area can be reduced.

According to the fourteenth aspect of the present invention, the impurity ion implantation is also performed on the surface of the substrate region between the first and second impurity regions, which may cause a malfunction during normal operation. Thus, it is possible to reliably realize the protection element in which the junction breakdown voltage is reduced.

According to a fifteenth aspect of the present invention, a protection element includes a first conductivity type impurity region and a second conductivity type impurity region, and the impurity ions are implanted to have the same conductivity type as the substrate. This is performed only for the impurity region which has the PN junction diode. Even when the PN junction diode is used as a protection element, the junction breakdown voltage can be reliably reduced by the high concentration PN junction.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an overall configuration of a semiconductor device according to the present invention.

FIG. 2 is a diagram specifically showing a configuration of a memory cell array section of the semiconductor device shown in FIG.

FIG. 3 is a diagram more specifically showing a configuration of a memory cell array unit shown in FIG. 2;

FIG. 4 is a diagram showing tail current characteristics of a MOS transistor.

FIG. 5 is a diagram for describing a problem in a case where a memory cell transistor is formed of a low threshold voltage memory cell transistor.

FIG. 6 shows a step of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a view illustrating a second manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a view illustrating a third manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 shows a fourth manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 shows a fifth manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a view illustrating a sixth manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a diagram showing distribution of impurity ions on a substrate surface during impurity ion implantation in a semiconductor device according to the present invention.

FIG. 13 is a view illustrating a seventh manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 14 shows an eighth manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 15A shows a configuration of a memory cell array portion in a ninth manufacturing step of the semiconductor device according to the first embodiment of the present invention, and FIG. 15B shows a configuration of a protection circuit region in the ninth manufacturing step; It is a figure which shows schematically.

FIG. 16 shows a tenth manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 17A is a diagram showing a configuration of a memory cell of a semiconductor device according to a second embodiment of the present invention, and FIG.
Is a diagram showing a modification example thereof.

FIG. 18 shows a structure of a memory cell of a semiconductor device according to a third embodiment of the present invention.

FIG. 19 is a diagram showing operation characteristics of the memory cell of FIG. 18;

20 is a diagram for describing a problem when the memory cell of FIG. 18 has a low threshold voltage.

FIG. 21A shows a sectional structure of a protection element of a semiconductor device according to a fourth embodiment of the present invention, and FIG. 21B shows an electrical equivalent circuit thereof.

FIG. 22A shows a sectional structure of a protection element of a semiconductor device according to a fifth embodiment of the present invention, and FIG. 22B shows an electrical equivalent circuit thereof.

FIG. 23 is a diagram showing an impurity ion implanted region according to a fifth embodiment of the present invention.

FIG. 24 is a diagram showing a first application example of the semiconductor protection device according to the present invention.

FIG. 25 is a diagram showing a second application example of the semiconductor protection device according to the present invention.

FIG. 26 is a diagram showing a third application example of the semiconductor protection device according to the present invention.

FIG. 27 is a diagram showing a fourth application example of the semiconductor protection device according to the present invention.

FIG. 28 is a diagram showing a fifth application example of the semiconductor protection device according to the present invention.

FIG. 29 is a diagram showing a sixth application example of the semiconductor protection device according to the present invention.

FIG. 30 is a diagram showing a seventh application example of the semiconductor protection device according to the present invention.

FIG. 31 is a diagram showing an eighth application example of the semiconductor protection device according to the present invention.

FIG. 32 is a diagram showing a ninth application example of the semiconductor protection device according to the present invention.

FIG. 33 is a diagram schematically showing a configuration of a conventional input protection circuit and a structure of a protection element.

[Explanation of symbols]

APC address protection circuit, OPC output protection circuit, I
PC input protection circuit, AB address buffer, CG
Control signal generation system, OB output buffer, MA memory cell array, MC memory cell, MT memory cell transistor, 200 semiconductor substrate, 210, 210a to 210h
Field insulating film (thermal oxide film), 220a, 220b
220 d P well, 218 gate electrode layer, 220
a low concentration impurity region, 222b low concentration impurity region, 2
24a, 224b High concentration impurity region, 300 memory cell formation region, 306 protection circuit formation region, Q1, Q2
SRAM memory cell transistor, 250 semiconductor substrate, 252a, 252b high concentration impurity region, 254
Floating gate, 256 control gate,
M1, M2 Flash memory cell (EEPROM cell), 300 semiconductor substrate, 310 low concentration well, 32
0 relatively high concentration impurity region, 322 low concentration impurity region, 324 high concentration impurity region, 330 high concentration impurity region, 316, 317 field insulating film, 1 external terminal, 350 semiconductor substrate, 352 well, 354
a, 354b relatively high concentration impurity regions, 356a,
356b Impurity region of relatively low concentration, 358a, 35
8b High concentration impurity region, 360 gate electrode layer, 36
5 MOS transistor, 359 channel region, QT
NPN lateral transistor, DP1, DP2, DP
3, DP4, DP5 PN junction diode, QT1, QT
2 MOS transistor (parasitic bipolar transistor), QT3, QT4 NPN lateral transistor,
400, 400a, 400b Substrate area, 402 external terminal, 401 output circuit, OQT1, OQT2 Low threshold voltage MOS transistor (parasitic bipolar transistor), QT6 MOS transistor.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication location H01L 21/8242

Claims (15)

[Claims] A semiconductor protection device for protecting an internal circuit from an abnormal voltage applied to an external terminal, wherein the semiconductor protection device is electrically connected to a semiconductor substrate region of a first conductivity type and a first external terminal. A first impurity region of a second conductivity type, a higher impurity concentration than the semiconductor substrate region, formed between the first impurity region and the semiconductor substrate region so as to surround the first impurity region. A second impurity region of a first conductivity type having a first conductivity type and a second impurity region formed on the surface of the semiconductor substrate region apart from the first and second impurity regions;
A semiconductor protection device including a third impurity region electrically connected to a second external terminal. 2. The semiconductor device according to claim 1, wherein said first impurity region is formed between said first and second impurity regions so as to surround said first impurity region and to be surrounded by said second impurity region. The semiconductor protection device according to claim 1, further comprising a fourth impurity region having an impurity concentration lower than the impurity concentration. 3. The semiconductor device according to claim 2, wherein the third impurity region is an impurity region of the second conductivity type, and is formed on the surface of the semiconductor substrate region so as to surround the third impurity region. The semiconductor protection device according to claim 1, further comprising a fourth impurity region of a first conductivity type having a concentration. 4. The semiconductor device further comprises a fifth impurity region of a second conductivity type, which is formed between the third and fourth impurity regions and has a lower impurity concentration than the third impurity region.
The semiconductor protection device according to claim 3. 5. The semiconductor protection device according to claim 1, wherein said third impurity region is a first conductivity type impurity region having an impurity concentration higher than an impurity concentration of said semiconductor substrate region. 6. The semiconductor protection device according to claim 1, further comprising a thick insulating film formed on a surface of said semiconductor substrate region between said first and third impurity regions. 7. The semiconductor device according to claim 1, further comprising a gate electrode layer formed on said semiconductor substrate region surface between said first and third impurity regions via a thin insulating film. Semiconductor protection equipment. 8. The device according to claim 1, wherein one of said first and second external terminals receives one of a power supply voltage and a ground voltage, and the other receives one of an input signal and an output signal. A semiconductor protection device according to claim 1. 9. One of the first and second external terminals receives one of an operating power supply voltage and a ground voltage, and the other external terminal receives the other of the operating power supply voltage and the ground voltage. 8. The semiconductor protection device according to any one of 7. 10. The gate electrode layer receives a signal from an internal circuit, one of the first and second external terminals receives one of an operating power supply voltage and a ground voltage, and the other functions as a signal output terminal. The semiconductor protection device according to claim 3, wherein 11. The protection device is used in a semiconductor memory device including a memory cell having at least one insulated gate field effect transistor for storing information, the protection device comprising a channel region of the insulated gate field effect transistor. 11. The semiconductor protection device according to claim 1, wherein a surface impurity concentration is substantially equal to an impurity concentration of said second impurity region. 12. A plurality of memory cells arranged in a matrix, each having at least one insulated gate field effect transistor, an internal circuit for accessing the plurality of memory cells, and the internal circuit. A protection element having a junction formed between at least one impurity region of the opposite conductivity type for protecting from an external abnormal voltage, comprising: an insulated gate electric field of the memory cell; The impurity ions are also implanted into the at least one junction forming region of the protection element in the same step as the impurity ions are implanted into the channel region for adjusting the threshold voltage of the effect transistor. To manufacture a semiconductor device. 13. The insulated gate field effect transistor of the memory cell is formed in a semiconductor substrate region of a first conductivity type, the impurity ions are impurity ions of a first conductivity type, and the protection element is a memory device. A second semiconductor substrate region of the first conductivity type provided separately from the cell formation region, and first and second semiconductor substrates of the second conductivity type formed on the surface of the second semiconductor substrate region with a space therebetween. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the impurity ion implantation is performed on the first and second impurity region forming regions. 14. The method of manufacturing a semiconductor device according to claim 13, wherein said impurity ion implantation is also performed on a surface of said second semiconductor substrate region between said first and second impurity regions. 15. The insulated gate field effect transistor of the memory cell is formed in a semiconductor substrate region of a first conductivity type, and the protection element is provided in a first conductivity type provided in a region different from the memory cell formation region. A first semiconductor region of the second conductivity type and a second impurity region of the first conductivity type, which are formed on the surface of the second semiconductor substrate region at a distance from each other. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the first conductivity type impurity ions are applied to a channel region of the insulated gate field effect transistor of the memory cell and the first impurity region formation region.