JPH1083679A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degradation of a retention characteristic of a semiconductor memory device caused by a phenomenon called as imprint in which a hysteresis characteristic of a ferroelectric is deviated. SOLUTION: This device is a semiconductor memory device using a ferroelectric substance capacitor which can store data even in a state in which a power source is not supplied due to residual polarization, a comparing circuit 30 is connected to bit lines 7, 8 and data lines 9, 10, data stored in ferroelectric capacitors 1, 2 is compared with data newly written in the ferroelectric capacitors 1, 2 based on a signal from the comparing circuit 30, when both data are different, an applying time of writing voltage of data, that is, a writing voltage applying time to a word line 5 and a cell plate 6 is made long by a writing operation control circuit 31. This writing voltage is given to the word line 5 and the cell plate 6 by drivers 14, 15 based on a control signal from the writing operation control circuit 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device mainly using a ferroelectric capacitor.

[0002]

2. Description of the Related Art Currently, a typical semiconductor memory device is a dynamic random access memory (DRAM), but recently, a ferroelectric memory device using a ferroelectric material as an insulating film of a charge storage capacitor of the DRAM. Has been developed. This memory device can be used as a non-volatile memory due to a characteristic of a ferroelectric material in which a DRAM remains volatile even when an external electric field is removed, while a DRAM is a volatile memory. Also, existing rewritable nonvolatile memory devices have excellent characteristics such as low power consumption and high rewrite speed. For this reason, interest is increasing as a next-generation main memory device.

FIG. 8 is a circuit diagram showing an example of a conventional 2Tr-2C (2Transistor-2Capacitance) type semiconductor memory device using a ferroelectric capacitor. In FIG. 8, 1 and 2 are ferroelectric capacitors. Access transistors 3 and 4 are NMOS transistors in the example shown. 5 is a word line, 6 is a cell plate, 7
And 8 are bit lines, and 9 and 10 are data lines. Reference numeral 11 denotes a differential amplifier for amplifying the potential difference between the bit lines 7 and 8, and in the example shown in the figure, is constituted by two clocked CMOS inverters whose activation and inactivation can be controlled by a control signal φs. Reference numeral 12 denotes a bit line 7 and a data line 9, and a bit line 8 and a data line 1.
The electrical connection / disconnection can be controlled by the control signal φt at the transfer gate connecting 0. Reference numeral 13 denotes a circuit for latching input data and output data. In the example shown in the figure, the circuit 13 includes two CMOS inverters. Reference numeral 14 denotes a word line driver, and 15 denotes a cell plate driver, which changes the potentials of the word line 5 and the cell plate 6 based on control signals φw and φc, respectively. A precharge circuit 16 sets the bit lines 7 and 8 to the ground potential based on the control signal / φp. The data lines 9 and 10 are connected to an input circuit and an output circuit.

FIG. 9 is a read operation timing chart showing a data read operation timing in the semiconductor memory device of FIG. WL, CP, BL, / BL, DL, / D
L is the potential of the word line 5, the cell plate 6, the bit line 7, the bit line 8, the data line 9, and the data line 10, and φs, φt, / φp are the differential amplifier 11, the transfer gate 12, the precharge, respectively. This is the level of the control signal of the circuit 16. A data reading operation in this device will be described with reference to FIGS.

It is assumed that all the nodes in FIG. 8 are at the ground potential as an initial state. First, the potential of the word line 5 is raised to turn on the NMOS transistors 3 and 4, and the potential of the cell plate 6 is raised. Then, the ferroelectric capacitor 1
Different potentials appear on the bit lines 7 and 8 depending on whether the directions of the spontaneous polarizations of and 2 are reversed. Next, the control signal φs
To activate the differential amplifier 11 to amplify the potential difference between the bit lines 7 and 8. After the amplification is completed, the control signal φt is enabled to enable the transfer gate 12
Is turned on, the potentials of the bit lines 7 and 8 are sent to the latch circuit 13, and the output circuit outputs data to the outside. FIG.
When the read data and the data of the latch circuit are different, the differential amplifier 11 inverts the potential of the latch circuit 13.

On the other hand, since the data in the memory cell has been destroyed by reading, the operation of rewriting starts. First, the potential of the cell plate 6 is lowered while the differential amplifier 11 is activated. After writing is performed in the memory cell by the potential held on the bit line 7 or 8, the potential of the word line 5 is lowered to
And 4 off. Next, the control signals φt and φs are disabled, the transfer gate 12 is turned off, and the differential amplifier 11 is deactivated. Finally, the control signal /
The read operation is completed by setting φp to a high level and precharging the bit lines 7 and 8 to the ground potential.

In the case of a write operation, the data for rewriting described above may be input from outside. That is, a potential is output from the input circuit to the data lines 9 and 10, data is read from the memory cell, amplified by the differential amplifier 11, and then the transfer gate 12 is turned on. 8, the desired data is written to the memory cell. FIG. 10 shows a timing chart of the write operation (the meaning of each signal name is shown in FIG. 9).
The description is omitted here. FIG.
When the data stored in the memory cell is different from the input data, such as 0, the data latched by the differential amplifier 11 is inverted by the input circuit.

[0008]

In the conventional device, the voltage-charge amount curve of the ferroelectric capacitor is deviated (imprint phenomenon), so that the data retention ability (retention characteristic) without power supply is reduced. There was a problem of deterioration. FIG. 11 shows the voltage-charge amount curve and the state of the deviation. The horizontal axis represents the voltage applied to both ends of the capacitor, and the vertical axis represents the charge amount appearing on the electrode of the capacitor. As shown in FIG. 11, in a ferroelectric capacitor, a residual charge Pr appears on an electrode even when an external voltage is 0 (V).

Now, it is assumed that the ferroelectric capacitor is in a state shown by a solid line 20. In the case of 2Tr-2C type,
The two ferroelectric capacitors holding data are in the states of points 21 and 22 on the solid line 20, respectively, and hold the data even without power supply due to the difference 2Pr between the residual charges. If left in this state, a change in characteristics occurs in the ferroelectric film due to the internal electric field due to the residual polarization. Therefore, the voltage-charge amount curve is shown by a dotted line 23 for the ferroelectric capacitor in the state of the point 21 and a dashed line 24 for the ferroelectric capacitor in the state of the point 22.
It changes like Thereafter, when the reverse data is written, the two ferroelectric capacitors are point 25 and point 2 respectively.
The state becomes 6. Therefore, the difference between the residual charges is
From the difference 2Pr between the points 25 and 26, the difference 2Pri between the points 25 and 26
, The retention characteristics deteriorate.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of preventing deterioration of retention characteristics due to a decrease in residual charges.

[0011]

In order to solve this problem, a semiconductor memory device according to the present invention comprises a comparing circuit for determining whether input data and data stored in a memory cell are equal or different. When the data input based on the output of the comparison circuit and the data stored in the memory cell are different, a desired voltage to be applied to the ferroelectric substance of the memory cell is set in a desired manner, for example, a writing voltage application time. To increase the write voltage, increase the write voltage, and repeat the inversion of the voltage applied to the ferroelectric of the memory cell before starting the write operation by applying the write voltage to perform the polarization inversion of the ferroelectric of the memory cell. And a control circuit for performing a so-called refresh operation.

According to the structure of the present invention, when the input data and the data stored in the memory cell are different, the voltage applied to the ferroelectric capacitor of the memory cell is different from the case where both data are the same. By making them different
It is possible to cancel the change in characteristics caused by the internal electric field due to the residual polarization, recover the bias of the voltage-charge amount curve, and prevent the deterioration of the retention characteristics due to the decrease in the residual charges. Also, when the input data and the data stored in the memory cell are different, a refresh operation for canceling the characteristic change is performed, and when the two data are the same, the refresh operation is not performed. In addition, it is possible to reduce an increase in power consumption for canceling the characteristic change and to reduce the fatigue of the ferroelectric film.

[0013]

A semiconductor memory device according to a first aspect of the present invention includes a memory cell using a dielectric capacitor, a bit line, a data line, and storage data and a data line read from the memory cell to a bit line. A comparison circuit that compares the write data inputted to the memory cell, and a control circuit that extends the application time of the write voltage applied to the memory cell when the storage data and the write data are different based on a signal from the comparison circuit. I have.

According to this configuration, when the storage data and the write data are different, the application time of the write voltage to be applied to the memory cell is longer than when both the data are the same. As a result, the change in characteristics caused by the internal electric field due to the residual polarization is canceled, the bias of the voltage-charge amount curve is recovered, and the deterioration of the retention characteristics due to the decrease in the residual charges is prevented.

According to another aspect of the present invention, a memory cell using a dielectric capacitor, a bit line, a data line, and storage data read from the memory cell to a bit line and input to the data line. A comparison circuit is provided for comparing the write data and a control circuit for increasing the write voltage applied to the memory cell when the storage data and the write data are different based on a signal from the comparison circuit.

According to this configuration, when the storage data and the write data are different, the write voltage applied to the memory cell is higher than when both the data are the same. As a result, the change in characteristics caused by the internal electric field due to the residual polarization is canceled, the bias of the voltage-charge amount curve is recovered, and the deterioration of the retention characteristics due to the decrease in the residual charges is prevented. At this time, since the canceling is performed by increasing the voltage, the change in the characteristic is effectively canceled.

According to a third aspect of the present invention, a memory cell using a dielectric capacitor, a bit line, a data line, and storage data read from the memory cell to a bit line and input to the data line. A comparison circuit for comparing the write data with a write voltage, and applying a write voltage when the storage data and the write data are different based on a signal from the comparison circuit, and applying a write voltage to the ferroelectric material of the memory cell before starting the write operation. A control circuit for inverting the polarization of the ferroelectric of the memory cell by repeating the inversion.

According to this configuration, when the storage data and the write data are different, the inversion of the voltage applied to the ferroelectric of the memory cell is repeated before the start of the write operation, and the polarization inversion of the ferroelectric of the memory cell is repeated. Done. As a result, the change in characteristics caused by the internal electric field due to the residual polarization is canceled, the bias of the voltage-charge amount curve is recovered, and the deterioration of the retention characteristics due to the decrease in the residual charges is prevented. In addition, the polarization inversion of the ferroelectric of the memory cell is performed when the storage data and the write data are different, and is not performed when the two data are the same. Less is.

The above phenomenon of dielectric film fatigue means that the magnitude of spontaneous polarization (2Pr in FIG. 11) is reduced by repeating the polarization inversion of the ferroelectric. If the magnitude of spontaneous polarization cannot be maintained beyond a certain level due to dielectric film fatigue, a sufficient potential difference does not occur in the bit line when data is read, and the characteristics of the sense amplifier and the variation in the bit line capacitance are reduced. Being strongly affected, data cannot be output correctly.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention. Among the components, those having the same reference numerals as those in FIG. 8 are basically the same, and the description thereof is omitted.
In FIG. 1, reference numeral 30 denotes a comparison circuit for comparing and judging whether input data (data on data lines 9 and 10) and data stored in a memory cell (data on bit lines 7 and 8) are the same or different. In the example of FIG. 1, exclusive-OR (exclusive-
OR) circuit is used. Note that, in FIG.
And an exclusive OR circuit connected to the data line 9 and an exclusive OR circuit connected to the bit line 8 and the data line 10. However, there is no problem if only one of them is provided.

Reference numeral 31 denotes a write operation control circuit for controlling a write operation based on a signal from the comparison circuit 30 for comparing data, and corresponds to a control circuit in the claims. Its function is to receive the control signals φw and φc generated by the operation clock circuit of the semiconductor memory device, apply a delay according to the result of the comparison circuit 30, and apply the control signals θw and θc
As a write operation control circuit. here,
The signals sent to the peripheral circuits of the memory cells instead of the control signals φw and φc from the operation clock circuit are denoted by θw and θc. The control signals .theta.w and .theta.c are sent to the peripheral circuit of the memory cell and, at the same time, returned to the operation clock circuit to correct the subsequent operation clock signals for the delay caused in .theta.w and .theta.c.

The circuit configuration of the write operation control circuit 31 includes falling delay circuits 32 and 33, a signal delayed through the falling delay circuits 32 and 33, and a signal not passing through the falling delay circuits 32 and 33. It comprises a transfer gate group 34 for switching, a latch circuit 35 for latching the result from the comparison circuit 30, and a transfer gate 36 for limiting the timing of inputting the output of the comparison circuit 30 to the latch circuit 35. The transfer gate 36 is controlled by a control signal φh. There is no problem even if the latch circuit 13 is omitted as a circuit for further stabilizing the operation.

Hereinafter, a write operation of the semiconductor memory device will be described. From the time when data is read from the memory cell to the bit lines 7 and 8 and amplified, the data is input to the data lines 9 and 10 by the input circuit and the latch circuit 13
The operation until the data is held is the same as that of the conventional example. In the present invention, before the next transfer gate 12 is turned on, the data of the memory cells on the bit lines 7 and 8 and the input data on the data lines 9 and 10 are compared by the comparison circuit 30.

When the two data are the same, a high-level voltage is supplied to the write operation control circuit 31.
By turning on the transfer gate 36, this is taken into the latch circuit 35. As a result, the control signals φw and φc from the operation clock circuit are directly selected by the transfer gate group 34 as the control signals θw and θc to the memory cell peripheral circuit. Since no delay is applied to the signal, a normal write operation as described in the conventional example is performed. However, it is necessary to turn off the transfer gate 36 before turning on the transfer gate 12 so that the potential changes of the bit lines 7 and 8 and the data lines 9 and 10 do not affect the write operation control circuit 31. There is.

When the two data are different, a low level voltage is supplied to the write operation control circuit 31. In that case, the control signals φw and φc fall and the delay circuits 32,
The signals delayed at 33 fall are the control signals θw, θc
Is output as FIG. 2 shows the resulting change in operation timing. φh is a control signal for the transfer gate 36, and other signals are the same as those in FIG. As shown by arrows 40 and 41 in FIG. 2, the write voltage application time for applying the write voltage to the memory cell is longer than in the conventional operation. Also, CP
And the control signals φs, φt, / φp after the delay of WL are
Due to the feedback of θw and θc to the operation clock circuit, the timing is delayed by the delay of CP and WL.

FIGS. 3 (a) to 3 (d) are diagrams showing the rewriting process in this device in terms of the voltage between the polar plates of the ferroelectric capacitor of the memory cell and the direction of polarization. Sign 1
8 are the same as those in FIG. 8, and the description thereof is omitted. Also, the direction of the polarization is represented by an arrow in the dielectric capacitors 1 and 2 according to the direction of the electric field that causes the polarization, and the direction of the voltage between the plates of the dielectric capacitors 1 and 2 is represented by a white arrow, The potential BL of the bit lines 7, 8
BL, potential WL of word line 5 and potential C of cell plate 6
The level of P is indicated by "H" in parentheses below each symbol.
i "and" Low ".

In the state where the power supply voltage is not supplied, FIG.
As shown in (a), data is held by the residual polarization of the ferroelectric. When reading this data, refer to FIG.
As shown in (b), the potential CP of the cell plate 6 is set to the high level to invert the polarization of the ferroelectric capacitor 1, and the potential BL of the bit line 7 and the potential of the bit line 8 /
BL is set to a high level and a low level. At this time, a voltage V1 is applied to the ferroelectric capacitor 2.

Subsequently, in order to write reverse data, FIG.
The potential BL of the bit line 7 and the potential / BL of the bit line 8 are reversed as shown in FIG. At this time, the ferroelectric capacitor 1
Applied a voltage V1 and held data as shown in FIG.
Polarization is caused in the direction opposite to that in the case of (a). In the present invention, the time (write voltage application time) for maintaining the state of FIG. 3C is extended as shown by the arrow 40 in FIG. 2 only when the read data and the write data are different. As a result, it is possible to remove a change in the characteristics of the ferroelectric capacitor 1 caused by the remanent polarization shown in FIG.

Next, as shown in FIG. 3D, when the potential CP of the cell plate 6 is set to the low level, the voltage V2 is applied to the ferroelectric capacitor 2 and the data is held in FIG. Polarization occurs in the direction opposite to that in the case of a). In this case, as in the case of the ferroelectric capacitor 1, the time during which the voltage V2 is applied to the ferroelectric capacitor 2 is shown in FIG.
Of the ferroelectric capacitor 2
The change of the characteristic is removed. In this way, FIG.
The change in the characteristics of the ferroelectric capacitors 1 and 2 caused in the state described above is removed, and the deterioration of the retention characteristics is prevented.

As described above, according to this embodiment,
When the storage data and the write data are different, the application time of the write voltage applied to the memory cell is made longer than when the two data are the same, so that the change in characteristics caused by the internal electric field due to the remanent polarization is canceled out. −
It is possible to recover the bias of the charge amount curve, and as a result, it is possible to prevent the retention characteristic from deteriorating due to the decrease in the residual charge.

[Second Embodiment] FIG. 4 shows a second embodiment of the present invention.
1 is a circuit diagram of a semiconductor memory device according to an embodiment. FIG. Among the components, those having the same numbers as those in FIG. 1 are basically the same, and the description thereof is omitted. In FIG. 4, reference numeral 50 denotes a write operation control circuit that controls a write operation based on the result from the data comparison circuit 30, and corresponds to a control circuit in the claims. Its function is to receive control signals .phi.w, .phi.c, .phi.s, and .phi.t generated by the operation clock circuit of the semiconductor memory device, and to control the data on the bit lines 7 and 8 and the data lines 9 and 10 according to the result of the comparison circuit 30. When the data is different, the driving circuit is switched to a higher power supply voltage to drive the word line 5, the cell plate 6, and the bit lines 7, 8, so that the high voltage operation does not affect the data lines 9, 10. Then, the transfer gate 12 is turned off.

The circuit configuration is similar to that of the word line driver 51.
A cell plate driver 52, a latch circuit 53 for latching the result from the comparison circuit 30, a switching circuit 54 for selecting the differential amplifiers 11 and 56 for driving the bit lines 7 and 8 based on the data of the latch circuit 53, Latch circuit 5
A transfer gate control circuit 55 for turning off the transfer gate 12 by the data of No. 3 and other circuits. Reference numeral 56 denotes a differential amplifier for amplifying the potential difference between the bit lines 7 and 8. In the example of the figure, the differential amplifier 56 is composed of two clocked CMOS inverters whose activation and inactivation can be controlled by the control signal θs2. Although not shown, the power supply voltage is naturally supplied, and a power supply voltage higher than that of the CMOS inverter forming the differential amplifier 11 is applied.

The word line driver 51 and the cell plate driver 52 are supplied with a higher drive voltage than the word line driver 14 and the cell plate driver 15, respectively. The transfer gate group 34 includes the word line drivers 14 and 51 and the cell plate drivers 15 and 5
2 is switched by the data of the latch circuit 53. The latch circuit 53 is obtained by adding a precharge circuit (MOS transistor) for initializing latch data to the latch circuit 35 of FIG. 1, and initializes latch data by a control signal / φp. Note that the output node of the latch circuit 53 is 57 for description.

When the control signal φs is at a high level and the node 57 is at a low level, the switching circuit 54
Is activated, and when the control signal φs is at a high level, the node 57
Activates the differential amplifier 56 when is at the high level. However, when the control signal φs is at the high level and the node 57 changes from the low level to the high level, the control signal θs2
At the rising edge of the control signal θs
Is delayed for a certain time after falling. When the control signal φt goes high when the node 57 is low, the transfer gate control circuit 55 turns the transfer gate 12 on by setting the control signal θt to high level. When the node 57 changes from low level to high level, the control signal .theta.t changes to low level after the delay time in the delay circuit 59. Note that the delay circuit 5
In the example shown in the figure, 8 and 59 use an even number of inverter circuits, and their input and output do not invert the logic level.
Also, there is no problem in a circuit that delays only a rising signal in combination with an AND circuit or the like.

FIG. 5 is an operation timing chart showing the timing of the write operation of the circuit of FIG. θs is a control signal for activating the differential amplifier 11, and θs2 is
Is a control signal that activates the transfer gate 1
2 is a control signal for turning on / off the switch 2. Others are the same as those in FIG. 2 and the description is omitted. In this embodiment, the voltage applied to the capacitor is increased without changing the write voltage application time. Of course, it is possible to increase the voltage and extend the application time within the scope of the present invention.

The write operation of this device will be described with reference to FIGS. When the data stored in the memory cell and the write data are the same as in the first embodiment, the same operation as in the conventional example is performed. If not,
Until the data is read from the memory cell and the potential of the bit line is amplified to the high level and the low level by the differential amplifier 11, the same operation as that of the conventional example is performed, but the result of the comparison circuit 30 is sent to the latch circuit 53. When the output node 57 goes high, the word line driver 14 and the cell plate driver 15 are switched to the word line driver 51 and the cell plate 52 having higher power supply voltages, and the potentials of the word line 5 and the cell plate 6 are changed. Go up. Further, the control signal θs becomes low level, and the differential amplifier 11 becomes inactive. Next, after the transfer gate 12 is turned on and the potential of the bit line is inverted, the control signal θt falling and delayed by the delay circuit 59 becomes low level, and the transfer gate 12 is turned off.

Here, the reason why the control signal θt is delayed will be described. That is, at the time of writing, the time required for inverting the potentials of the bit lines BL and / BL according to the potentials of the data lines DL and / DL is secured. In the conventional example, the transfer gate 12 is kept turned on until the end of the cycle, but in this embodiment,
It is necessary to activate the differential amplifier 56 to turn off the transfer gate 12 before raising the bit line voltage (if the transfer gate 12 is connected to a non-high voltage data line,
Since the voltage of the bit line cannot be increased),
Is a signal whose fall is delayed based on the output of the latch circuit 53.

Next, when the control signal θs2, which has been raised and delayed by the delay circuit 58, goes high, the differential amplifier 56 is activated, and the potential on the high level side of the bit line rises. In this state, the ferroelectric capacitor 1
, A voltage is applied in the direction shown in FIG. As in the case of the first embodiment, the change in the characteristics of the ferroelectric capacitor 1 is removed during this period. However, since a higher voltage is applied between the plates of the capacitor than in the conventional example, the change is removed. The effect is great. Further, by writing at a high voltage, the decrease in the residual charge as shown in FIG. 11 can be compensated.

Subsequently, when the potential of the cell plate 6 is set to a low level, a voltage is applied to the ferroelectric capacitor 2 in the direction shown in FIG. 3D and polarization occurs, and the same effect as that of the ferroelectric capacitor 1 is obtained. Is obtained. Then, word line 5
To a low level, deactivate the differential amplifier 56, and precharge the bit lines 7, 8 and the output node 57 of the latch circuit 53 to a low level, thereby completing the write operation.

In this example, the switching of the driving voltage of the word line driver, the cell plate driver and the differential amplifier is performed by preparing separate circuits having different power supply voltages, respectively. There is no problem even if you switch. As described above, according to this embodiment, when the storage data and the write data are different, the write voltage applied to the memory cell is higher than when the two data are the same. The bias in the voltage-charge amount curve can be recovered by canceling the change in the generated characteristics, and as a result, the deterioration of the retention characteristics due to the decrease in the residual charges can be prevented. At this time, since the cancellation is performed by increasing the voltage, it is possible to effectively cancel the change in the characteristic.

[Third Embodiment] FIG. 6 shows a third embodiment of the present invention.
1 is a circuit diagram of a semiconductor memory device according to an embodiment. FIG. Among the components, those having the same numbers as those in FIG. 1 are basically the same, and the description thereof is omitted. In FIG. 6, reference numeral 60 denotes a write operation control circuit that controls a write operation based on the result from the data comparison circuit 30, and corresponds to a control circuit in the claims. Its function is to receive a control signal φc generated by an operation clock circuit of the semiconductor memory device and a pulse signal π from inside or outside of the semiconductor memory device, and perform a write operation before starting a write operation according to the result of the comparison circuit 30. To
This refreshes the ferroelectric capacitors 1 and 2 of the memory cell.

The circuit configuration comprises a latch circuit 61 and a frequency divider / counter 62. The latch circuit 61 is basically the same as the latch circuit 35 of FIG. 1, except that a precharge circuit (comprising a MOS transistor) for initializing latch data by a signal from the frequency divider / counter 62 is added. . The output signal θb and the pulse signal π of the latch circuit 61 are input to the frequency divider / counter 62,
When .theta.b is at a low level, the output is in a preset state, and its outputs Q1 to Q4 are all at a high level. When .theta.b is at a high level, counting of the pulse signal .pi. is started. In the example of FIG. 6, a lip carry type hexadecimal down counter using four D-type flip-flops is used, but any circuit having a frequency divider and a counter function may be used. There is no problem with using it. Examples of the circuit for supplying the pulse signal π include a CR oscillator and a crystal oscillator.

Reference numeral 63 denotes a bit line driver, which is a latch circuit 6
A clocked CMOS inverter which controls activation and inactivation of one output node as a control signal θb. FIG. 7 is a write operation timing chart showing the write operation timing of the circuit of FIG. θb is the potential of the output node of the latch circuit 61, and the other is the same as that of FIG.

The write operation of this device will be described with reference to FIGS. As in the first embodiment,
When the data stored in the memory cell is the same as the write data, the same operation as in the conventional example is performed. If the two data are different, the same operation as in the conventional example is performed until the data is read from the memory cell and the bit line potential is amplified to the high level and the low level by the differential amplifier 11, but the subsequent operation is different. . That is, the result of the comparison circuit 30 is sent to the latch circuit 61, and the control signal .theta.b goes high, whereby the control signal of the cell plate driver 15 switches from .phi.c to the output Q1 of the frequency divider / counter 62, and the bit line The driver 63 is activated, and the divider / counter 62
And the counting of the pulse signal π is started. The control signal .theta.b is returned to the operation clock circuit, and the operation clock is temporarily stopped while .theta.b is at the high level. In this example, the potential of the bit line 8 is driven by the bit line driver 63 to invert the latch data of the differential amplifier 11, and a potential opposite to that of the bit line 8 is applied to the bit line 7 by the differential amplifier 11. However, there is no problem if the differential amplifier 11 is deactivated and the two bit line drivers are connected to both the bit lines 7 and 8 to drive the bit line potential.

While the control signal θb is at the high level, the operation of changing the potential of the cell plate twice while the change of the potential of the bit lines 7 and 8 makes one cycle as shown in FIG. 7 is repeated. Since the word line 5 remains at the high level, the voltage is continuously applied to the ferroelectric capacitors 1 and 2 once in the opposite direction, and the reversal of the polarization is repeated. Therefore, when the voltage-charge amount curve of the ferroelectric capacitor is biased as shown in FIG. 11, the characteristics change so that the bias is reduced. When a fixed number of pulses are input to the frequency divider / counter 62, the output / Q4 becomes high level, and the output .theta.b of the latch circuit 61 is precharged to low level. As a result, the cell plate driver 15
Is returned to φc, the bit line driver 63 becomes inactive, and the frequency divider / counter 62 enters the preset state. Further, the advance of the operation clock signal is resumed, and thereafter the write operation as in the conventional example is performed. As described above, the bias of the voltage-charge amount characteristic of the ferroelectric capacitor can be eliminated by repeating the polarization inversion, and the deterioration of the retention can be prevented. Further, it is advantageous in terms of fatigue of the ferroelectric film due to polarization reversal, as compared with the case where the ferroelectric capacitor is always refreshed.

As described above, according to this embodiment,
When the storage data and the write data are different, the reversal of the voltage applied to the ferroelectric of the memory cell is repeated before the start of the write operation to perform the polarization inversion of the ferroelectric of the memory cell. The bias in the voltage-charge amount curve can be recovered by canceling the change in the generated characteristics, and as a result, the deterioration of the retention characteristics due to the decrease in the residual charges can be prevented. In addition, the polarization inversion of the ferroelectric of the memory cell is performed when the storage data and the write data are different, and is not performed when the two data are the same. The shortening of life can be reduced.

In the above embodiment, 2Tr-2C (2
Transistor-2Capacitance) type memory cells have been described, but all of those examples are 1Tr-1C (1Transi
It can also be applied to (stor-1 Capacitance) type memory cells.
It operates as a 1Tr-1C type memory device by removing the ferroelectric capacitance 2 and the NMOS transistor 4 in FIG. 8, FIG. 1, FIG. 4 and FIG. That is clear. However, in the case of the 1Tr-1C type, the determination of whether the data is at the high level or the low level is made by comparing the data with the reference potential. This is a more serious problem as compared with the 2Tr-2C type in which the low level is determined, and the present invention is particularly effective. That is, FIG.
Regarding the prevention of the imprint phenomenon as shown in (1), it is the same in both cases, but the 1Tr-1C type is more strongly affected by the imprint phenomenon due to the difference in the determination method for data reading, and Therefore, it is particularly effective to apply the present invention, since the data retention ability (retention characteristic) is greatly influenced by the data retention ability.

[0048]

According to the semiconductor memory device of the present invention, when writing data reverse to data stored in a memory cell, the time for applying a write voltage is increased, the write voltage is increased, or the write voltage is increased. Refreshing by periodically inverting the voltage to be applied to the ferroelectric capacitor before entering the operation to remove the bias of the voltage-charge amount curve, thus preventing deterioration of the retention characteristics. Can be. In addition, the write data is compared with the stored data, and whether or not an operation for removing the bias of the voltage-charge amount curve of the ferroelectric capacitor is determined based on a result thereof. When performing the operation to eliminate the bias of the device, extra operations are reduced compared to the case where the refresh is always performed, the increase in power consumption is suppressed, the increase in cycle time is suppressed, and the fatigue of the ferroelectric film is suppressed. Can and is advantageous.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a memory cell peripheral circuit of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a write operation timing chart of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a conceptual diagram showing a voltage and a polarization direction of a ferroelectric capacitor during data storage and operation of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a memory cell peripheral circuit of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a write operation timing chart of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 6 is a circuit diagram of a memory cell peripheral circuit of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a write operation timing chart of the semiconductor memory device according to the third embodiment of the present invention.

FIG. 8 is a circuit diagram of a memory cell peripheral circuit of a conventional semiconductor memory device.

FIG. 9 is a timing chart of a read operation of a conventional semiconductor memory device.

FIG. 10 is a write operation timing diagram of a conventional semiconductor memory device.

FIG. 11 is a hysteresis characteristic diagram showing a voltage-charge amount curve of a ferroelectric capacitor.

[Explanation of symbols]

 1, 2 Ferroelectric capacitor 3, 4 NMOS transistor 5 Word line 6 Cell plate 7, 8 Bit line 9, 10 Data line 11 Differential amplifier 12 Transfer gate 13 Latch circuit 14 Word line driver 15 Cell plate driver 30 Comparison circuit 31 Write operation control circuits 32, 33 Fall delay circuit 34 Transfer gate 35 Latch circuit 36 Transfer gate 50 Write operation control circuit 51 Word line driver 52 Cell plate driver 53 Latch circuit 56 Differential amplifier 58, 59 Delay circuit 60 Write operation control circuit 61 Latch circuit 62 Divider and counter 63 Bit line driver

Claims (3)

[Claims] 1. A memory cell using a dielectric capacitor, a bit line, a data line, and storage data read from the memory cell to the bit line and write data input to the data line are compared. A semiconductor memory device comprising: a comparison circuit that performs the above operation; and a control circuit that increases the application time of a write voltage applied to the memory cell when the storage data differs from the write data based on a signal from the comparison circuit. 2. A memory cell using a dielectric capacitor, a bit line, a data line, and comparison between storage data read from the memory cell to the bit line and write data input to the data line. And a control circuit for increasing a write voltage applied to the memory cell when the storage data and the write data are different based on a signal from the comparison circuit. 3. A memory cell using a dielectric capacitor, a bit line, a data line, and comparing storage data read from the memory cell to the bit line and write data input to the data line. And a reversal of a voltage applied to the ferroelectric material of the memory cell before a write operation is performed by applying a write voltage when the storage data and the write data are different based on a signal from the comparison circuit. And a control circuit for repeating the polarization reversal of the ferroelectric of the memory cell.