JPH1084111A - High voltage MOS transistor - Google Patents
High voltage MOS transistorInfo
- Publication number
- JPH1084111A JPH1084111A JP8236050A JP23605096A JPH1084111A JP H1084111 A JPH1084111 A JP H1084111A JP 8236050 A JP8236050 A JP 8236050A JP 23605096 A JP23605096 A JP 23605096A JP H1084111 A JPH1084111 A JP H1084111A
- Authority
- JP
- Japan
- Prior art keywords
- type diffusion
- diffusion layer
- conductivity type
- type
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/01—Manufacture or treatment
- H10D62/051—Forming charge compensation regions, e.g. superjunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【課題】 高耐圧特性を維持しながら、オン抵抗を下げ
て動作速度を向上できる高耐圧ＭＯＳトランジスタを実
現する。
【解決手段】 Ｎ型ウエル２の表面に形成されＬＯＣＯ
Ｓ酸化膜５で覆われたＰ型拡散層３をチャネル長方向断
面において複数に分割し、その分割したＰ型拡散層３の
間に、Ｎ型ウエル２より不純物濃度の高いＮ型拡散層４
を、Ｐ型拡散層３と同じ深さかそれよりも浅く形成して
いる。複数個のＰ型拡散層３から延びた空乏層は互いに
影響して耐圧としては低下することなく、高耐圧特性を
維持できる。また、トランジスタがオンしたとき、Ｐ型
拡散層３の間にＮ型拡散層４を配置したことによりチャ
ネル抵抗が低減し、トランジスタの動作速度を向上する
ことができる。
(57) [PROBLEMS] To provide a high withstand voltage MOS transistor capable of improving the operating speed by lowering the on-resistance while maintaining high withstand voltage characteristics. SOLUTION: LOCO formed on the surface of an N-type well 2 is provided.
The P-type diffusion layer 3 covered with the S oxide film 5 is divided into a plurality of sections in a channel length direction cross section, and the N-type diffusion layer 4 having an impurity concentration higher than that of the N-type well 2 is provided between the divided P-type diffusion layers 3.
Is formed at the same depth as the P-type diffusion layer 3 or shallower than that. The depletion layers extending from the plurality of P-type diffusion layers 3 can maintain high withstand voltage characteristics without affecting each other and reducing the withstand voltage. Further, when the transistor is turned on, the channel resistance is reduced by disposing the N-type diffusion layer 4 between the P-type diffusion layers 3, and the operation speed of the transistor can be improved.
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、高耐圧ＭＯＳト
ランジスタに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage MOS transistor.
【０００２】[0002]
【従来の技術】従来の高耐圧ＭＯＳトランジスタについ
て図３を参照しながら説明する。図３は従来の高耐圧Ｍ
ＯＳトランジスタの断面構造図である。図３において、
１はＰ型シリコン基板、２はＮ型ウエル、３はＰ型拡散
層、５はＬＯＣＯＳ酸化膜、６はゲート電極、７はＮ型
ドレイン領域、８はＮ型ソース領域、９は層間絶縁膜、
１０はドレイン電極、１１はソース電極、１２はＰＳＧ
（燐・シリケート・ガラス）膜、１３はポリイミド膜で
ある。2. Description of the Related Art A conventional high voltage MOS transistor will be described with reference to FIG. FIG. 3 shows a conventional high withstand voltage M
FIG. 3 is a cross-sectional structure diagram of an OS transistor. In FIG.
1 is a P-type silicon substrate, 2 is an N-type well, 3 is a P-type diffusion layer, 5 is a LOCOS oxide film, 6 is a gate electrode, 7 is an N-type drain region, 8 is an N-type source region, and 9 is an interlayer insulating film. ,
10 is a drain electrode, 11 is a source electrode, 12 is PSG
A (phosphorus silicate glass) film 13 is a polyimide film.
【０００３】この従来の高耐圧ＭＯＳトランジスタは、
Ｐ型シリコン基板１の表面にＮ型ソース領域８とＮ型ウ
エル２を設け、Ｎ型ウエル２の表面にＰ型拡散層３とＮ
型ドレイン領域７を設け、Ｐ型拡散層３上をＬＯＣＯＳ
酸化膜５で覆ってあり、Ｎ型ソース領域８の端部上から
ＬＯＣＯＳ酸化膜５上にかけてゲート酸化膜を介してゲ
ート電極６を設けている。そして、層間絶縁膜９のコン
タクトホールを介してＮ型ドレイン領域７，Ｎ型ソース
領域８上にそれぞれドレイン電極１０，ソース電極１１
を設け、保護膜としてＰＳＧ膜１２およびポリイミド膜
１３を設けている。[0003] This conventional high withstand voltage MOS transistor,
An N-type source region 8 and an N-type well 2 are provided on the surface of a P-type silicon substrate 1, and a P-type diffusion layer 3 and an N-type
And a LOCOS is formed on the P-type diffusion layer 3.
The gate electrode 6 is covered by the oxide film 5 and extends from the end of the N-type source region 8 to the LOCOS oxide film 5 via the gate oxide film. Then, the drain electrode 10 and the source electrode 11 are formed on the N-type drain region 7 and the N-type source region 8 through the contact holes of the interlayer insulating film 9, respectively.
And a PSG film 12 and a polyimide film 13 are provided as protective films.
【０００４】この構成では、Ｐ型拡散層３をソース電極
１１と同電位にすることにより、Ｐ型拡散層３とＮ型ウ
エル２が両方から空乏化して高耐圧化できるようになっ
ている。また、トランジスタがオンした場合には、Ｐ型
拡散層３直下のＮ型ウエル２がチャネルとなる。In this configuration, by setting the P-type diffusion layer 3 to the same potential as the source electrode 11, the P-type diffusion layer 3 and the N-type well 2 are depleted from both, so that a high breakdown voltage can be achieved. When the transistor is turned on, the N-type well 2 immediately below the P-type diffusion layer 3 becomes a channel.
【０００５】[0005]
【発明が解決しようとする課題】このような従来の高耐
圧ＭＯＳトランジスタでは、トランジスタがオンになっ
た場合、ドレイン部のオン抵抗がＰ型拡散層３直下のＮ
型ウエル２の抵抗で決定されるために、チャネル部の不
純物濃度が低くなるとオン抵抗が高くなり、トランジス
タの動作速度を決定する一因であるオン電流が小さくな
り、動作速度が遅くなるという課題があった。In such a conventional high withstand voltage MOS transistor, when the transistor is turned on, the on-resistance of the drain portion is reduced to the N-type level just below the P-type diffusion layer 3.
Since the resistance is determined by the resistance of the mold well 2, when the impurity concentration in the channel portion is low, the on-resistance is high, and the on-current, which is a factor in determining the operation speed of the transistor, is small, and the operation speed is low. was there.
【０００６】この発明は上記課題を解決するもので、高
耐圧特性を維持しながら、オン抵抗を下げて動作速度を
向上することができる高耐圧ＭＯＳトランジスタを提供
することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide a high-breakdown-voltage MOS transistor capable of improving the operating speed by lowering the on-resistance while maintaining high withstand voltage characteristics.
【０００７】[0007]
【課題を解決するための手段】請求項１記載の高耐圧Ｍ
ＯＳトランジスタは、第１導電型半導体基板の表面に第
２導電型ソース領域と第２導電型ウエルを設け、第２導
電型ウエルの表面に第１導電型拡散層と第２導電型ドレ
イン領域を設け、第１導電型拡散層上をＬＯＣＯＳ酸化
膜で覆い、第２導電型ソース領域の端部上からＬＯＣＯ
Ｓ酸化膜上にかけてゲート酸化膜を介してゲート電極を
設けた高耐圧ＭＯＳトランジスタであって、第１導電型
拡散層をチャネル長方向断面において複数に分割し、こ
の分割した第１導電型拡散層の間に第２導電型拡散層を
第１導電型拡散層と同じまたは浅い深さに設けたことを
特徴とする。A high withstand voltage M according to claim 1
In the OS transistor, a second conductivity type source region and a second conductivity type well are provided on a surface of a first conductivity type semiconductor substrate, and a first conductivity type diffusion layer and a second conductivity type drain region are formed on a surface of the second conductivity type well. The first conductive type diffusion layer is covered with a LOCOS oxide film, and the LOCOS oxide film is formed on the end of the second conductive type source region.
A high breakdown voltage MOS transistor in which a gate electrode is provided on an S oxide film via a gate oxide film, wherein the first conductivity type diffusion layer is divided into a plurality in a channel length direction cross section, and the divided first conductivity type diffusion layer The second conductive type diffusion layer is provided at the same or shallower depth as the first conductive type diffusion layer.
【０００８】この構成によれば、第２導電型ウエルの表
面に形成された第１導電型拡散層をチャネル長方向断面
において複数に分割し、この分割した第１導電型拡散層
の間に第２導電型拡散層を設けたことにより、高耐圧特
性を維持しながら、トランジスタがオンしたときのチャ
ネル抵抗を低減することができ、トランジスタの動作速
度を向上することができる。According to this structure, the first conductivity type diffusion layer formed on the surface of the second conductivity type well is divided into a plurality of sections in the channel length direction cross section, and the first conductivity type diffusion layer is provided between the divided first conductivity type diffusion layers. By providing the two-conductivity type diffusion layer, the channel resistance when the transistor is turned on can be reduced while the high withstand voltage characteristics are maintained, and the operation speed of the transistor can be improved.
【０００９】請求項２記載の高耐圧ＭＯＳトランジスタ
は、請求項１記載の高耐圧ＭＯＳトランジスタにおい
て、第２導電型拡散層は第１導電型拡散層と同じまたは
浅い深さにしている。このように、第１導電型拡散層の
間に設けた第２導電型拡散層を、第１導電型拡散層と同
じまたは浅い深さとすることにより、第１導電型拡散層
からの空乏層が第２導電型拡散層の下部領域に拡がりや
すく、空乏化がより均一に行われ、高耐圧化に、より効
果がある。According to a second aspect of the present invention, there is provided a high breakdown voltage MOS transistor according to the first aspect, wherein the second conductivity type diffusion layer has the same depth as the first conductivity type diffusion layer. As described above, by setting the second conductivity type diffusion layer provided between the first conductivity type diffusion layers to have the same or shallow depth as the first conductivity type diffusion layer, the depletion layer from the first conductivity type diffusion layer is reduced. It is easy to spread to the lower region of the second conductivity type diffusion layer, the depletion is performed more uniformly, and the higher withstand voltage is more effective.
【００１０】請求項３記載の高耐圧ＭＯＳトランジスタ
は、請求項１または２記載の高耐圧ＭＯＳトランジスタ
において、第２導電型拡散層は第２導電型ウエルより不
純物濃度を高くしている。このように、第１導電型拡散
層の間に設けた第２導電型拡散層の不純物濃度を第２導
電型ウエルより高くすることにより、トランジスタがオ
ンしたときのチャネル抵抗をより低減することができ、
トランジスタの動作速度をより向上することができる。According to a third aspect of the present invention, there is provided a high breakdown voltage MOS transistor according to the first or second aspect, wherein the second conductivity type diffusion layer has an impurity concentration higher than that of the second conductivity type well. As described above, by making the impurity concentration of the second conductivity type diffusion layer provided between the first conductivity type diffusion layers higher than that of the second conductivity type well, the channel resistance when the transistor is turned on can be further reduced. Can,
The operation speed of the transistor can be further improved.
【００１１】[0011]
【発明の実施の形態】以下、この発明の実施の形態につ
いて図面を参照しながら説明する。図１はこの発明の実
施の形態における高耐圧ＭＯＳトランジスタの断面構造
図である。図１において、１はＰ型シリコン基板（第１
導電型半導体基板）、２はＮ型ウエル（第２導電型ウエ
ル）、３はＰ型拡散層（第１導電型拡散層）、４はＮ型
拡散層（第２導電型拡散層）、５はＬＯＣＯＳ酸化膜、
６はゲート電極、７はＮ型ドレイン領域、８はＮ型ソー
ス領域、９は層間絶縁膜、１０はドレイン電極、１１は
ソース電極、１２はＰＳＧ（燐・シリケート・ガラス）
膜、１３はポリイミド膜である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional structural view of a high voltage MOS transistor according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a P-type silicon substrate (first
A conductive type semiconductor substrate), 2 an N-type well (second conductive type well), 3 a P-type diffused layer (first conductive type diffused layer), 4 an N-type diffused layer (second conductive type diffused layer), 5 Is a LOCOS oxide film,
6 is a gate electrode, 7 is an N-type drain region, 8 is an N-type source region, 9 is an interlayer insulating film, 10 is a drain electrode, 11 is a source electrode, and 12 is PSG (phosphorus silicate glass).
The film 13 is a polyimide film.
【００１２】この高耐圧ＭＯＳトランジスタは、Ｎ型ウ
エル２の表面に形成されＬＯＣＯＳ酸化膜５で覆われた
Ｐ型拡散層３をチャネル長方向断面において複数に分割
し、その分割したＰ型拡散層３の間にＮ型ウエル２より
不純物濃度の高いＮ型拡散層４をＰ型拡散層３と同じ深
さかそれよりも浅く形成したことを特徴とし、その他の
構成は図３に示す従来例と同様である。In this high breakdown voltage MOS transistor, the P-type diffusion layer 3 formed on the surface of the N-type well 2 and covered with the LOCOS oxide film 5 is divided into a plurality of sections in the channel length direction, and the divided P-type diffusion layers are divided. 3 is characterized in that an N-type diffusion layer 4 having an impurity concentration higher than that of the N-type well 2 is formed at the same depth as the P-type diffusion layer 3 or shallower than the P-type diffusion layer 3. The same is true.
【００１３】この高耐圧ＭＯＳトランジスタの製造方法
について、図２の工程順断面図を参照しながら説明して
おく。図２（ａ）に示すように、Ｐ型シリコン基板１の
表面にＮ型ウエル２をイオン注入と熱処理により形成す
る。つぎに、図２（ｂ）に示すように、Ｎ型ウエル２内
の表面に、Ｐ型拡散層３とＮ型拡散層４をイオン注入と
熱処理により形成する。このＰ型拡散層３とＮ型拡散層
４は、例えば、Ｐ型拡散層用のマスクを用いてボロン注
入を行い、Ｐ型拡散層用のマスクを除去し、つぎにＮ型
拡散層用のマスクを用いてリン注入を行い、ドライブイ
ン処理することにより形成する。A method of manufacturing this high voltage MOS transistor will be described with reference to the sectional views in the order of steps shown in FIG. As shown in FIG. 2A, an N-type well 2 is formed on the surface of a P-type silicon substrate 1 by ion implantation and heat treatment. Next, as shown in FIG. 2B, a P-type diffusion layer 3 and an N-type diffusion layer 4 are formed on the surface in the N-type well 2 by ion implantation and heat treatment. For example, boron is implanted into the P-type diffusion layer 3 and the N-type diffusion layer 4 using a mask for the P-type diffusion layer, and the mask for the P-type diffusion layer is removed. It is formed by performing phosphorus implantation using a mask and performing drive-in processing.
【００１４】つぎに、図２（ｃ）に示すように、Ｐ型拡
散層３とＮ型拡散層４を覆うようにＬＯＣＯＳ酸化膜５
を形成する。つぎに、図２（ｄ）に示すように、ＬＯＣ
ＯＳ酸化膜５の端を含む領域に酸化膜を介してゲート電
極６を形成した後、Ｎ型ドレイン領域７およびＮ型ソー
ス領域８をイオン注入により形成する。つぎに、図２
（ｅ）に示すように、層間絶縁膜９を形成した後、コン
タクトホールを設けてドレイン電極１０およびソース電
極１１を形成する。最後に、図２（ｆ）に示すように、
保護膜としてＰＳＧ膜１２およびポリイミド膜１３を形
成する。Next, as shown in FIG. 2C, a LOCOS oxide film 5 is formed so as to cover the P-type diffusion layer 3 and the N-type diffusion layer 4.
To form Next, as shown in FIG.
After forming the gate electrode 6 in the region including the end of the OS oxide film 5 via the oxide film, the N-type drain region 7 and the N-type source region 8 are formed by ion implantation. Next, FIG.
As shown in (e), after the interlayer insulating film 9 is formed, a contact hole is provided and a drain electrode 10 and a source electrode 11 are formed. Finally, as shown in FIG.
A PSG film 12 and a polyimide film 13 are formed as protective films.
【００１５】以上のようにこの実施の形態によれば、Ｎ
型ウエル２の表面に形成されるＰ型拡散層３をチャネル
長方向断面において複数に分割し、Ｐ型拡散層３の間に
Ｐ型拡散層３と同じまたは浅い深さのＮ型拡散層４を形
成している。この実施の形態では、Ｎ型ウエル２の濃度
は約１×１０16ｃｍ-3であり、Ｎ型拡散層４の表面濃度
は約２×１０16ｃｍ-3、Ｐ型拡散層３の表面濃度は約４
×１０16ｃｍ-3である。そして、Ｐ型拡散層３はソース
電極１１と同電位になるように接続されている。この構
成によれば、複数個のＰ型拡散層３から延びた空乏層は
互いに影響し、最終的には図３の従来例と同様になり、
耐圧としては低下することはなく、高耐圧特性を維持で
きる。また、トランジスタがオンしたとき、チャネル部
分は、Ｎ型ウエル２だけでなくＮ型拡散層４の一部分ま
で含まれることから、Ｐ型拡散層３のある部分とＮ型拡
散層４のある部分とではチャネル部分の断面積と不純物
濃度が異なり、全体として見た場合、従来例に比べてチ
ャネル抵抗が低減する。その結果、トランジスタの動作
速度を向上することができる。As described above, according to this embodiment, N
The P-type diffusion layer 3 formed on the surface of the mold well 2 is divided into a plurality of sections in the cross section in the channel length direction, and an N-type diffusion layer 4 having the same or shallow depth as the P-type diffusion layer 3 is formed between the P-type diffusion layers 3. Is formed. In this embodiment, the concentration of the N-type well 2 is about 1 × 10 16 cm −3 , the surface concentration of the N-type diffusion layer 4 is about 2 × 10 16 cm −3 , and the surface concentration of the P-type diffusion layer 3 Is about 4
× 10 16 cm -3 . The P-type diffusion layer 3 is connected to have the same potential as the source electrode 11. According to this configuration, the depletion layers extending from the plurality of P-type diffusion layers 3 affect each other, and eventually become the same as the conventional example of FIG.
The withstand voltage does not decrease, and high withstand voltage characteristics can be maintained. Further, when the transistor is turned on, the channel portion is included not only in the N-type well 2 but also in a portion of the N-type diffusion layer 4, so that the channel portion includes the P-type diffusion layer 3 and the N-type diffusion layer 4. In this case, the cross-sectional area of the channel portion and the impurity concentration are different, and when viewed as a whole, the channel resistance is reduced as compared with the conventional example. As a result, the operation speed of the transistor can be improved.
【００１６】なお、Ｎ型拡散層４を、Ｐ型拡散層３と同
じまたは浅い深さにした理由は、Ｐ型拡散層３からの空
乏層がＮ型拡散層４の下部領域に拡がりやすく、空乏化
がより均一に行われ、高耐圧化を実現するうえで好まし
いからであり、もしＮ型拡散層４がＰ型拡散層３より深
い領域にまで形成されていると、Ｐ型拡散層３から延び
た空乏層がＮ型拡散層４の下部で狭くなり、耐圧が下が
ることになる。The reason why the N-type diffusion layer 4 has the same or shallow depth as the P-type diffusion layer 3 is that the depletion layer from the P-type diffusion layer 3 easily spreads to the lower region of the N-type diffusion layer 4. This is because the depletion is more uniformly performed and it is preferable to realize a high breakdown voltage. If the N-type diffusion layer 4 is formed to a region deeper than the P-type diffusion layer 3, the P-type diffusion layer 3 The depletion layer extending from the N-type diffusion layer 4 becomes narrower below the N-type diffusion layer 4, and the breakdown voltage decreases.
【００１７】なお、この実施の形態では、Ｎ型ウエル２
内に形成したＮ型拡散層４を、Ｐ型拡散層３と接するよ
うに配置したが、Ｐ型拡散層３の間にＰ型拡散層３と離
して配置してもよい。また、各Ｐ型拡散層３および各Ｎ
型拡散層４はそれぞれ同じ形状にする必要はない。ま
た、高耐圧構造によく用いられる構造にも適用でき、島
状のＮ型ドレイン領域７を中心としてその周りにＬＯＣ
ＯＳ酸化膜５をリング状に配置し、そのリング状のＬＯ
ＣＯＳ酸化膜５の下部に、同じくリング状のＰ型拡散層
３とＮ型拡散層４とを交互に配置するようにしてもよ
い。In this embodiment, the N-type well 2
Although the N-type diffusion layer 4 formed therein is arranged so as to be in contact with the P-type diffusion layer 3, it may be arranged between the P-type diffusion layers 3 so as to be separated from the P-type diffusion layer 3. Further, each P-type diffusion layer 3 and each N
The mold diffusion layers 4 do not need to have the same shape. In addition, the present invention can be applied to a structure often used for a high withstand voltage structure.
The OS oxide film 5 is arranged in a ring shape, and the ring-shaped LO
A ring-shaped P-type diffusion layer 3 and an N-type diffusion layer 4 may be alternately arranged below the COS oxide film 5.
【００１８】また、保護膜としてＰＳＧ膜１２とポリイ
ミド膜１３を使用したが、特に限定されたものではな
い。なお、この実施の形態では、Ｐ型半導体基板を用い
たが、Ｎ型半導体基板を用い、各領域の導電型を逆にし
てもよい。Although the PSG film 12 and the polyimide film 13 are used as the protective films, they are not particularly limited. In this embodiment, a P-type semiconductor substrate is used, but an N-type semiconductor substrate may be used and the conductivity type of each region may be reversed.
【００１９】[0019]
【発明の効果】以上のようにこの発明によれば、第２導
電型ウエルの表面に形成されＬＯＣＯＳ酸化膜で覆われ
た第１導電型拡散層をチャネル長方向断面において複数
に分割し、この分割した第１導電型拡散層の間に第２導
電型拡散層を設けたことにより、高耐圧特性を維持しな
がら、トランジスタがオンしたときのチャネル抵抗を低
減することができ、トランジスタの動作速度を向上する
ことができる。As described above, according to the present invention, the first conductivity type diffusion layer formed on the surface of the second conductivity type well and covered with the LOCOS oxide film is divided into a plurality in the channel length direction cross section. By providing the second conductivity type diffusion layer between the divided first conductivity type diffusion layers, the channel resistance when the transistor is turned on can be reduced while maintaining high breakdown voltage characteristics, and the operation speed of the transistor can be reduced. Can be improved.
【００２０】さらに、第１導電型拡散層の間に設けた第
２導電型拡散層を、第１導電型拡散層と同じまたは浅い
深さとすることにより、第１導電型拡散層からの空乏層
が第２導電型拡散層の下部領域に拡がりやすく、空乏化
がより均一に行われ、高耐圧化に、より効果がある。ま
た、第２導電型拡散層の不純物濃度を第２導電型ウエル
より高くすることにより、トランジスタがオンしたとき
のチャネル抵抗をより低減することができ、トランジス
タの動作速度をより向上することができる。Further, by making the second conductivity type diffusion layer provided between the first conductivity type diffusion layers the same or shallower as the first conductivity type diffusion layer, a depletion layer from the first conductivity type diffusion layer is formed. Are easily spread to the lower region of the second conductivity type diffusion layer, depletion is performed more uniformly, and this is more effective in increasing the breakdown voltage. Further, by setting the impurity concentration of the second conductivity type diffusion layer higher than that of the second conductivity type well, the channel resistance when the transistor is turned on can be further reduced, and the operation speed of the transistor can be further improved. .
【図面の簡単な説明】[Brief description of the drawings]
【図１】この発明の実施の形態における高耐圧ＭＯＳト
ランジスタの断面構造図。FIG. 1 is a sectional structural view of a high-voltage MOS transistor according to an embodiment of the present invention.
【図２】この発明の実施の形態における製造工程を示す
断面図。FIG. 2 is a sectional view showing a manufacturing process according to the embodiment of the present invention.
【図３】従来の高耐圧ＭＯＳトランジスタの断面構造
図。FIG. 3 is a sectional structural view of a conventional high-breakdown-voltage MOS transistor.
１ Ｐ型シリコン基板（第１導電型半導体基板） ２ Ｎ型ウエル（第２導電型ウエル） ３ Ｐ型拡散層（第１導電型拡散層） ４ Ｎ型拡散層（第２導電型拡散層） ５ ＬＯＣＯＳ酸化膜 ６ ゲート電極 ７ Ｎ型ドレイン領域 ８ Ｎ型ソース領域 ９ 層間絶縁膜 １０ ドレイン電極 １１ ソース電極 １２ ＰＳＧ膜 １３ ポリイミド膜 Reference Signs List 1 P-type silicon substrate (first conductivity type semiconductor substrate) 2 N-type well (second conductivity type well) 3 P-type diffusion layer (first conductivity type diffusion layer) 4 N-type diffusion layer (second conductivity type diffusion layer) Reference Signs List 5 LOCOS oxide film 6 Gate electrode 7 N-type drain region 8 N-type source region 9 Interlayer insulating film 10 Drain electrode 11 Source electrode 12 PSG film 13 Polyimide film
Claims (3)
型ソース領域と第２導電型ウエルを設け、前記第２導電
型ウエルの表面に第１導電型拡散層と第２導電型ドレイ
ン領域を設け、前記第１導電型拡散層上をＬＯＣＯＳ酸
化膜で覆い、前記第２導電型ソース領域の端部上から前
記ＬＯＣＯＳ酸化膜上にかけてゲート酸化膜を介してゲ
ート電極を設けた高耐圧ＭＯＳトランジスタであって、 前記第１導電型拡散層をチャネル長方向断面において複
数に分割し、この分割した前記第１導電型拡散層の間に
第２導電型拡散層を設けたことを特徴とする高耐圧ＭＯ
Ｓトランジスタ。A second conductivity type source region and a second conductivity type well provided on a surface of the first conductivity type semiconductor substrate; a first conductivity type diffusion layer and a second conductivity type drain on the surface of the second conductivity type well; A high withstand voltage, wherein a region is provided, the first conductivity type diffusion layer is covered with a LOCOS oxide film, and a gate electrode is provided from the end of the second conductivity type source region to the LOCOS oxide film via a gate oxide film. A MOS transistor, wherein the first conductivity type diffusion layer is divided into a plurality in a channel length direction cross section, and a second conductivity type diffusion layer is provided between the divided first conductivity type diffusion layers. High withstand voltage MO
S transistor.
同じまたは浅い深さにした請求項１記載の高耐圧ＭＯＳ
トランジスタ。2. The high breakdown voltage MOS according to claim 1, wherein the second conductivity type diffusion layer has the same or shallow depth as the first conductivity type diffusion layer.
Transistor.
り不純物濃度を高くした請求項１または２記載の高耐圧
ＭＯＳトランジスタ。3. The high breakdown voltage MOS transistor according to claim 1, wherein the second conductivity type diffusion layer has a higher impurity concentration than the second conductivity type well.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23605096A JP3193984B2 (en) | 1996-09-06 | 1996-09-06 | High voltage MOS transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23605096A JP3193984B2 (en) | 1996-09-06 | 1996-09-06 | High voltage MOS transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1084111A true JPH1084111A (en) | 1998-03-31 |
| JP3193984B2 JP3193984B2 (en) | 2001-07-30 |
Family
ID=16995013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23605096A Expired - Fee Related JP3193984B2 (en) | 1996-09-06 | 1996-09-06 | High voltage MOS transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3193984B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6312996B1 (en) | 1998-10-19 | 2001-11-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6534829B2 (en) | 1998-06-25 | 2003-03-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2008034738A (en) * | 2006-07-31 | 2008-02-14 | Sanyo Electric Co Ltd | Semiconductor device |
| CN102694008A (en) * | 2011-03-22 | 2012-09-26 | 立锜科技股份有限公司 | High voltage component and manufacturing method thereof |
-
1996
- 1996-09-06 JP JP23605096A patent/JP3193984B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6534829B2 (en) | 1998-06-25 | 2003-03-18 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| US6312996B1 (en) | 1998-10-19 | 2001-11-06 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2008034738A (en) * | 2006-07-31 | 2008-02-14 | Sanyo Electric Co Ltd | Semiconductor device |
| CN102694008A (en) * | 2011-03-22 | 2012-09-26 | 立锜科技股份有限公司 | High voltage component and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3193984B2 (en) | 2001-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100363353B1 (en) | Semiconductor device and manufacturing method thereof | |
| US6614075B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP3185656B2 (en) | Lateral field effect transistor and method of manufacturing the same | |
| JPH0897411A (en) | Lateral high breakdown voltage trench MOSFET and manufacturing method thereof | |
| JP2000286346A (en) | Semiconductor device and manufacturing method thereof | |
| JP2000188391A (en) | Method for manufacturing semiconductor integrated circuit device | |
| KR880002245A (en) | Integrated circuit comprising bipolar transistor and complementary MOS transistor on common substrate and manufacturing method thereof | |
| JPH08107202A (en) | Lateral high breakdown voltage field effect transistor and method of manufacturing the same | |
| JP2001308321A (en) | Semiconductor device and manufacturing method thereof | |
| JPH11251597A (en) | Semiconductor device | |
| JPH0846196A (en) | MOS transistor and manufacturing method thereof | |
| JP3642768B2 (en) | Horizontal high voltage semiconductor device | |
| JP3193984B2 (en) | High voltage MOS transistor | |
| JP2004031805A (en) | Semiconductor device and manufacturing method thereof | |
| JP4677166B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3363810B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2834058B2 (en) | Method for manufacturing semiconductor device | |
| JP2001060634A (en) | Semiconductor device and manufacture thereof | |
| JPH0758776B2 (en) | Composite semiconductor device | |
| JP2000068499A (en) | Semiconductor device and manufacture of the same | |
| JPH06268162A (en) | Semiconductor device and its manufacture | |
| JPH11186402A (en) | Semiconductor device and manufacture of semiconductor | |
| JP2004063918A (en) | Lateral mos transistor | |
| JP2807718B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3031282B2 (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |